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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: qemu-devel@nongnu.org, "Marcel Apfelbaum" <marcel@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	linux-cxl@vger.kernel.org,
	"Ben Widawsky" <ben.widawsky@intel.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	linuxarm@huawei.com,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Saransh Gupta1" <saransh@ibm.com>,
	"Shreyas Shah" <shreyas.shah@elastics.cloud>,
	"Chris Browy" <cbrowy@avery-design.com>,
	"Samarth Saxena" <samarths@cadence.com>,
	"Dan Williams" <dan.j.williams@intel.com>
Subject: Re: [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA)
Date: Wed, 02 Mar 2022 10:03:34 +0000	[thread overview]
Message-ID: <87wnhck6oi.fsf@linaro.org> (raw)
In-Reply-To: <20220211120747.3074-23-Jonathan.Cameron@huawei.com>


Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:

> From: Ben Widawsky <ben.widawsky@intel.com>
>
> Implement get and set handlers for the Label Storage Area
> used to hold data describing persistent memory configuration
> so that it can be ensured it is seen in the same configuration
> after reboot.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  hw/cxl/cxl-mailbox-utils.c  | 57 +++++++++++++++++++++++++++++++++++++
>  hw/mem/cxl_type3.c          | 56 +++++++++++++++++++++++++++++++++++-
>  include/hw/cxl/cxl_device.h |  5 ++++
>  3 files changed, 117 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index ccf9c3d794..f4a309ddbf 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -56,6 +56,8 @@ enum {
>          #define MEMORY_DEVICE 0x0
>      CCLS        = 0x41,
>          #define GET_PARTITION_INFO     0x0
> +        #define GET_LSA       0x2
> +        #define SET_LSA       0x3
>  };
>  
>  /* 8.2.8.4.5.1 Command Return Codes */
> @@ -327,7 +329,59 @@ static ret_code cmd_ccls_get_partition_info(struct cxl_cmd *cmd,
>      return CXL_MBOX_SUCCESS;
>  }
>  
> +static ret_code cmd_ccls_get_lsa(struct cxl_cmd *cmd,
> +                                 CXLDeviceState *cxl_dstate,
> +                                 uint16_t *len)
> +{
> +    struct {
> +        uint32_t offset;
> +        uint32_t length;
> +    } __attribute__((packed, __aligned__(8))) *get_lsa;
> +    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
> +    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
> +    uint32_t offset, length;
> +
> +    get_lsa = (void *)cmd->payload;
> +    offset = get_lsa->offset;
> +    length = get_lsa->length;
> +
> +    *len = 0;

This can drop into the failure leg.

> +    if (offset + length > cvc->get_lsa_size(ct3d)) {
> +        return CXL_MBOX_INVALID_INPUT;
> +    }
> +
> +    *len = cvc->get_lsa(ct3d, get_lsa, length, offset);
> +    return CXL_MBOX_SUCCESS;
> +}
> +
> +static ret_code cmd_ccls_set_lsa(struct cxl_cmd *cmd,
> +                                 CXLDeviceState *cxl_dstate,
> +                                 uint16_t *len)
> +{
> +    struct {
> +        uint32_t offset;
> +        uint32_t rsvd;
> +    } __attribute__((packed, __aligned__(8))) *set_lsa = (void *)cmd->payload;
> +    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
> +    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
> +    uint16_t plen = *len;
> +
> +    *len = 0;
> +    if (!plen) {
> +        return CXL_MBOX_SUCCESS;
> +    }
> +
> +    if (set_lsa->offset + plen > cvc->get_lsa_size(ct3d) + sizeof(*set_lsa)) {
> +        return CXL_MBOX_INVALID_INPUT;
> +    }
> +
> +    cvc->set_lsa(ct3d, (void *)set_lsa + sizeof(*set_lsa),
> +                 plen - sizeof(*set_lsa), set_lsa->offset);

All these sizeof's make me wonder if these structures should be public
with a #define? Failing that having

  const size_t lsa_len = sizeof(*set_lsa);

and use that might make the flow a bit easier to scan. That said why
isn't set_lsa taking a type of *set_lsa instead of having void casts?

> +    return CXL_MBOX_SUCCESS;
> +}
> +
>  #define IMMEDIATE_CONFIG_CHANGE (1 << 1)
> +#define IMMEDIATE_DATA_CHANGE (1 << 2)
>  #define IMMEDIATE_POLICY_CHANGE (1 << 3)
>  #define IMMEDIATE_LOG_CHANGE (1 << 4)
>  
> @@ -350,6 +404,9 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
>          cmd_identify_memory_device, 0, 0 },
>      [CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
>          cmd_ccls_get_partition_info, 0, 0 },
> +    [CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 0, 0 },
> +    [CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa,
> +        ~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE },
>  };
>  
>  void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index b16262d3cc..b1ba4bf0de 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -8,6 +8,7 @@
>  #include "qapi/error.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> +#include "qemu/pmem.h"
>  #include "qemu/range.h"
>  #include "qemu/rcu.h"
>  #include "sysemu/hostmem.h"
> @@ -114,6 +115,11 @@ static void cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
>      memory_region_set_enabled(mr, true);
>      host_memory_backend_set_mapped(ct3d->hostmem, true);
>      ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size;
> +
> +    if (!ct3d->lsa) {
> +        error_setg(errp, "lsa property must be set");
> +        return;
> +    }
>  }
>  
>  
> @@ -168,12 +174,58 @@ static Property ct3_props[] = {
>      DEFINE_PROP_SIZE("size", CXLType3Dev, size, -1),
>      DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
>                       HostMemoryBackend *),
> +    DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
> +                     HostMemoryBackend *),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
>  static uint64_t get_lsa_size(CXLType3Dev *ct3d)
>  {
> -    return 0;
> +    MemoryRegion *mr;
> +
> +    mr = host_memory_backend_get_memory(ct3d->lsa);
> +    return memory_region_size(mr);
> +}
> +
> +static void validate_lsa_access(MemoryRegion *mr, uint64_t size,
> +                                uint64_t offset)
> +{
> +    assert(offset + size <= memory_region_size(mr));
> +    assert(offset + size > offset);
> +}
> +
> +static uint64_t get_lsa(CXLType3Dev *ct3d, void *buf, uint64_t size,
> +                    uint64_t offset)
> +{
> +    MemoryRegion *mr;
> +    void *lsa;
> +
> +    mr = host_memory_backend_get_memory(ct3d->lsa);
> +    validate_lsa_access(mr, size, offset);
> +
> +    lsa = memory_region_get_ram_ptr(mr) + offset;
> +    memcpy(buf, lsa, size);
> +
> +    return size;
> +}
> +
> +static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size,
> +                    uint64_t offset)
> +{
> +    MemoryRegion *mr;
> +    void *lsa;
> +
> +    mr = host_memory_backend_get_memory(ct3d->lsa);
> +    validate_lsa_access(mr, size, offset);
> +
> +    lsa = memory_region_get_ram_ptr(mr) + offset;
> +    memcpy(lsa, buf, size);
> +    memory_region_set_dirty(mr, offset, size);
> +
> +    /*
> +     * Just like the PMEM, if the guest is not allowed to exit gracefully, label
> +     * updates will get lost.
> +     */
>  }
>  
>  static void ct3_class_init(ObjectClass *oc, void *data)
> @@ -194,6 +246,8 @@ static void ct3_class_init(ObjectClass *oc, void *data)
>      device_class_set_props(dc, ct3_props);
>  
>      cvc->get_lsa_size = get_lsa_size;
> +    cvc->get_lsa = get_lsa;
> +    cvc->set_lsa = set_lsa;
>  }
>  
>  static const TypeInfo ct3d_info = {
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index ebb391153a..43908f161b 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -257,6 +257,11 @@ struct CXLType3Class {
>  
>      /* public */
>      uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
> +
> +    uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
> +                        uint64_t offset);
> +    void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
> +                    uint64_t offset);
>  };
>  
>  #endif


-- 
Alex Bennée

  reply	other threads:[~2022-03-02 10:08 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-11 12:07 [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 01/43] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 04/43] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-01 15:32   ` Alex Bennée
2022-03-03 16:31     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 07/43] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-01 15:54   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-01 17:45   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 12/43] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 13/43] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 14/43] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-01 17:47   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 15/43] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-01 18:00   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 16/43] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-01 18:08   ` Alex Bennée
2022-03-03 17:22     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-02-11 16:50   ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-01 18:11   ` Alex Bennée
2022-03-03 17:53     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-01 18:17   ` Alex Bennée
2022-03-03 18:07     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 20/43] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-01 18:46   ` Alex Bennée
2022-03-04 13:16     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-03-02 10:01   ` Alex Bennée
2022-03-04 13:30     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-03-02 10:03   ` Alex Bennée [this message]
2022-03-04 14:16     ` Jonathan Cameron
2022-03-04 14:26       ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-02 10:20   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-02 12:14   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-02 12:16   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-02 12:17   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-02  6:55   ` Markus Armbruster
2022-03-04 15:56     ` Jonathan Cameron
2022-03-04 17:13       ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-02 12:18   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-03-02 13:53   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-02 16:07   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-02 16:07   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 39/43] tests/acpi: Add tables " Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 42/43] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-02-18 18:17 ` [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron

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