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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Markus Armbruster <armbru@redhat.com>
Cc: "Jonathan Cameron via" <qemu-devel@nongnu.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Marcel Apfelbaum" <marcel@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	linux-cxl@vger.kernel.org,
	"Ben Widawsky" <ben.widawsky@intel.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	linuxarm@huawei.com,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Saransh Gupta1" <saransh@ibm.com>,
	"Shreyas Shah" <shreyas.shah@elastics.cloud>,
	"Chris Browy" <cbrowy@avery-design.com>,
	"Samarth Saxena" <samarths@cadence.com>,
	"Dan Williams" <dan.j.williams@intel.com>
Subject: Re: [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows.
Date: Fri, 4 Mar 2022 15:56:38 +0000	[thread overview]
Message-ID: <20220304155638.00007bae@huawei.com> (raw)
In-Reply-To: <87y21slu6m.fsf@pond.sub.org>

On Wed, 02 Mar 2022 07:55:45 +0100
Markus Armbruster <armbru@redhat.com> wrote:

> Jonathan Cameron via <qemu-devel@nongnu.org> writes:
> 
> > From: Jonathan Cameron <jonathan.cameron@huawei.com>
> >
> > The concept of these is introduced in [1] in terms of the
> > description the CEDT ACPI table. The principal is more general.
> > Unlike once traffic hits the CXL root bridges, the host system
> > memory address routing is implementation defined and effectively
> > static once observable by standard / generic system software.
> > Each CXL Fixed Memory Windows (CFMW) is a region of PA space
> > which has fixed system dependent routing configured so that
> > accesses can be routed to the CXL devices below a set of target
> > root bridges. The accesses may be interleaved across multiple
> > root bridges.
> >
> > For QEMU we could have fully specified these regions in terms
> > of a base PA + size, but as the absolute address does not matter
> > it is simpler to let individual platforms place the memory regions.
> >
> > ExampleS:
> > -cxl-fixed-memory-window targets=cxl.0,size=128G
> > -cxl-fixed-memory-window targets=cxl.1,size=128G
> > -cxl-fixed-memory-window targets=cxl0,targets=cxl.1,size=256G,interleave-granularity=2k
> >
> > Specifies
> > * 2x 128G regions not interleaved across root bridges, one for each of
> >   the root bridges with ids cxl.0 and cxl.1
> > * 256G region interleaved across root bridges with ids cxl.0 and cxl.1
> > with a 2k interleave granularity.
> >
> > When system software enumerates the devices below a given root bridge
> > it can then decide which CFMW to use. If non interleave is desired
> > (or possible) it can use the appropriate CFMW for the root bridge in
> > question.  If there are suitable devices to interleave across the
> > two root bridges then it may use the 3rd CFMS.
> >
> > A number of other designs were considered but the following constraints
> > made it hard to adapt existing QEMU approaches to this particular problem.
> > 1) The size must be known before a specific architecture / board brings
> >    up it's PA memory map.  We need to set up an appropriate region.
> > 2) Using links to the host bridges provides a clean command line interface
> >    but these links cannot be established until command line devices have
> >    been added.
> >
> > Hence the two step process used here of first establishing the size,
> > interleave-ways and granularity + caching the ids of the host bridges
> > and then, once available finding the actual host bridges so they can
> > be used later to support interleave decoding.
> >
> > [1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
> >
> > Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>  
> 
> [...]
> 
> > diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
> > new file mode 100644
> > index 0000000000..9f303e6d8e
> > --- /dev/null
> > +++ b/hw/cxl/cxl-host.c  
> 
> [...]
> 
> > +QemuOptsList qemu_cxl_fixed_window_opts = {
> > +    .name = "cxl-fixed-memory-window",
> > +    .implied_opt_name = "type",
> > +    .head = QTAILQ_HEAD_INITIALIZER(qemu_cxl_fixed_window_opts.head),
> > +    .desc = { { 0 } }
> > +};
> > +  
> 
> [...]
> 
> > +static int parse_cxl_fixed_memory_window(void *opaque, QemuOpts *opts,
> > +                                         Error **errp)
> > +{
> > +    CXLFixedMemoryWindowOptions *object = NULL;
> > +    MachineState *ms = MACHINE(opaque);
> > +    Error *err = NULL;
> > +    Visitor *v = opts_visitor_new(opts);
> > +
> > +    visit_type_CXLFixedMemoryWindowOptions(v, NULL, &object, errp);
> > +    visit_free(v);
> > +    if (!object) {
> > +        return -1;
> > +    }
> > +
> > +    set_cxl_fixed_memory_window_options(ms, object, &err);
> > +
> > +    qapi_free_CXLFixedMemoryWindowOptions(object);
> > +    if (err) {
> > +        error_propagate(errp, err);
> > +        return -1;
> > +    }
> > +
> > +    return 0;
> > +}
> > +
> > +void parse_cxl_fixed_memory_window_opts(MachineState *ms)
> > +{
> > +    qemu_opts_foreach(qemu_find_opts("cxl-fixed-memory-window"),
> > +                      parse_cxl_fixed_memory_window, ms, &error_fatal);
> > +}  
> 
> [...]
> 
> > diff --git a/qapi/machine.json b/qapi/machine.json
> > index 42fc68403d..0998a9128d 100644
> > --- a/qapi/machine.json
> > +++ b/qapi/machine.json
> > @@ -504,6 +504,21 @@
> >     'dst': 'uint16',
> >     'val': 'uint8' }}
> >  
> > +##
> > +# @CXLFixedMemoryWindowOptions:
> > +#
> > +# Create a CXL Fixed Memory Window (for OptsVisitor)
> > +#
> > +# @targets: Target root bridge IDs  
> 
> Missing: @size, @targets.
> 
> > +#
> > +# Since X.X //fixme  
> 
> Well, "fix me, please".
> 
> > +##
> > +{ 'struct': 'CXLFixedMemoryWindowOptions',
> > +  'data': {
> > +      'size': 'size',
> > +      '*interleave-granularity': 'size',
> > +      'targets': ['str'] }}
> > +
> >  ##
> >  # @X86CPURegister32:
> >  #  
> 
> [...]
> 
> > diff --git a/qemu-options.hx b/qemu-options.hx
> > index ba3ae6a42a..b4d2cc6f48 100644
> > --- a/qemu-options.hx
> > +++ b/qemu-options.hx
> > @@ -467,6 +467,43 @@ SRST
> >          -numa hmat-cache,node-id=1,size=10K,level=1,associativity=direct,policy=write-back,line=8
> >  ERST
> >  
> > +DEF("cxl-fixed-memory-window", HAS_ARG, QEMU_OPTION_cxl_fixed_memory_window,
> > +    "-cxl-fixed-memory-window targets=firsttarget,targets=secondtarget,size=size[,interleave-granularity=granularity]\n",
> > +    QEMU_ARCH_ALL)
> > +SRST
> > +``-cxl-fixed-memory-window targets=firsttarget,targets=secondtarget,size=size[,interleave-granularity=granularity]``
> > +    Define a CXL Fixed Memory Window (CFMW).
> > +
> > +    Described in the CXL 2.0 ECN: CEDT CFMWS & QTG _DSM.
> > +
> > +    They are regions of Host Physical Addresses (HPA) on a system which
> > +    may be interleaved across one or more CXL host bridges.  The system
> > +    software will assign particular devices into these windows and
> > +    configure the downstream Host-managed Device Memory (HDM) decoders
> > +    in root ports, switch ports and devices appropriately to meet the
> > +    interleave requirements before enabling the memory devices.
> > +
> > +    ``targets=firsttarget`` provides the mapping to CXL host bridges
> > +    which may be identified by the id provied in the -device entry.
> > +    Multiple entries are needed to specify all the targets when
> > +    the fixed memory window represents interleaved memory.
> > +
> > +    ``size=size`` sets the size of the CFMW. This must be a multiple of
> > +    256MiB. The region will be aligned to 256MiB but the location is
> > +    platform and configuration dependent.
> > +
> > +    ``interleave-granularity=granularity`` sets the granularity of
> > +    interleave. Default 256KiB. Only 256KiB, 512KiB, 1024KiB, 2048KiB
> > +    4096KiB, 8192KiB and 16384KiB granularities supported.
> > +
> > +    Example:
> > +
> > +    ::
> > +
> > +        -cxl-fixed-memory-window -targets=cxl.0,-targets=cxl.1,size=128G,interleave-granularity=512k
> > +
> > +ERST
> > +
> >  DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd,
> >      "-add-fd fd=fd,set=set[,opaque=opaque]\n"
> >      "                Add 'fd' to fd 'set'\n", QEMU_ARCH_ALL)
> > diff --git a/softmmu/vl.c b/softmmu/vl.c
> > index 5e1b35ba48..f83f158fff 100644
> > --- a/softmmu/vl.c
> > +++ b/softmmu/vl.c
> > @@ -91,6 +91,7 @@
> >  #include "qemu/config-file.h"
> >  #include "qemu/qemu-options.h"
> >  #include "qemu/main-loop.h"
> > +#include "hw/cxl/cxl.h"
> >  #ifdef CONFIG_VIRTFS
> >  #include "fsdev/qemu-fsdev.h"
> >  #endif
> > @@ -2744,6 +2745,7 @@ void qmp_x_exit_preconfig(Error **errp)
> >  
> >      qemu_init_board();
> >      qemu_create_cli_devices();
> > +    cxl_fixed_memory_window_link_targets(errp);
> >      qemu_machine_creation_done();
> >  
> >      if (loadvm) {
> > @@ -2805,6 +2807,7 @@ void qemu_init(int argc, char **argv, char **envp)
> >      qemu_add_opts(&qemu_msg_opts);
> >      qemu_add_opts(&qemu_name_opts);
> >      qemu_add_opts(&qemu_numa_opts);
> > +    qemu_add_opts(&qemu_cxl_fixed_window_opts);
> >      qemu_add_opts(&qemu_icount_opts);
> >      qemu_add_opts(&qemu_semihosting_config_opts);
> >      qemu_add_opts(&qemu_fw_cfg_opts);
> > @@ -2927,6 +2930,13 @@ void qemu_init(int argc, char **argv, char **envp)
> >                      exit(1);
> >                  }
> >                  break;
> > +            case QEMU_OPTION_cxl_fixed_memory_window:
> > +                opts = qemu_opts_parse_noisily(qemu_find_opts("cxl-fixed-memory-window"),
> > +                                               optarg, true);
> > +                if (!opts) {
> > +                    exit(1);
> > +                }
> > +                break;
> >              case QEMU_OPTION_display:
> >                  parse_display(optarg);
> >                  break;
> > @@ -3764,6 +3774,7 @@ void qemu_init(int argc, char **argv, char **envp)
> >  
> >      qemu_resolve_machine_memdev();
> >      parse_numa_opts(current_machine);
> > +    parse_cxl_fixed_memory_window_opts(current_machine);
> >  
> >      if (vmstate_dump_file) {
> >          /* dump and exit */  
> 
> Have you considered using qobject_input_visitor_new_str() instead of
> QemuOpts?
> 

Umm. No. Why might that be a better approach?

Thanks,

Jonathan



  reply	other threads:[~2022-03-04 15:56 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-11 12:07 [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 01/43] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 04/43] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-01 15:32   ` Alex Bennée
2022-03-03 16:31     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 07/43] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-01 15:54   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-01 17:45   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 12/43] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 13/43] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 14/43] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-01 17:47   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 15/43] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-01 18:00   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 16/43] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-01 18:08   ` Alex Bennée
2022-03-03 17:22     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-02-11 16:50   ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-01 18:11   ` Alex Bennée
2022-03-03 17:53     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-01 18:17   ` Alex Bennée
2022-03-03 18:07     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 20/43] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-01 18:46   ` Alex Bennée
2022-03-04 13:16     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-03-02 10:01   ` Alex Bennée
2022-03-04 13:30     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-03-02 10:03   ` Alex Bennée
2022-03-04 14:16     ` Jonathan Cameron
2022-03-04 14:26       ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-02 10:20   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-02 12:14   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-02 12:16   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-02 12:17   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-02  6:55   ` Markus Armbruster
2022-03-04 15:56     ` Jonathan Cameron [this message]
2022-03-04 17:13       ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-02 12:18   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-03-02 13:53   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-02 16:07   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-02 16:07   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 39/43] tests/acpi: Add tables " Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 42/43] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-02-18 18:17 ` [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron

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