* [PATCH 1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
2020-03-10 3:32 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C " Joakim Zhang
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Add power domain for I2C and INTMUX in CM40 SS.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
drivers/firmware/imx/scu-pd.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
index b556612207e5..e803dcf60d14 100644
--- a/drivers/firmware/imx/scu-pd.c
+++ b/drivers/firmware/imx/scu-pd.c
@@ -158,6 +158,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
/* DC SS */
{ "dc0", IMX_SC_R_DC_0, 1, false, 0 },
{ "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 },
+
+ /* CM40 SS */
+ { "cm40_i2c", IMX_SC_R_M4_0_I2C, 1, 0 },
+ { "cm40_intmux", IMX_SC_R_M4_0_INTMUX, 1, 0 },
};
static const struct imx_sc_pd_soc imx8qxp_scu_pd = {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS
2020-02-17 3:19 ` [PATCH 1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS Joakim Zhang
@ 2020-03-10 3:32 ` Shawn Guo
0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2020-03-10 3:32 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette, sboyd, robh+dt, mark.rutland, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, leonard.crestez, daniel.baluta,
aisheng.dong, peng.fan, fugang.duan, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
On Mon, Feb 17, 2020 at 11:19:15AM +0800, Joakim Zhang wrote:
> Add power domain for I2C and INTMUX in CM40 SS.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C in CM40 SS
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
2020-02-17 3:19 ` [PATCH 1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
2020-02-25 17:57 ` Rob Herring
2020-03-10 3:42 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 3/7] bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible string Joakim Zhang
` (4 subsequent siblings)
6 siblings, 2 replies; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Add SCU and LPCG clocks for I2C in CM40 SS.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
include/dt-bindings/clock/imx8-clock.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 673a8c662340..84a442be700f 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -131,7 +131,12 @@
#define IMX_ADMA_PWM_CLK 188
#define IMX_ADMA_LCD_CLK 189
-#define IMX_SCU_CLK_END 190
+/* CM40 SS */
+#define IMX_CM40_IPG_CLK 200
+#define IMX_CM40_I2C_CLK 205
+
+#define IMX_SCU_CLK_END 220
+
/* LPCG clocks */
@@ -290,4 +295,10 @@
#define IMX_ADMA_LPCG_CLK_END 45
+/* CM40 SS LPCG */
+#define IMX_CM40_LPCG_I2C_IPG_CLK 0
+#define IMX_CM40_LPCG_I2C_CLK 1
+
+#define IMX_CM40_LPCG_CLK_END 2
+
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C in CM40 SS
2020-02-17 3:19 ` [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C " Joakim Zhang
@ 2020-02-25 17:57 ` Rob Herring
2020-02-26 2:56 ` Joakim Zhang
2020-03-10 3:42 ` Shawn Guo
1 sibling, 1 reply; 16+ messages in thread
From: Rob Herring @ 2020-02-25 17:57 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette, sboyd, mark.rutland, shawnguo, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, leonard.crestez, daniel.baluta,
aisheng.dong, peng.fan, fugang.duan, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
On Mon, Feb 17, 2020 at 11:19:16AM +0800, Joakim Zhang wrote:
> Add SCU and LPCG clocks for I2C in CM40 SS.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> include/dt-bindings/clock/imx8-clock.h | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
> index 673a8c662340..84a442be700f 100644
> --- a/include/dt-bindings/clock/imx8-clock.h
> +++ b/include/dt-bindings/clock/imx8-clock.h
> @@ -131,7 +131,12 @@
> #define IMX_ADMA_PWM_CLK 188
> #define IMX_ADMA_LCD_CLK 189
>
> -#define IMX_SCU_CLK_END 190
> +/* CM40 SS */
> +#define IMX_CM40_IPG_CLK 200
> +#define IMX_CM40_I2C_CLK 205
> +
> +#define IMX_SCU_CLK_END 220
Why are you skipping numbers?
> +
>
> /* LPCG clocks */
>
> @@ -290,4 +295,10 @@
>
> #define IMX_ADMA_LPCG_CLK_END 45
>
> +/* CM40 SS LPCG */
> +#define IMX_CM40_LPCG_I2C_IPG_CLK 0
> +#define IMX_CM40_LPCG_I2C_CLK 1
> +
> +#define IMX_CM40_LPCG_CLK_END 2
> +
> #endif /* __DT_BINDINGS_CLOCK_IMX_H */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C in CM40 SS
2020-02-25 17:57 ` Rob Herring
@ 2020-02-26 2:56 ` Joakim Zhang
0 siblings, 0 replies; 16+ messages in thread
From: Joakim Zhang @ 2020-02-26 2:56 UTC (permalink / raw)
To: Rob Herring
Cc: mturquette, sboyd, mark.rutland, shawnguo, s.hauer, kernel,
festevam, dl-linux-imx, Leonard Crestez, Aisheng Dong, linux-clk,
devicetree, linux-arm-kernel, linux-kernel
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2020年2月26日 1:58
> To: Joakim Zhang <qiangqing.zhang@nxp.com>
> Cc: mturquette@baylibre.com; sboyd@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; Anson Huang
> <anson.huang@nxp.com>; Leonard Crestez <leonard.crestez@nxp.com>;
> Daniel Baluta <daniel.baluta@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan
> <fugang.duan@nxp.com>; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C in CM40 SS
>
> On Mon, Feb 17, 2020 at 11:19:16AM +0800, Joakim Zhang wrote:
> > Add SCU and LPCG clocks for I2C in CM40 SS.
> >
> > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> > ---
> > include/dt-bindings/clock/imx8-clock.h | 13 ++++++++++++-
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/dt-bindings/clock/imx8-clock.h
> b/include/dt-bindings/clock/imx8-clock.h
> > index 673a8c662340..84a442be700f 100644
> > --- a/include/dt-bindings/clock/imx8-clock.h
> > +++ b/include/dt-bindings/clock/imx8-clock.h
> > @@ -131,7 +131,12 @@
> > #define IMX_ADMA_PWM_CLK 188
> > #define IMX_ADMA_LCD_CLK 189
> >
> > -#define IMX_SCU_CLK_END 190
> > +/* CM40 SS */
> > +#define IMX_CM40_IPG_CLK 200
> > +#define IMX_CM40_I2C_CLK 205
> > +
> > +#define IMX_SCU_CLK_END 220
>
> Why are you skipping numbers?
Hi Rob,
I found that there is a gap in SCU clock between subsystem, some numbers could be reserved for devices which may be added into this subsystem in the future.
Best Regards,
Joakim Zhang
> > +
> >
> > /* LPCG clocks */
> >
> > @@ -290,4 +295,10 @@
> >
> > #define IMX_ADMA_LPCG_CLK_END 45
> >
> > +/* CM40 SS LPCG */
> > +#define IMX_CM40_LPCG_I2C_IPG_CLK 0
> > +#define IMX_CM40_LPCG_I2C_CLK 1
> > +
> > +#define IMX_CM40_LPCG_CLK_END 2
> > +
> > #endif /* __DT_BINDINGS_CLOCK_IMX_H */
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C in CM40 SS
2020-02-17 3:19 ` [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C " Joakim Zhang
2020-02-25 17:57 ` Rob Herring
@ 2020-03-10 3:42 ` Shawn Guo
1 sibling, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2020-03-10 3:42 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette, sboyd, robh+dt, mark.rutland, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, leonard.crestez, daniel.baluta,
aisheng.dong, peng.fan, fugang.duan, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
On Mon, Feb 17, 2020 at 11:19:16AM +0800, Joakim Zhang wrote:
> Add SCU and LPCG clocks for I2C in CM40 SS.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> include/dt-bindings/clock/imx8-clock.h | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
I think it can be merged into patch #4.
Shawn
>
> diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
> index 673a8c662340..84a442be700f 100644
> --- a/include/dt-bindings/clock/imx8-clock.h
> +++ b/include/dt-bindings/clock/imx8-clock.h
> @@ -131,7 +131,12 @@
> #define IMX_ADMA_PWM_CLK 188
> #define IMX_ADMA_LCD_CLK 189
>
> -#define IMX_SCU_CLK_END 190
> +/* CM40 SS */
> +#define IMX_CM40_IPG_CLK 200
> +#define IMX_CM40_I2C_CLK 205
> +
> +#define IMX_SCU_CLK_END 220
> +
>
> /* LPCG clocks */
>
> @@ -290,4 +295,10 @@
>
> #define IMX_ADMA_LPCG_CLK_END 45
>
> +/* CM40 SS LPCG */
> +#define IMX_CM40_LPCG_I2C_IPG_CLK 0
> +#define IMX_CM40_LPCG_I2C_CLK 1
> +
> +#define IMX_CM40_LPCG_CLK_END 2
> +
> #endif /* __DT_BINDINGS_CLOCK_IMX_H */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/7] bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible string
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
2020-02-17 3:19 ` [PATCH 1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS Joakim Zhang
2020-02-17 3:19 ` [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C " Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
2020-02-25 17:58 ` Rob Herring
2020-02-17 3:19 ` [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS Joakim Zhang
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Add "fsl,imx8qxp-lpcg-cm40" compatible string.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
index 965cfa42e025..dcb9208a0e02 100644
--- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
+++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
@@ -21,6 +21,7 @@ Required properties:
"fsl,imx8qxp-lpcg-img",
"fsl,imx8qxp-lpcg-lsio",
"fsl,imx8qxp-lpcg-vpu"
+ "fsl,imx8qxp-lpcg-cm40"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/7] bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible string
2020-02-17 3:19 ` [PATCH 3/7] bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible string Joakim Zhang
@ 2020-02-25 17:58 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-02-25 17:58 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer,
kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
On Mon, 17 Feb 2020 11:19:17 +0800, Joakim Zhang wrote:
> Add "fsl,imx8qxp-lpcg-cm40" compatible string.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
` (2 preceding siblings ...)
2020-02-17 3:19 ` [PATCH 3/7] bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible string Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
2020-03-10 3:45 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX " Joakim Zhang
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Enable SCU and LPCG clocks for I2C in CM40 SS.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
drivers/clk/imx/clk-imx8qxp.c | 4 ++++
3 files changed, 19 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index 04c8ee35e14c..795909ecfba6 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
{ IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
};
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
+ { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0, CM40_I2C_LPCG, 0, 0, },
+ { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk", "cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
+ .lpcg = imx8qxp_lpcg_cm40,
+ .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
+ .num_max = IMX_CM40_LPCG_CLK_END,
+};
+
static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
.lpcg = imx8qxp_lpcg_lsio,
.num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
@@ -219,6 +230,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = {
{ .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
{ .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
{ .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
+ { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
{ /* sentinel */ }
};
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
index 2a37ce57c500..28ca730dd135 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
@@ -99,4 +99,7 @@
#define ADMA_FLEXCAN_1_LPCG 0x1ce0000
#define ADMA_FLEXCAN_2_LPCG 0x1cf0000
+/* CM40 SS */
+#define CM40_I2C_LPCG 0x60000
+
#endif /* _IMX8QXP_LPCG_H */
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 5e2903efc488..d051073ff042 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
+ clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "cm40_ipg_clk_root", NULL, 0, 132000000);
/* ARM core */
clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
@@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
+ /* CM40 SS */
+ clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
+
for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clks[i]))
pr_warn("i.MX clk %u: register failed with %ld\n",
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS
2020-02-17 3:19 ` [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS Joakim Zhang
@ 2020-03-10 3:45 ` Shawn Guo
2020-03-10 6:01 ` Joakim Zhang
0 siblings, 1 reply; 16+ messages in thread
From: Shawn Guo @ 2020-03-10 3:45 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette, sboyd, robh+dt, mark.rutland, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, leonard.crestez, daniel.baluta,
aisheng.dong, peng.fan, fugang.duan, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
On Mon, Feb 17, 2020 at 11:19:18AM +0800, Joakim Zhang wrote:
> Enable SCU and LPCG clocks for I2C in CM40 SS.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
So you decided to stop waiting for Aisheng's new imx8qxp clock driver?
Shawn
> ---
> drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
> drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
> drivers/clk/imx/clk-imx8qxp.c | 4 ++++
> 3 files changed, 19 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> index 04c8ee35e14c..795909ecfba6 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> @@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
> { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
> };
>
> +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
> + { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0, CM40_I2C_LPCG, 0, 0, },
> + { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk", "cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, },
> +};
> +
> +static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
> + .lpcg = imx8qxp_lpcg_cm40,
> + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
> + .num_max = IMX_CM40_LPCG_CLK_END,
> +};
> +
> static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
> .lpcg = imx8qxp_lpcg_lsio,
> .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
> @@ -219,6 +230,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = {
> { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
> { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
> { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
> + { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
> { /* sentinel */ }
> };
>
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> index 2a37ce57c500..28ca730dd135 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> @@ -99,4 +99,7 @@
> #define ADMA_FLEXCAN_1_LPCG 0x1ce0000
> #define ADMA_FLEXCAN_2_LPCG 0x1cf0000
>
> +/* CM40 SS */
> +#define CM40_I2C_LPCG 0x60000
> +
> #endif /* _IMX8QXP_LPCG_H */
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 5e2903efc488..d051073ff042 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
> clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
> clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
> + clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "cm40_ipg_clk_root", NULL, 0, 132000000);
>
> /* ARM core */
> clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
> @@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
> clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
>
> + /* CM40 SS */
> + clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
> +
> for (i = 0; i < clk_data->num; i++) {
> if (IS_ERR(clks[i]))
> pr_warn("i.MX clk %u: register failed with %ld\n",
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS
2020-03-10 3:45 ` Shawn Guo
@ 2020-03-10 6:01 ` Joakim Zhang
0 siblings, 0 replies; 16+ messages in thread
From: Joakim Zhang @ 2020-03-10 6:01 UTC (permalink / raw)
To: Shawn Guo
Cc: mturquette, sboyd, robh+dt, mark.rutland, s.hauer, kernel,
festevam, dl-linux-imx, Aisheng Dong, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: 2020年3月10日 11:45
> To: Joakim Zhang <qiangqing.zhang@nxp.com>
> Cc: mturquette@baylibre.com; sboyd@kernel.org; robh+dt@kernel.org;
> mark.rutland@arm.com; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; Anson Huang
> <anson.huang@nxp.com>; Leonard Crestez <leonard.crestez@nxp.com>;
> Daniel Baluta <daniel.baluta@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan
> <fugang.duan@nxp.com>; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C
> in CM40 SS
>
> On Mon, Feb 17, 2020 at 11:19:18AM +0800, Joakim Zhang wrote:
> > Enable SCU and LPCG clocks for I2C in CM40 SS.
> >
> > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
>
> So you decided to stop waiting for Aisheng's new imx8qxp clock driver?
Hi Shawn,
Please ignore all clock and dts patches, I will send out again after Aisheng's new imx8qxp clock driver. Thanks.
Best Regards,
Joakim Zhang
> Shawn
>
> > ---
> > drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
> > drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
> > drivers/clk/imx/clk-imx8qxp.c | 4 ++++
> > 3 files changed, 19 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > index 04c8ee35e14c..795909ecfba6 100644
> > --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> > @@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data
> imx8qxp_lpcg_lsio[] = {
> > { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk",
> > "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, }, };
> >
> > +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
> > + { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0,
> CM40_I2C_LPCG, 0, 0, },
> > + { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk",
> > +"cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, }, };
> > +
> > +static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
> > + .lpcg = imx8qxp_lpcg_cm40,
> > + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
> > + .num_max = IMX_CM40_LPCG_CLK_END,
> > +};
> > +
> > static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
> > .lpcg = imx8qxp_lpcg_lsio,
> > .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio), @@ -219,6 +230,7 @@
> > static const struct of_device_id imx8qxp_lpcg_match[] = {
> > { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
> > { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
> > { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
> > + { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
> > { /* sentinel */ }
> > };
> >
> > diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > index 2a37ce57c500..28ca730dd135 100644
> > --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> > @@ -99,4 +99,7 @@
> > #define ADMA_FLEXCAN_1_LPCG 0x1ce0000
> > #define ADMA_FLEXCAN_2_LPCG 0x1cf0000
> >
> > +/* CM40 SS */
> > +#define CM40_I2C_LPCG 0x60000
> > +
> > #endif /* _IMX8QXP_LPCG_H */
> > diff --git a/drivers/clk/imx/clk-imx8qxp.c
> > b/drivers/clk/imx/clk-imx8qxp.c index 5e2903efc488..d051073ff042
> > 100644
> > --- a/drivers/clk/imx/clk-imx8qxp.c
> > +++ b/drivers/clk/imx/clk-imx8qxp.c
> > @@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device
> *pdev)
> > clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL,
> "hsio_per_clk_root", NULL, 0, 133333333);
> > clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL,
> "lsio_mem_clk_root", NULL, 0, 200000000);
> > clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL,
> "lsio_bus_clk_root", NULL, 0, 100000000);
> > + clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL,
> "cm40_ipg_clk_root", NULL, 0, 132000000);
> >
> > /* ARM core */
> > clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35,
> IMX_SC_PM_CLK_CPU);
> > @@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device
> *pdev)
> > clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk",
> IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
> > clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk",
> IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
> >
> > + /* CM40 SS */
> > + clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk",
> IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
> > +
> > for (i = 0; i < clk_data->num; i++) {
> > if (IS_ERR(clks[i]))
> > pr_warn("i.MX clk %u: register failed with %ld\n",
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX in CM40 SS
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
` (3 preceding siblings ...)
2020-02-17 3:19 ` [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
2020-03-10 3:49 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 6/7] clk: imx: imx8qxp: add LPCG clock for FlexCAN in ADMA SS Joakim Zhang
2020-02-17 3:19 ` [PATCH 7/7] arch: arm64: dts: imx8qxp: add device node for CAN " Joakim Zhang
6 siblings, 1 reply; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Add device node for I2C and INTMUX in CM40 SS.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 27 +++++++++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 47 +++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index d3d26cca7d52..f88402ee650c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -30,6 +30,26 @@
};
};
+&cm40_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cm40_i2c>;
+ status = "okay";
+
+ pca6416: gpio@20 {
+ compatible = "nxp,pca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&cm40_intmux {
+ status = "okay";
+};
+
&adma_lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
@@ -161,6 +181,13 @@
};
&iomuxc {
+ pinctrl_cm40_i2c: cm40i2cgrp {
+ fsl,pins = <
+ IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
+ IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index fb5f752b15fe..cd10519eced7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -213,6 +213,53 @@
clock-output-names = "xtal_24MHz";
};
+ cm40_subsys: bus@34000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+
+ cm40_lpcg: clock-controller@375d0000 {
+ compatible = "fsl,imx8qxp-lpcg-cm40";
+ reg = <0x375d0000 0x70000>;
+ #clock-cells = <1>;
+ };
+
+ cm40_i2c: i2c@37230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x37230000 0x1000>;
+ interrupts = <9 0>;
+ interrupt-parent = <&cm40_intmux>;
+ clocks = <&cm40_lpcg IMX_CM40_LPCG_I2C_CLK>,
+ <&cm40_lpcg IMX_CM40_LPCG_I2C_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_CM40_I2C_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ status = "disabled";
+ };
+
+ cm40_intmux: intmux@37400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&clk IMX_CM40_IPG_CLK>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+ status = "disabled";
+ };
+ };
+
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX in CM40 SS
2020-02-17 3:19 ` [PATCH 5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX " Joakim Zhang
@ 2020-03-10 3:49 ` Shawn Guo
0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2020-03-10 3:49 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette, sboyd, robh+dt, mark.rutland, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, leonard.crestez, daniel.baluta,
aisheng.dong, peng.fan, fugang.duan, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
On Mon, Feb 17, 2020 at 11:19:19AM +0800, Joakim Zhang wrote:
> Add device node for I2C and INTMUX in CM40 SS.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
The 'arch:' prefix in subject is not necessary.
Shawn
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/7] clk: imx: imx8qxp: add LPCG clock for FlexCAN in ADMA SS
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
` (4 preceding siblings ...)
2020-02-17 3:19 ` [PATCH 5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX " Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
2020-02-17 3:19 ` [PATCH 7/7] arch: arm64: dts: imx8qxp: add device node for CAN " Joakim Zhang
6 siblings, 0 replies; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Add LPCG clock for FlexCAN in ADMA SS.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
drivers/clk/imx/clk-imx8qxp-lpcg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index 795909ecfba6..07aba029c3ba 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -72,6 +72,9 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
{ IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
{ IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
{ IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
+ { IMX_ADMA_LPCG_CAN0_IPG_PE_CLK, "can0_lpcg_pe_clk", "can0_clk", 0, ADMA_FLEXCAN_0_LPCG, 0, 0, },
+ { IMX_ADMA_LPCG_CAN0_IPG_CLK, "can0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_FLEXCAN_0_LPCG, 16, 0, },
+ { IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK, "can0_lpcg_chi_clk", "dma_ipg_clk_root", 0, ADMA_FLEXCAN_0_LPCG, 20, 0, },
{ IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
{ IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/7] arch: arm64: dts: imx8qxp: add device node for CAN in ADMA SS
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
` (5 preceding siblings ...)
2020-02-17 3:19 ` [PATCH 6/7] clk: imx: imx8qxp: add LPCG clock for FlexCAN in ADMA SS Joakim Zhang
@ 2020-02-17 3:19 ` Joakim Zhang
6 siblings, 0 replies; 16+ messages in thread
From: Joakim Zhang @ 2020-02-17 3:19 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, shawnguo, s.hauer
Cc: kernel, festevam, linux-imx, Anson.Huang, leonard.crestez,
daniel.baluta, aisheng.dong, peng.fan, fugang.duan, linux-clk,
devicetree, linux-arm-kernel, linux-kernel, Joakim Zhang
Add device node for CAN in ADMA SS.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 47 +++++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 59 +++++++++++++++++++
2 files changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index f88402ee650c..72a45dd7129e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -28,6 +28,25 @@
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ reg_can_en: regulator-can-en {
+ compatible = "regulator-fixed";
+ regulator-name = "can-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can_stby: regulator-can-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can_en>;
+ };
};
&cm40_i2c {
@@ -80,6 +99,20 @@
};
};
+&adma_flexcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan0>;
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
+&adma_flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
&adma_i2c1 {
#address-cells = <1>;
#size-cells = <0>;
@@ -207,6 +240,20 @@
>;
};
+ pinctrl_flexcan0: flexcan0grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021
+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021
+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021
+ >;
+ };
+
pinctrl_ioexp_rst: ioexp_rst_grp {
fsl,pins = <
IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index cd10519eced7..f549e33d1c82 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -34,6 +34,9 @@
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
serial3 = &adma_lpuart3;
+ can0 = &adma_flexcan0;
+ can1 = &adma_flexcan1;
+ can2 = &adma_flexcan2;
};
cpus {
@@ -384,6 +387,62 @@
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};
+
+ adma_flexcan0: can@5a8d0000 {
+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+ reg = <0x5a8d0000 0x10000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&pd IMX_SC_R_CAN_0>;
+ /* SLSlice[4] */
+ fsl,clk-source = <0>;
+ status = "disabled";
+ };
+
+ adma_flexcan1: can@5a8e0000 {
+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+ reg = <0x5a8e0000 0x10000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ /* CAN0 clock and PD is shared among all CAN instances
+ * as CAN1 shares CAN0's clock and to enable CAN0's
+ * clock it has to be powered on.
+ */
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&pd IMX_SC_R_CAN_1>;
+ /* SLSlice[4] */
+ fsl,clk-source = <0>;
+ status = "disabled";
+ };
+
+ adma_flexcan2: can@5a8f0000 {
+ compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+ reg = <0x5a8f0000 0x10000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ /* CAN0 clock and PD is shared among all CAN instances
+ * as CAN2 shares CAN0's clock and to enable CAN0's
+ * clock it has to be powered on.
+ */
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&pd IMX_SC_R_CAN_2>;
+ /* SLSlice[4] */
+ fsl,clk-source = <0>;
+ status = "disabled";
+ };
};
conn_subsys: bus@5b000000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread