* [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs
2017-12-08 15:46 [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
@ 2017-12-08 15:46 ` Alexandre Belloni
2017-12-13 0:44 ` Rob Herring
2017-12-08 15:46 ` [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
2017-12-17 16:59 ` [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs PrasannaKumar Muralidharan
2 siblings, 1 reply; 7+ messages in thread
From: Alexandre Belloni @ 2017-12-08 15:46 UTC (permalink / raw)
To: Ralf Baechle
Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring, devicetree
Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 46 +++++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..1bb578b9d135
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,46 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+- mips-hpt-frequency: CPU counter frequency.
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianess, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+
--
2.15.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs
2017-12-08 15:46 ` [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni
@ 2017-12-13 0:44 ` Rob Herring
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2017-12-13 0:44 UTC (permalink / raw)
To: Alexandre Belloni; +Cc: Ralf Baechle, linux-mips, linux-kernel, devicetree
On Fri, Dec 08, 2017 at 04:46:11PM +0100, Alexandre Belloni wrote:
> Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 46 +++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding
2017-12-08 15:46 [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2017-12-08 15:46 ` [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni
@ 2017-12-08 15:46 ` Alexandre Belloni
[not found] ` <20171208154618.20105-8-alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-17 16:59 ` [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs PrasannaKumar Muralidharan
2 siblings, 1 reply; 7+ messages in thread
From: Alexandre Belloni @ 2017-12-08 15:46 UTC (permalink / raw)
To: Ralf Baechle
Cc: linux-mips, linux-kernel, Alexandre Belloni, Rob Herring,
devicetree, Sebastian Reichel, linux-pm
Add binding documentation for the Microsemi Ocelot reset block.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sebastian Reichel <sre@kernel.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 000000000000..1bcf276b04cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,17 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+
+ reset {
+ compatible = "mscc,ocelot-chip-reset";
+ };
+ };
--
2.15.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs
2017-12-08 15:46 [PATCH v2 00/13] MIPS: add support for the Microsemi MIPS SoCs Alexandre Belloni
2017-12-08 15:46 ` [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs Alexandre Belloni
2017-12-08 15:46 ` [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding Alexandre Belloni
@ 2017-12-17 16:59 ` PrasannaKumar Muralidharan
2 siblings, 0 replies; 7+ messages in thread
From: PrasannaKumar Muralidharan @ 2017-12-17 16:59 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Ralf Baechle, linux-mips, open list, Rob Herring, devicetree,
Thomas Gleixner, Jason Cooper, Linus Walleij, linux-gpio,
Sebastian Reichel, linux-pm
Hi Alexandre,
With very small amount of code in arch/mips this series looks really nice.
On 8 December 2017 at 21:16, Alexandre Belloni
<alexandre.belloni@free-electrons.com> wrote:
> Hi,
>
> This patch series adds initial support for the Microsemi MIPS SoCs. It
> is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514).
>
> It adds support for the IRQ controller, pinmux and gpio controller and
> reset control.
>
> This produces a kernel that can boot to the console.
>
> This is a single series for reference but it can also be taken
> separately by each maintainer as each drivers are independant.
>
> Changes in v2:
> - removed the wildcard in MAINAINERS
> - corrected the Cc list
> - added proper documentation for both syscons
> - removed the mscc,cpucontrol property
> - updated the ranges property in the ocelot dtsi
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: linux-gpio@vger.kernel.org
> Cc: Sebastian Reichel <sre@kernel.org>
> Cc: linux-pm@vger.kernel.org
>
>
> Alexandre Belloni (13):
> dt-bindings: Add vendor prefix for Microsemi Corporation
> dt-bindings: interrupt-controller: Add binding for the Microsemi
> Ocelot interrupt controller
> irqchip: Add a driver for the Microsemi Ocelot controller
> dt-bindings: pinctrl: Add bindings for Microsemi Ocelot
> pinctrl: Add Microsemi Ocelot SoC driver
> dt-bindings: mips: Add bindings for Microsemi SoCs
> dt-bindings: power: reset: Document ocelot-reset binding
> power: reset: Add a driver for the Microsemi Ocelot reset
> MIPS: mscc: Add initial support for Microsemi MIPS SoCs
> MIPS: mscc: add ocelot dtsi
> MIPS: mscc: add ocelot PCB123 device tree
> MIPS: defconfigs: add a defconfig for Microsemi SoCs
> MAINTAINERS: Add entry for Microsemi MIPS SoCs
>
> .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 +
> Documentation/devicetree/bindings/mips/mscc.txt | 46 ++
> .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 39 ++
> .../bindings/power/reset/ocelot-reset.txt | 17 +
> .../devicetree/bindings/vendor-prefixes.txt | 1 +
> MAINTAINERS | 7 +
> arch/mips/Kbuild.platforms | 1 +
> arch/mips/Kconfig | 24 +
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/mscc/Makefile | 6 +
> arch/mips/boot/dts/mscc/ocelot.dtsi | 115 +++++
> arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 ++
> arch/mips/configs/mscc_defconfig | 84 ++++
> arch/mips/mscc/Makefile | 11 +
> arch/mips/mscc/Platform | 12 +
> arch/mips/mscc/setup.c | 106 +++++
> drivers/irqchip/Kconfig | 5 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-mscc-ocelot.c | 109 +++++
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-ocelot.c | 505 +++++++++++++++++++++
> drivers/power/reset/Kconfig | 7 +
> drivers/power/reset/Makefile | 1 +
> drivers/power/reset/ocelot-reset.c | 86 ++++
> 25 files changed, 1244 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
> create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> create mode 100644 arch/mips/boot/dts/mscc/Makefile
> create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
> create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> create mode 100644 arch/mips/configs/mscc_defconfig
> create mode 100644 arch/mips/mscc/Makefile
> create mode 100644 arch/mips/mscc/Platform
> create mode 100644 arch/mips/mscc/setup.c
> create mode 100644 drivers/irqchip/irq-mscc-ocelot.c
> create mode 100644 drivers/pinctrl/pinctrl-ocelot.c
> create mode 100644 drivers/power/reset/ocelot-reset.c
>
> --
> 2.15.1
>
>
Except for irqchip driver and pinctrl driver other parts of the series is
Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Regards,
PrasannaKumar
^ permalink raw reply [flat|nested] 7+ messages in thread