* [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-07 13:48 ` Mika Westerberg
2019-11-13 9:54 ` Linus Walleij
2019-11-06 14:48 ` [PATCH v1 2/8] pinctrl: lynxpoint: Use raw_spinlock for locking Andy Shevchenko
` (7 subsequent siblings)
8 siblings, 2 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
Move Lynxpoint GPIO driver under Intel pin control umbrella
for further transformation to a real pin control driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
MAINTAINERS | 1 -
drivers/gpio/Kconfig | 8 --------
drivers/gpio/Makefile | 1 -
drivers/pinctrl/intel/Kconfig | 10 ++++++++++
drivers/pinctrl/intel/Makefile | 1 +
.../intel/pinctrl-lynxpoint.c} | 0
6 files changed, 11 insertions(+), 10 deletions(-)
rename drivers/{gpio/gpio-lynxpoint.c => pinctrl/intel/pinctrl-lynxpoint.c} (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1378491c223c..9b71250e3014 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8325,7 +8325,6 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
F: drivers/gpio/gpio-ich.c
F: drivers/gpio/gpio-intel-mid.c
-F: drivers/gpio/gpio-lynxpoint.c
F: drivers/gpio/gpio-merrifield.c
F: drivers/gpio/gpio-ml-ioh.c
F: drivers/gpio/gpio-pch.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 8adffd42f8cb..6923142fd874 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -335,14 +335,6 @@ config GPIO_LPC32XX
Select this option to enable GPIO driver for
NXP LPC32XX devices.
-config GPIO_LYNXPOINT
- tristate "Intel Lynxpoint GPIO support"
- depends on ACPI && X86
- select GPIOLIB_IRQCHIP
- help
- driver for GPIO functionality on Intel Lynxpoint PCH chipset
- Requires ACPI device enumeration code to set up a platform device.
-
config GPIO_MB86S7X
tristate "GPIO support for Fujitsu MB86S7x Platforms"
help
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 34eb8b2b12dd..55b2b645391e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -76,7 +76,6 @@ obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
-obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index c091eb2f0aeb..260193c453b0 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -42,6 +42,16 @@ config PINCTRL_MERRIFIELD
interface that allows configuring of SoC pins and using them as
GPIOs.
+config PINCTRL_LYNXPOINT
+ tristate "Intel Lynxpoint pinctrl and GPIO driver"
+ depends on ACPI
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ help
+ Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
+ provides an interface that allows configuring of PCH pins and
+ using them as GPIOs.
+
config PINCTRL_INTEL
tristate
select PINMUX
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 5e92aba018ac..541b94cfe398 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -13,5 +13,6 @@ obj-$(CONFIG_PINCTRL_ELKHARTLAKE) += pinctrl-elkhartlake.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
+obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o
diff --git a/drivers/gpio/gpio-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
similarity index 100%
rename from drivers/gpio/gpio-lynxpoint.c
rename to drivers/pinctrl/intel/pinctrl-lynxpoint.c
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder
2019-11-06 14:48 ` [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder Andy Shevchenko
@ 2019-11-07 13:48 ` Mika Westerberg
2019-11-07 14:47 ` Andy Shevchenko
2019-11-13 9:54 ` Linus Walleij
1 sibling, 1 reply; 15+ messages in thread
From: Mika Westerberg @ 2019-11-07 13:48 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: linux-gpio, Bartosz Golaszewski, Linus Walleij
On Wed, Nov 06, 2019 at 04:48:22PM +0200, Andy Shevchenko wrote:
> Move Lynxpoint GPIO driver under Intel pin control umbrella
> for further transformation to a real pin control driver.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> MAINTAINERS | 1 -
> drivers/gpio/Kconfig | 8 --------
> drivers/gpio/Makefile | 1 -
> drivers/pinctrl/intel/Kconfig | 10 ++++++++++
> drivers/pinctrl/intel/Makefile | 1 +
> .../intel/pinctrl-lynxpoint.c} | 0
> 6 files changed, 11 insertions(+), 10 deletions(-)
> rename drivers/{gpio/gpio-lynxpoint.c => pinctrl/intel/pinctrl-lynxpoint.c} (100%)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1378491c223c..9b71250e3014 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8325,7 +8325,6 @@ S: Maintained
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git
> F: drivers/gpio/gpio-ich.c
> F: drivers/gpio/gpio-intel-mid.c
> -F: drivers/gpio/gpio-lynxpoint.c
> F: drivers/gpio/gpio-merrifield.c
> F: drivers/gpio/gpio-ml-ioh.c
> F: drivers/gpio/gpio-pch.c
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 8adffd42f8cb..6923142fd874 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -335,14 +335,6 @@ config GPIO_LPC32XX
> Select this option to enable GPIO driver for
> NXP LPC32XX devices.
>
> -config GPIO_LYNXPOINT
> - tristate "Intel Lynxpoint GPIO support"
> - depends on ACPI && X86
> - select GPIOLIB_IRQCHIP
> - help
> - driver for GPIO functionality on Intel Lynxpoint PCH chipset
> - Requires ACPI device enumeration code to set up a platform device.
> -
> config GPIO_MB86S7X
> tristate "GPIO support for Fujitsu MB86S7x Platforms"
> help
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 34eb8b2b12dd..55b2b645391e 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -76,7 +76,6 @@ obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
> obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
> obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
> obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
> -obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
> obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
> obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
> obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
> diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
> index c091eb2f0aeb..260193c453b0 100644
> --- a/drivers/pinctrl/intel/Kconfig
> +++ b/drivers/pinctrl/intel/Kconfig
> @@ -42,6 +42,16 @@ config PINCTRL_MERRIFIELD
> interface that allows configuring of SoC pins and using them as
> GPIOs.
>
> +config PINCTRL_LYNXPOINT
> + tristate "Intel Lynxpoint pinctrl and GPIO driver"
> + depends on ACPI
> + select GPIOLIB
> + select GPIOLIB_IRQCHIP
> + help
> + Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
> + provides an interface that allows configuring of PCH pins and
> + using them as GPIOs.
In order to keep the above (non pinctrl-intel.c based drivers) sorted
alphabetically, can you move this before PINCTRL_MERRIFIELD?
> +
> config PINCTRL_INTEL
> tristate
> select PINMUX
> diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
> index 5e92aba018ac..541b94cfe398 100644
> --- a/drivers/pinctrl/intel/Makefile
> +++ b/drivers/pinctrl/intel/Makefile
> @@ -13,5 +13,6 @@ obj-$(CONFIG_PINCTRL_ELKHARTLAKE) += pinctrl-elkhartlake.o
> obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
> obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
> obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
> +obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
Here too.
> obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
> obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o
> diff --git a/drivers/gpio/gpio-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
> similarity index 100%
> rename from drivers/gpio/gpio-lynxpoint.c
> rename to drivers/pinctrl/intel/pinctrl-lynxpoint.c
> --
> 2.24.0.rc1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder
2019-11-07 13:48 ` Mika Westerberg
@ 2019-11-07 14:47 ` Andy Shevchenko
0 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-07 14:47 UTC (permalink / raw)
To: Mika Westerberg; +Cc: linux-gpio, Bartosz Golaszewski, Linus Walleij
On Thu, Nov 07, 2019 at 03:48:42PM +0200, Mika Westerberg wrote:
> On Wed, Nov 06, 2019 at 04:48:22PM +0200, Andy Shevchenko wrote:
> > Move Lynxpoint GPIO driver under Intel pin control umbrella
> > for further transformation to a real pin control driver.
> > +config PINCTRL_LYNXPOINT
> > + tristate "Intel Lynxpoint pinctrl and GPIO driver"
> > + depends on ACPI
> > + select GPIOLIB
> > + select GPIOLIB_IRQCHIP
> > + help
> > + Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
> > + provides an interface that allows configuring of PCH pins and
> > + using them as GPIOs.
>
> In order to keep the above (non pinctrl-intel.c based drivers) sorted
> alphabetically, can you move this before PINCTRL_MERRIFIELD?
Fixed in my review branch.
> > +obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
>
> Here too.
Ditto.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder
2019-11-06 14:48 ` [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder Andy Shevchenko
2019-11-07 13:48 ` Mika Westerberg
@ 2019-11-13 9:54 ` Linus Walleij
2019-11-13 13:40 ` Andy Shevchenko
1 sibling, 1 reply; 15+ messages in thread
From: Linus Walleij @ 2019-11-13 9:54 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Mika Westerberg, open list:GPIO SUBSYSTEM, Bartosz Golaszewski
On Wed, Nov 6, 2019 at 3:48 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
This Kconfig symbol goes away:
> -config GPIO_LYNXPOINT
This one appears:
> +config PINCTRL_LYNXPOINT
As long as you're certain this will not cause any problems it's
fine by me (thinking people who have old configs etc).
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder
2019-11-13 9:54 ` Linus Walleij
@ 2019-11-13 13:40 ` Andy Shevchenko
0 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-13 13:40 UTC (permalink / raw)
To: Linus Walleij
Cc: Mika Westerberg, open list:GPIO SUBSYSTEM, Bartosz Golaszewski
On Wed, Nov 13, 2019 at 10:54:28AM +0100, Linus Walleij wrote:
> On Wed, Nov 6, 2019 at 3:48 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
>
> This Kconfig symbol goes away:
>
> > -config GPIO_LYNXPOINT
>
> This one appears:
>
> > +config PINCTRL_LYNXPOINT
>
> As long as you're certain this will not cause any problems it's
> fine by me (thinking people who have old configs etc).
No. it's not a problem as long as people run `make oldconfig`.
We assume that distros do that way and carefully check each new option.
So, we consider no problem is here.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v1 2/8] pinctrl: lynxpoint: Use raw_spinlock for locking
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 3/8] pinctrl: lynxpoint: Correct amount of pins Andy Shevchenko
` (6 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
The Intel Lynxpoint pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt
we will get a BUG() asserted.
This is because in -rt spinlocks are preemptible so taking the driver
private spinlock in irqchip callbacks causes might_sleep() to trigger.
In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 28 +++++++++++------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index e9e47c0d5be7..6467095523cc 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -47,7 +47,7 @@
struct lp_gpio {
struct gpio_chip chip;
struct platform_device *pdev;
- spinlock_t lock;
+ raw_spinlock_t lock;
unsigned long reg_base;
};
@@ -144,7 +144,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
if (hwirq >= lg->chip.ngpio)
return -EINVAL;
- spin_lock_irqsave(&lg->lock, flags);
+ raw_spin_lock_irqsave(&lg->lock, flags);
value = inl(reg);
/* set both TRIG_SEL and INV bits to 0 for rising edge */
@@ -164,7 +164,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
value |= TRIG_SEL_BIT | INT_INV_BIT;
outl(value, reg);
- spin_unlock_irqrestore(&lg->lock, flags);
+ raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
@@ -181,14 +181,14 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
- spin_lock_irqsave(&lg->lock, flags);
+ raw_spin_lock_irqsave(&lg->lock, flags);
if (value)
outl(inl(reg) | OUT_LVL_BIT, reg);
else
outl(inl(reg) & ~OUT_LVL_BIT, reg);
- spin_unlock_irqrestore(&lg->lock, flags);
+ raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -197,9 +197,9 @@ static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
- spin_lock_irqsave(&lg->lock, flags);
+ raw_spin_lock_irqsave(&lg->lock, flags);
outl(inl(reg) | DIR_BIT, reg);
- spin_unlock_irqrestore(&lg->lock, flags);
+ raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
@@ -213,9 +213,9 @@ static int lp_gpio_direction_output(struct gpio_chip *chip,
lp_gpio_set(chip, offset, value);
- spin_lock_irqsave(&lg->lock, flags);
+ raw_spin_lock_irqsave(&lg->lock, flags);
outl(inl(reg) & ~DIR_BIT, reg);
- spin_unlock_irqrestore(&lg->lock, flags);
+ raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
@@ -266,9 +266,9 @@ static void lp_irq_enable(struct irq_data *d)
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
- spin_lock_irqsave(&lg->lock, flags);
+ raw_spin_lock_irqsave(&lg->lock, flags);
outl(inl(reg) | BIT(hwirq % 32), reg);
- spin_unlock_irqrestore(&lg->lock, flags);
+ raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static void lp_irq_disable(struct irq_data *d)
@@ -279,9 +279,9 @@ static void lp_irq_disable(struct irq_data *d)
unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
- spin_lock_irqsave(&lg->lock, flags);
+ raw_spin_lock_irqsave(&lg->lock, flags);
outl(inl(reg) & ~BIT(hwirq % 32), reg);
- spin_unlock_irqrestore(&lg->lock, flags);
+ raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static struct irq_chip lp_irqchip = {
@@ -345,7 +345,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
return -EBUSY;
}
- spin_lock_init(&lg->lock);
+ raw_spin_lock_init(&lg->lock);
gc = &lg->chip;
gc->label = dev_name(dev);
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v1 3/8] pinctrl: lynxpoint: Correct amount of pins
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 1/8] pinctrl: lynxpoint: Move GPIO driver to pin controller folder Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 2/8] pinctrl: lynxpoint: Use raw_spinlock for locking Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 4/8] pinctrl: lynxpoint: Keep pointer to struct device instead of its container Andy Shevchenko
` (5 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
When we count from 0 it's possible to get into off-by-one error.
That's what had happened to this driver. So, correct amount of pins
and related typos in the code.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index 6467095523cc..ebc523233df4 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -18,9 +18,9 @@
#include <linux/slab.h>
#include <linux/types.h>
-/* LynxPoint chipset has support for 94 gpio pins */
+/* LynxPoint chipset has support for 95 GPIO pins */
-#define LP_NUM_GPIO 94
+#define LP_NUM_GPIO 95
/* Bitmapped register offsets */
#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
@@ -54,11 +54,11 @@ struct lp_gpio {
/*
* Lynxpoint gpios are controlled through both bitmapped registers and
* per gpio specific registers. The bitmapped registers are in chunks of
- * 3 x 32bit registers to cover all 94 gpios
+ * 3 x 32bit registers to cover all 95 GPIOs
*
* per gpio specific registers consist of two 32bit registers per gpio
- * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
- * 188 config registers.
+ * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
+ * 190 config registers.
*
* A simplified view of the register layout look like this:
*
@@ -67,7 +67,7 @@ struct lp_gpio {
* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
* ...
* LP_INT_ENABLE[31:0] ...
- * LP_INT_ENABLE[63:31] ...
+ * LP_INT_ENABLE[63:32] ...
* LP_INT_ENABLE[94:64] ...
* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v1 4/8] pinctrl: lynxpoint: Keep pointer to struct device instead of its container
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
` (2 preceding siblings ...)
2019-11-06 14:48 ` [PATCH v1 3/8] pinctrl: lynxpoint: Correct amount of pins Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 5/8] pinctrl: lynxpoint: Use %pR to print IO resource Andy Shevchenko
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
There is no need to keep pointer to struct platform_device, which is container
of struct device, because the latter is what have been used everywhere outside
of ->probe() path. In any case we may derive pointer to the container when
needed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index ebc523233df4..dbca1ff076c8 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -46,7 +46,7 @@
struct lp_gpio {
struct gpio_chip chip;
- struct platform_device *pdev;
+ struct device *dev;
raw_spinlock_t lock;
unsigned long reg_base;
};
@@ -103,11 +103,11 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
- pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
+ pm_runtime_get(lg->dev); /* should we put if failed */
/* Fail if BIOS reserved pin for ACPI use */
if (!(inl(acpi_use) & BIT(offset % 32))) {
- dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
+ dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset);
return -EBUSY;
}
/* Fail if pin is in alternate function mode (not GPIO mode) */
@@ -129,7 +129,7 @@ static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
/* disable input sensing */
outl(inl(conf2) | GPINDIS_BIT, conf2);
- pm_runtime_put(&lg->pdev->dev);
+ pm_runtime_put(lg->dev);
}
static int lp_irq_type(struct irq_data *d, unsigned type)
@@ -325,7 +325,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
if (!lg)
return -ENOMEM;
- lg->pdev = pdev;
+ lg->dev = dev;
platform_set_drvdata(pdev, lg);
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v1 5/8] pinctrl: lynxpoint: Use %pR to print IO resource
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
` (3 preceding siblings ...)
2019-11-06 14:48 ` [PATCH v1 4/8] pinctrl: lynxpoint: Keep pointer to struct device instead of its container Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 6/8] pinctrl: lynxpoint: Switch to memory mapped IO accessors Andy Shevchenko
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
Replace explicit casting by pointer to struct resource with
specifier replacement to %pR to print the IO resource.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index dbca1ff076c8..05921729fe78 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -340,8 +340,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
reg_len = resource_size(io_rc);
if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
- dev_err(dev, "failed requesting IO region 0x%x\n",
- (unsigned int)lg->reg_base);
+ dev_err(dev, "failed requesting IO region %pR\n", &io_rc);
return -EBUSY;
}
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v1 6/8] pinctrl: lynxpoint: Switch to memory mapped IO accessors
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
` (4 preceding siblings ...)
2019-11-06 14:48 ` [PATCH v1 5/8] pinctrl: lynxpoint: Use %pR to print IO resource Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 7/8] pinctrl: lynxpoint: Convert unsigned to unsigned int Andy Shevchenko
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
Convert driver to use memory mapped IO accessors.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 83 +++++++++++------------
1 file changed, 40 insertions(+), 43 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index 05921729fe78..d3065b5a5f75 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -48,7 +48,7 @@ struct lp_gpio {
struct gpio_chip chip;
struct device *dev;
raw_spinlock_t lock;
- unsigned long reg_base;
+ void __iomem *regs;
};
/*
@@ -80,7 +80,7 @@ struct lp_gpio {
* LP94_CONFIG2 (gpio 94) ...
*/
-static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
+static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
int reg)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
@@ -93,29 +93,29 @@ static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
/* bitmapped registers */
reg_offset = (offset / 32) * 4;
- return lg->reg_base + reg + reg_offset;
+ return lg->regs + reg + reg_offset;
}
static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
- unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
- unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
- unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
+ void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
+ void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
+ void __iomem *acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
pm_runtime_get(lg->dev); /* should we put if failed */
/* Fail if BIOS reserved pin for ACPI use */
- if (!(inl(acpi_use) & BIT(offset % 32))) {
+ if (!(ioread32(acpi_use) & BIT(offset % 32))) {
dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset);
return -EBUSY;
}
/* Fail if pin is in alternate function mode (not GPIO mode) */
- if (!(inl(reg) & USE_SEL_BIT))
+ if (!(ioread32(reg) & USE_SEL_BIT))
return -ENODEV;
/* enable input sensing */
- outl(inl(conf2) & ~GPINDIS_BIT, conf2);
+ iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2);
return 0;
@@ -124,10 +124,10 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
- unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
+ void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
/* disable input sensing */
- outl(inl(conf2) | GPINDIS_BIT, conf2);
+ iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2);
pm_runtime_put(lg->dev);
}
@@ -137,15 +137,15 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct lp_gpio *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
+ void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
unsigned long flags;
u32 value;
- unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
if (hwirq >= lg->chip.ngpio)
return -EINVAL;
raw_spin_lock_irqsave(&lg->lock, flags);
- value = inl(reg);
+ value = ioread32(reg);
/* set both TRIG_SEL and INV bits to 0 for rising edge */
if (type & IRQ_TYPE_EDGE_RISING)
@@ -163,7 +163,7 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
if (type & IRQ_TYPE_LEVEL_HIGH)
value |= TRIG_SEL_BIT | INT_INV_BIT;
- outl(value, reg);
+ iowrite32(value, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
@@ -171,22 +171,22 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
- return !!(inl(reg) & IN_LVL_BIT);
+ void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
+ return !!(ioread32(reg) & IN_LVL_BIT);
}
static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
- unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
+ void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
if (value)
- outl(inl(reg) | OUT_LVL_BIT, reg);
+ iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
else
- outl(inl(reg) & ~OUT_LVL_BIT, reg);
+ iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
@@ -194,11 +194,11 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
- unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
+ void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
- outl(inl(reg) | DIR_BIT, reg);
+ iowrite32(ioread32(reg) | DIR_BIT, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
@@ -208,13 +208,13 @@ static int lp_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
- unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
+ void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
lp_gpio_set(chip, offset, value);
raw_spin_lock_irqsave(&lg->lock, flags);
- outl(inl(reg) & ~DIR_BIT, reg);
+ iowrite32(ioread32(reg) & ~DIR_BIT, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
@@ -226,7 +226,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct lp_gpio *lg = gpiochip_get_data(gc);
struct irq_chip *chip = irq_data_get_irq_chip(data);
- unsigned long reg, ena, pending;
+ void __iomem *reg, *ena;
+ unsigned long pending;
u32 base, pin;
/* check from GPIO controller which pin triggered the interrupt */
@@ -235,13 +236,13 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
/* Only interrupts that are enabled */
- pending = inl(reg) & inl(ena);
+ pending = ioread32(reg) & ioread32(ena);
for_each_set_bit(pin, &pending, 32) {
unsigned irq;
/* Clear before handling so we don't lose an edge */
- outl(BIT(pin), reg);
+ iowrite32(BIT(pin), reg);
irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
generic_handle_irq(irq);
@@ -263,11 +264,11 @@ static void lp_irq_enable(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct lp_gpio *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
- unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
+ void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
- outl(inl(reg) | BIT(hwirq % 32), reg);
+ iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
@@ -276,11 +277,11 @@ static void lp_irq_disable(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct lp_gpio *lg = gpiochip_get_data(gc);
u32 hwirq = irqd_to_hwirq(d);
- unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
+ void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
- outl(inl(reg) & ~BIT(hwirq % 32), reg);
+ iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
@@ -297,16 +298,16 @@ static struct irq_chip lp_irqchip = {
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
- unsigned long reg;
+ void __iomem *reg;
unsigned base;
for (base = 0; base < lg->chip.ngpio; base += 32) {
/* disable gpio pin interrupts */
reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
- outl(0, reg);
+ iowrite32(0, reg);
/* Clear interrupt status register */
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
- outl(0xffffffff, reg);
+ iowrite32(0xffffffff, reg);
}
return 0;
@@ -318,7 +319,6 @@ static int lp_gpio_probe(struct platform_device *pdev)
struct gpio_chip *gc;
struct resource *io_rc, *irq_rc;
struct device *dev = &pdev->dev;
- unsigned long reg_len;
int ret = -ENODEV;
lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
@@ -329,18 +329,14 @@ static int lp_gpio_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, lg);
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
- irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-
if (!io_rc) {
dev_err(dev, "missing IO resources\n");
return -EINVAL;
}
- lg->reg_base = io_rc->start;
- reg_len = resource_size(io_rc);
-
- if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
- dev_err(dev, "failed requesting IO region %pR\n", &io_rc);
+ lg->regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
+ if (!lg->regs) {
+ dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
return -EBUSY;
}
@@ -361,6 +357,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
gc->parent = dev;
/* set up interrupts */
+ irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (irq_rc && irq_rc->start) {
struct gpio_irq_chip *girq;
@@ -403,14 +400,14 @@ static int lp_gpio_runtime_resume(struct device *dev)
static int lp_gpio_resume(struct device *dev)
{
struct lp_gpio *lg = dev_get_drvdata(dev);
- unsigned long reg;
+ void __iomem *reg;
int i;
/* on some hardware suspend clears input sensing, re-enable it here */
for (i = 0; i < lg->chip.ngpio; i++) {
if (gpiochip_is_requested(&lg->chip, i) != NULL) {
reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
- outl(inl(reg) & ~GPINDIS_BIT, reg);
+ iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
}
}
return 0;
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v1 7/8] pinctrl: lynxpoint: Convert unsigned to unsigned int
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
` (5 preceding siblings ...)
2019-11-06 14:48 ` [PATCH v1 6/8] pinctrl: lynxpoint: Switch to memory mapped IO accessors Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-06 14:48 ` [PATCH v1 8/8] pinctrl: lynxpoint: Move ->remove closer to ->probe() Andy Shevchenko
2019-11-13 9:54 ` [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Linus Walleij
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
Simple type conversion with no functional change implied.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 24 +++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index d3065b5a5f75..49dcdc2c205d 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -80,7 +80,7 @@ struct lp_gpio {
* LP94_CONFIG2 (gpio 94) ...
*/
-static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
+static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
int reg)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
@@ -96,7 +96,7 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
return lg->regs + reg + reg_offset;
}
-static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
+static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
@@ -121,7 +121,7 @@ static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
return 0;
}
-static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
+static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
@@ -132,7 +132,7 @@ static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
pm_runtime_put(lg->dev);
}
-static int lp_irq_type(struct irq_data *d, unsigned type)
+static int lp_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct lp_gpio *lg = gpiochip_get_data(gc);
@@ -169,13 +169,13 @@ static int lp_irq_type(struct irq_data *d, unsigned type)
return 0;
}
-static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
return !!(ioread32(reg) & IN_LVL_BIT);
}
-static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
@@ -191,7 +191,7 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
-static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
@@ -204,8 +204,8 @@ static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
return 0;
}
-static int lp_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
+static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
+ int value)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
@@ -239,7 +239,7 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
pending = ioread32(reg) & ioread32(ena);
for_each_set_bit(pin, &pending, 32) {
- unsigned irq;
+ unsigned int irq;
/* Clear before handling so we don't lose an edge */
iowrite32(BIT(pin), reg);
@@ -299,7 +299,7 @@ static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct lp_gpio *lg = gpiochip_get_data(chip);
void __iomem *reg;
- unsigned base;
+ unsigned int base;
for (base = 0; base < lg->chip.ngpio; base += 32) {
/* disable gpio pin interrupts */
@@ -371,7 +371,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
- girq->parents[0] = (unsigned)irq_rc->start;
+ girq->parents[0] = (unsigned int)irq_rc->start;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
}
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v1 8/8] pinctrl: lynxpoint: Move ->remove closer to ->probe()
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
` (6 preceding siblings ...)
2019-11-06 14:48 ` [PATCH v1 7/8] pinctrl: lynxpoint: Convert unsigned to unsigned int Andy Shevchenko
@ 2019-11-06 14:48 ` Andy Shevchenko
2019-11-13 9:54 ` [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Linus Walleij
8 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-06 14:48 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Bartosz Golaszewski, Linus Walleij
Cc: Andy Shevchenko
Consolidate ->remove and ->probe() callbacks for better maintenance.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-lynxpoint.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index 49dcdc2c205d..43dc15b9ad4a 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -387,6 +387,12 @@ static int lp_gpio_probe(struct platform_device *pdev)
return 0;
}
+static int lp_gpio_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
static int lp_gpio_runtime_suspend(struct device *dev)
{
return 0;
@@ -426,12 +432,6 @@ static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
-static int lp_gpio_remove(struct platform_device *pdev)
-{
- pm_runtime_disable(&pdev->dev);
- return 0;
-}
-
static struct platform_driver lp_gpio_driver = {
.probe = lp_gpio_probe,
.remove = lp_gpio_remove,
--
2.24.0.rc1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella
2019-11-06 14:48 [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Andy Shevchenko
` (7 preceding siblings ...)
2019-11-06 14:48 ` [PATCH v1 8/8] pinctrl: lynxpoint: Move ->remove closer to ->probe() Andy Shevchenko
@ 2019-11-13 9:54 ` Linus Walleij
2019-11-25 12:02 ` Andy Shevchenko
8 siblings, 1 reply; 15+ messages in thread
From: Linus Walleij @ 2019-11-13 9:54 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Mika Westerberg, open list:GPIO SUBSYSTEM, Bartosz Golaszewski
On Wed, Nov 6, 2019 at 3:48 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> Intel Lynxpoint GPIO is actually half way to the Chassis specification that has
> been established starting from Intel Skylake. It has some pin control
> properties we may utilize. To achieve this, move the driver under pin control
> umbrella and do a bunch of clean ups.
>
> This is the first step. Next step will be to convert it to the actual pin
> control driver.
>
> The series has been tested on Harrisbeach Ultrabook where Lynxpoint GPIO is
> exposed to the OS.
>
> Andy Shevchenko (8):
> pinctrl: lynxpoint: Move GPIO driver to pin controller folder
> pinctrl: lynxpoint: Use raw_spinlock for locking
> pinctrl: lynxpoint: Correct amount of pins
> pinctrl: lynxpoint: Keep pointer to struct device instead of its
> container
> pinctrl: lynxpoint: Use %pR to print IO resource
> pinctrl: lynxpoint: Switch to memory mapped IO accessors
> pinctrl: lynxpoint: Convert unsigned to unsigned int
> pinctrl: lynxpoint: Move ->remove closer to ->probe()
I'm a big fan of this refactoring.
Can you send this series as a separate pull request that I can pull into
the GPIO tree rather than pin control, or maybe both, once you're
pleased with it?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella
2019-11-13 9:54 ` [PATCH v1 0/8] pinctrl: intel: Move Lynxpoint to pin control umbrella Linus Walleij
@ 2019-11-25 12:02 ` Andy Shevchenko
0 siblings, 0 replies; 15+ messages in thread
From: Andy Shevchenko @ 2019-11-25 12:02 UTC (permalink / raw)
To: Linus Walleij
Cc: Mika Westerberg, open list:GPIO SUBSYSTEM, Bartosz Golaszewski
On Wed, Nov 13, 2019 at 10:54:36AM +0100, Linus Walleij wrote:
> On Wed, Nov 6, 2019 at 3:48 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
>
> > Intel Lynxpoint GPIO is actually half way to the Chassis specification that has
> > been established starting from Intel Skylake. It has some pin control
> > properties we may utilize. To achieve this, move the driver under pin control
> > umbrella and do a bunch of clean ups.
> >
> > This is the first step. Next step will be to convert it to the actual pin
> > control driver.
> >
> > The series has been tested on Harrisbeach Ultrabook where Lynxpoint GPIO is
> > exposed to the OS.
> >
> > Andy Shevchenko (8):
> > pinctrl: lynxpoint: Move GPIO driver to pin controller folder
> > pinctrl: lynxpoint: Use raw_spinlock for locking
> > pinctrl: lynxpoint: Correct amount of pins
> > pinctrl: lynxpoint: Keep pointer to struct device instead of its
> > container
> > pinctrl: lynxpoint: Use %pR to print IO resource
> > pinctrl: lynxpoint: Switch to memory mapped IO accessors
> > pinctrl: lynxpoint: Convert unsigned to unsigned int
> > pinctrl: lynxpoint: Move ->remove closer to ->probe()
>
> I'm a big fan of this refactoring.
Glad we are on the same page about it!
> Can you send this series as a separate pull request that I can pull into
> the GPIO tree rather than pin control, or maybe both, once you're
> pleased with it?
I have done more and it still requires some work. I will send v2 after merge
window being closed.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 15+ messages in thread