From: David Woodhouse <dwmw2@infradead.org> To: x86@kernel.org Cc: iommu <iommu@lists.linux-foundation.org>, kvm <kvm@vger.kernel.org>, linux-hyperv@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com> Subject: [PATCH 03/13] x86/ioapic: Handle Extended Destination ID field in RTE Date: Mon, 5 Oct 2020 16:28:46 +0100 Message-ID: <20201005152856.974112-3-dwmw2@infradead.org> (raw) In-Reply-To: <20201005152856.974112-1-dwmw2@infradead.org> From: David Woodhouse <dwmw@amazon.co.uk> The IOAPIC Redirection Table Entries contain an 8-bit Extended Destination ID field which maps to bits 11-4 of the MSI address. The lowest bit is used to indicate remappable format, when interrupt remapping is in use. A hypervisor can use the other 7 bits to permit guests to address up to 15 bits of APIC IDs, thus allowing 32768 vCPUs before having to expose a vIOMMU and interrupt remapping to the guest. No behavioural change in this patch, since nothing yet permits APIC IDs above 255 to be used with the non-IR IOAPIC domain. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> --- arch/x86/include/asm/io_apic.h | 3 ++- arch/x86/kernel/apic/io_apic.c | 19 +++++++++++++------ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index a1a26f6d3aa4..e65a0b7379d0 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -78,7 +78,8 @@ struct IO_APIC_route_entry { mask : 1, /* 0: enabled, 1: disabled */ __reserved_2 : 15; - __u32 __reserved_3 : 24, + __u32 __reserved_3 : 17, + ext_dest : 7, dest : 8; } __attribute__ ((packed)); diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index a33380059db6..aa9a3b54a96c 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1239,10 +1239,10 @@ static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) buf, (ir_entry->index2 << 15) | ir_entry->index, ir_entry->zero); else - printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", + printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf, entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ? - "logical " : "physical", + "logical " : "physical", entry.ext_dest, entry.dest, entry.delivery_mode); } } @@ -1410,6 +1410,7 @@ void native_restore_boot_irq_mode(void) */ if (ioapic_i8259.pin != -1) { struct IO_APIC_route_entry entry; + u32 apic_id = read_apic_id(); memset(&entry, 0, sizeof(entry)); entry.mask = IOAPIC_UNMASKED; @@ -1417,7 +1418,8 @@ void native_restore_boot_irq_mode(void) entry.polarity = IOAPIC_POL_HIGH; entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; entry.delivery_mode = dest_ExtINT; - entry.dest = read_apic_id(); + entry.dest = apic_id & 0xff; + entry.ext_dest = apic_id >> 8; /* * Add it to the IO-APIC irq-routing table: @@ -1861,7 +1863,8 @@ static void ioapic_configure_entry(struct irq_data *irqd) * ioapic chip to verify that. */ if (irqd->chip == &ioapic_chip) { - mpd->entry.dest = cfg->dest_apicid; + mpd->entry.dest = cfg->dest_apicid & 0xff; + mpd->entry.ext_dest = cfg->dest_apicid >> 8; mpd->entry.vector = cfg->vector; } for_each_irq_pin(entry, mpd->irq_2_pin) @@ -2027,6 +2030,7 @@ static inline void __init unlock_ExtINT_logic(void) int apic, pin, i; struct IO_APIC_route_entry entry0, entry1; unsigned char save_control, save_freq_select; + u32 apic_id; pin = find_isa_irq_pin(8, mp_INT); if (pin == -1) { @@ -2042,11 +2046,13 @@ static inline void __init unlock_ExtINT_logic(void) entry0 = ioapic_read_entry(apic, pin); clear_IO_APIC_pin(apic, pin); + apic_id = hard_smp_processor_id(); memset(&entry1, 0, sizeof(entry1)); entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; entry1.mask = IOAPIC_UNMASKED; - entry1.dest = hard_smp_processor_id(); + entry1.dest = apic_id & 0xff; + entry1.ext_dest = apic_id >> 8; entry1.delivery_mode = dest_ExtINT; entry1.polarity = entry0.polarity; entry1.trigger = IOAPIC_EDGE; @@ -2949,7 +2955,8 @@ static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, memset(entry, 0, sizeof(*entry)); entry->delivery_mode = apic->irq_delivery_mode; entry->dest_mode = apic->irq_dest_mode; - entry->dest = cfg->dest_apicid; + entry->dest = cfg->dest_apicid & 0xff; + entry->ext_dest = cfg->dest_apicid >> 8; entry->vector = cfg->vector; entry->trigger = data->trigger; entry->polarity = data->polarity; -- 2.26.2
next prev parent reply index Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-05 15:28 [PATCH 0/13] Fix per-domain IRQ affinity, allow >255 CPUs on x86 without IRQ remapping David Woodhouse 2020-10-05 15:28 ` [PATCH 01/13] x86/apic: Use x2apic in guest kernels even with unusable CPUs David Woodhouse 2020-10-05 15:28 ` [PATCH 02/13] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse 2020-10-06 20:45 ` Thomas Gleixner 2020-10-05 15:28 ` David Woodhouse [this message] 2020-10-05 15:28 ` [PATCH 04/13] x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where available David Woodhouse 2020-10-05 15:28 ` [PATCH 05/13] genirq: Prepare for default affinity to be passed to __irq_alloc_descs() David Woodhouse 2020-10-06 21:01 ` Thomas Gleixner 2020-10-06 21:07 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 06/13] genirq: Add default_affinity argument " David Woodhouse 2020-10-06 21:06 ` Thomas Gleixner 2020-10-05 15:28 ` [PATCH 07/13] irqdomain: Add max_affinity argument to irq_domain_alloc_descs() David Woodhouse 2020-10-06 21:26 ` Thomas Gleixner 2020-10-07 7:19 ` David Woodhouse 2020-10-07 13:37 ` Thomas Gleixner 2020-10-07 14:10 ` David Woodhouse 2020-10-07 15:57 ` Thomas Gleixner 2020-10-07 16:11 ` David Woodhouse 2020-10-07 20:53 ` Thomas Gleixner 2020-10-08 7:21 ` David Woodhouse 2020-10-08 9:34 ` Thomas Gleixner 2020-10-08 11:10 ` David Woodhouse 2020-10-08 12:40 ` Thomas Gleixner 2020-10-09 7:54 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 08/13] genirq: Add irq_domain_set_affinity() David Woodhouse 2020-10-06 21:32 ` Thomas Gleixner 2020-10-07 7:22 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 09/13] x86/irq: Add x86_non_ir_cpumask David Woodhouse 2020-10-06 21:42 ` Thomas Gleixner 2020-10-07 7:25 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 10/13] x86/irq: Limit IOAPIC and MSI domains' affinity without IR David Woodhouse 2020-10-06 21:54 ` Thomas Gleixner 2020-10-07 7:48 ` David Woodhouse 2020-10-07 12:59 ` Thomas Gleixner 2020-10-07 13:08 ` David Woodhouse 2020-10-07 14:05 ` Thomas Gleixner 2020-10-07 14:23 ` David Woodhouse 2020-10-07 16:02 ` Thomas Gleixner 2020-10-07 16:15 ` David Woodhouse 2020-10-07 15:05 ` David Woodhouse 2020-10-07 15:25 ` Thomas Gleixner 2020-10-07 15:46 ` David Woodhouse 2020-10-07 17:23 ` Thomas Gleixner 2020-10-07 17:34 ` David Woodhouse 2020-10-05 15:28 ` [PATCH 11/13] x86/smp: Allow more than 255 CPUs even without interrupt remapping David Woodhouse 2020-10-05 15:28 ` [PATCH 12/13] iommu/irq_remapping: Kill most of hyperv-iommu.c now it's redundant David Woodhouse 2020-10-05 15:28 ` [PATCH 13/13] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse 2020-10-07 8:14 ` Paolo Bonzini 2020-10-07 8:59 ` David Woodhouse 2020-10-07 11:15 ` Paolo Bonzini 2020-10-07 12:04 ` David Woodhouse
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