From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: "Zhi, Yong" <yong.zhi@intel.com>
Cc: "linux-media@vger.kernel.org" <linux-media@vger.kernel.org>,
"tfiga@chromium.org" <tfiga@chromium.org>,
"mchehab@kernel.org" <mchehab@kernel.org>,
"hans.verkuil@cisco.com" <hans.verkuil@cisco.com>,
"laurent.pinchart@ideasonboard.com"
<laurent.pinchart@ideasonboard.com>,
"Mani, Rajmohan" <rajmohan.mani@intel.com>,
"Zheng, Jian Xu" <jian.xu.zheng@intel.com>,
"Hu, Jerry W" <jerry.w.hu@intel.com>,
"Toivonen, Tuukka" <tuukka.toivonen@intel.com>,
"Qiu, Tian Shu" <tian.shu.qiu@intel.com>,
"Cao, Bingbu" <bingbu.cao@intel.com>,
"Li, Chao C" <chao.c.li@intel.com>
Subject: Re: [PATCH v7 03/16] v4l: Add Intel IPU3 meta data uAPI
Date: Sat, 1 Dec 2018 22:57:18 +0200 [thread overview]
Message-ID: <20181201205717.2q3u6qf576zhmynj@kekkonen.localdomain> (raw)
Message-ID: <20181201205718.ExW_z2QkXlNW-j0IfTlEbuupxo3IcT5DftzgH7XZCF8@z> (raw)
In-Reply-To: <C193D76D23A22742993887E6D207B54D3DB335C2@ORSMSX106.amr.corp.intel.com>
Hi Yong,
On Thu, Nov 29, 2018 at 11:06:23PM +0000, Zhi, Yong wrote:
> Hi, Sakari,
>
> > -----Original Message-----
> > From: Sakari Ailus [mailto:sakari.ailus@linux.intel.com]
> > Sent: Thursday, November 29, 2018 4:46 PM
> > To: Zhi, Yong <yong.zhi@intel.com>
> > Cc: linux-media@vger.kernel.org; tfiga@chromium.org;
> > mchehab@kernel.org; hans.verkuil@cisco.com;
> > laurent.pinchart@ideasonboard.com; Mani, Rajmohan
> > <rajmohan.mani@intel.com>; Zheng, Jian Xu <jian.xu.zheng@intel.com>; Hu,
> > Jerry W <jerry.w.hu@intel.com>; Toivonen, Tuukka
> > <tuukka.toivonen@intel.com>; Qiu, Tian Shu <tian.shu.qiu@intel.com>; Cao,
> > Bingbu <bingbu.cao@intel.com>; Li, Chao C <chao.c.li@intel.com>
> > Subject: Re: [PATCH v7 03/16] v4l: Add Intel IPU3 meta data uAPI
> >
> > Hi Yong,
> >
> > On Fri, Nov 16, 2018 at 10:37:00PM +0000, Zhi, Yong wrote:
> > ...
> > > > > +/**
> > > > > + * struct ipu3_uapi_shd_grid_config - Bayer shading(darkening)
> > > > > +correction
> > > > > + *
> > > > > + * @width: Grid horizontal dimensions, u8, [8, 128], default 73
> > > > > + * @height: Grid vertical dimensions, u8, [8, 128], default 56
> > > > > + * @block_width_log2: Log2 of the width of the grid cell in pixel
> > > > count
> > > > > + * u4, [0, 15], default value 5.
> > > > > + * @__reserved0: reserved
> > > > > + * @block_height_log2: Log2 of the height of the grid cell in pixel
> > > > count
> > > > > + * u4, [0, 15], default value 6.
> > > > > + * @__reserved1: reserved
> > > > > + * @grid_height_per_slice: SHD_MAX_CELLS_PER_SET/width.
> > > > > + * (with SHD_MAX_CELLS_PER_SET =
> > 146).
> > > > > + * @x_start: X value of top left corner of sensor relative to ROI
> > > > > + * u12, [-4096, 0]. default 0, only negative values.
> > > > > + * @y_start: Y value of top left corner of sensor relative to ROI
> > > > > + * u12, [-4096, 0]. default 0, only negative values.
> > > >
> > > > I suppose u12 is incorrect here, if the value is signed --- and
> > > > negative (sign bit) if not 0?
> > > >
> > >
> > > The value will be written to 13 bit register, should use s12.0.
> >
> > If you have s12, that means the most significant bit is the sign bit. So if the
> > smallest value is -4096, you'd need s13.
> >
> > But where is the sign bit, i.e. is this either s13 or s16?
> >
>
> The notation of s12.0 means 13 bit with fraction bit as 0 right?
In s12.0, bit 11 is the sign bit, and bits 10--0 are the integer part. The
smallest number that can be represented is thus -2048 (not -4096).
>
> > >
> > > > > + */
> > > > > +struct ipu3_uapi_shd_grid_config {
> > > > > + /* reg 0 */
> > > > > + __u8 width;
> > > > > + __u8 height;
> > > > > + __u8 block_width_log2:3;
> > > > > + __u8 __reserved0:1;
> > > > > + __u8 block_height_log2:3;
> > > > > + __u8 __reserved1:1;
> > > > > + __u8 grid_height_per_slice;
> > > > > + /* reg 1 */
> > > > > + __s16 x_start;
> > > > > + __s16 y_start;
> > > > > +} __packed;
> >
> > ...
> >
> > > > > +/**
> > > > > + * struct ipu3_uapi_iefd_cux2_1 - Calculate power of non-directed
> > denoise
> > > > > + * element apply.
> > > > > + * @x0: X0 point of Config Unit, u9.0, default 0.
> > > > > + * @x1: X1 point of Config Unit, u9.0, default 0.
> > > > > + * @a01: Slope A of Config Unit, s4.4, default 0.
> > > >
> > > > The field is marked unsigned below. Which one is correct?
> > > >
> > >
> > > They are both correct, however, s4.4 is the internal representation
> > > used by CU, the inputs are unsigned, I will add a note in v8, same
> > > applies to the few other places as you commented.
> >
> > I still find this rather confusing. Is there a sign bit or is there not?
> >
>
> It's unsigned number from driver perspective, all CU inputs are unsigned,
> however, they will be "converted" to signed for FW/HW to use. I have to
> consult FW expert if more clarification is needed.
I think that would be good to have; if you somehow convert an unsigned
integer to a negative number, there's more than just the type cast there.
--
Kind regards,
Sakari Ailus
sakari.ailus@linux.intel.com
next prev parent reply other threads:[~2018-12-01 20:57 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-29 22:22 [PATCH v7 00/16] Intel IPU3 ImgU patchset Yong Zhi
2018-10-29 22:22 ` [PATCH v7 01/16] v4l: Add Intel IPU3 meta buffer formats Yong Zhi
2018-11-02 12:59 ` Mauro Carvalho Chehab
2018-11-02 13:05 ` Mauro Carvalho Chehab
2018-11-29 19:16 ` Laurent Pinchart
2018-11-29 23:12 ` Zhi, Yong
2018-10-29 22:22 ` [PATCH v7 02/16] doc-rst: Add Intel IPU3 documentation Yong Zhi
2018-11-29 22:50 ` Laurent Pinchart
2018-12-13 9:38 ` Sakari Ailus
2018-12-13 10:41 ` Laurent Pinchart
2018-12-13 10:50 ` Sakari Ailus
2018-12-13 9:38 ` [PATCH 1/1] staging/ipu3-imgu: Address documentation comments Sakari Ailus
2018-10-29 22:22 ` [PATCH v7 03/16] v4l: Add Intel IPU3 meta data uAPI Yong Zhi
2018-11-02 13:02 ` Sakari Ailus
2018-11-16 22:37 ` Zhi, Yong
[not found] ` <20181129224548.qwbkau6suipt2veq@kekkonen.localdomain>
2018-11-29 23:06 ` Zhi, Yong
2018-11-29 23:06 ` Zhi, Yong
2018-12-01 20:57 ` Sakari Ailus [this message]
2018-12-01 20:57 ` Sakari Ailus
2018-11-02 13:49 ` Mauro Carvalho Chehab
2018-11-02 14:04 ` Tomasz Figa
2018-11-06 23:27 ` Mani, Rajmohan
2018-11-15 10:52 ` Hans Verkuil
2018-11-29 0:41 ` Mani, Rajmohan
2018-11-06 18:25 ` Zhi, Yong
2018-11-15 12:51 ` Hans Verkuil
2018-11-21 18:45 ` Zhi, Yong
2018-10-29 22:22 ` [PATCH v7 04/16] intel-ipu3: abi: Add register definitions and enum Yong Zhi
2018-10-29 22:22 ` [PATCH v7 05/16] intel-ipu3: abi: Add structs Yong Zhi
2018-11-05 8:27 ` Sakari Ailus
2018-11-05 19:05 ` Mani, Rajmohan
2018-11-06 8:04 ` Sakari Ailus
2018-11-06 23:31 ` Mani, Rajmohan
2018-10-29 22:23 ` [PATCH v7 06/16] intel-ipu3: mmu: Implement driver Yong Zhi
2018-11-05 11:55 ` Sakari Ailus
2018-11-06 5:50 ` Zhi, Yong
2018-11-06 5:56 ` Tomasz Figa
2018-10-29 22:23 ` [PATCH v7 07/16] intel-ipu3: Implement DMA mapping functions Yong Zhi
2018-10-29 22:23 ` [PATCH v7 08/16] intel-ipu3: css: Add dma buff pool utility functions Yong Zhi
2018-11-08 15:36 ` Sakari Ailus
2018-11-09 23:16 ` Zhi, Yong
2018-11-12 9:21 ` Sakari Ailus
2018-10-29 22:23 ` [PATCH v7 09/16] intel-ipu3: css: Add support for firmware management Yong Zhi
2018-11-28 22:22 ` Sakari Ailus
2018-10-29 22:23 ` [PATCH v7 11/16] intel-ipu3: css: Compute and program ccs Yong Zhi
2018-10-29 22:23 ` [PATCH v7 12/16] intel-ipu3: css: Initialize css hardware Yong Zhi
2018-11-09 12:06 ` Sakari Ailus
2018-10-29 22:23 ` [PATCH v7 13/16] intel-ipu3: Add css pipeline programming Yong Zhi
2018-10-29 22:23 ` [PATCH v7 14/16] intel-ipu3: Add v4l2 driver based on media framework Yong Zhi
2018-11-09 12:36 ` Sakari Ailus
2018-11-09 23:26 ` Zhi, Yong
2018-11-15 12:51 ` Hans Verkuil
2018-11-15 16:09 ` Zhi, Yong
2018-10-29 22:23 ` [PATCH v7 15/16] intel-ipu3: Add imgu top level pci device driver Yong Zhi
2018-11-09 12:54 ` Sakari Ailus
2018-11-12 22:16 ` Zhi, Yong
2018-10-29 22:23 ` [PATCH v7 16/16] intel-ipu3: Add dual pipe support Yong Zhi
2018-11-01 12:03 ` [PATCH v7 00/16] Intel IPU3 ImgU patchset Sakari Ailus
2018-11-07 4:16 ` Bing Bu Cao
2018-11-09 1:28 ` Zhi, Yong
2018-11-09 11:28 ` Sakari Ailus
2018-11-09 10:09 ` Sakari Ailus
2018-11-12 4:31 ` Bing Bu Cao
2018-11-13 10:31 ` Sakari Ailus
2018-11-13 11:04 ` Bing Bu Cao
2018-11-13 21:58 ` Sakari Ailus
2018-11-14 7:02 ` Bing Bu Cao
2018-11-29 23:09 ` Laurent Pinchart
2018-11-30 13:37 ` Sakari Ailus
2018-11-29 23:07 ` Laurent Pinchart
2018-12-03 9:51 ` Sakari Ailus
2018-12-03 12:34 ` Laurent Pinchart
2018-11-14 0:25 ` jacopo mondi
2018-11-14 7:40 ` Sakari Ailus
2018-11-18 0:12 ` jacopo mondi
2018-11-29 14:43 ` Laurent Pinchart
2018-11-29 19:51 ` Tomasz Figa
2018-11-29 22:54 ` Laurent Pinchart
2018-11-29 22:58 ` Mani, Rajmohan
2018-12-04 16:07 ` Mani, Rajmohan
2018-12-04 16:42 ` Laurent Pinchart
2018-12-04 16:53 ` Mani, Rajmohan
2018-12-05 0:30 ` Mani, Rajmohan
2018-12-11 13:34 ` Laurent Pinchart
2018-12-11 13:43 ` Laurent Pinchart
2018-12-11 14:20 ` Laurent Pinchart
2018-12-16 7:26 ` Laurent Pinchart
2018-12-20 22:25 ` Laurent Pinchart
2018-12-21 3:04 ` Tomasz Figa
2019-01-08 6:54 ` Tomasz Figa
2019-01-09 16:40 ` Jacopo Mondi
2019-01-09 17:00 ` Mani, Rajmohan
2019-01-09 17:25 ` Jacopo Mondi
2019-01-09 18:01 ` Mani, Rajmohan
2019-01-09 18:20 ` Jacopo Mondi
2019-01-09 18:36 ` Mani, Rajmohan
2019-01-10 8:19 ` Jacopo Mondi
2019-01-12 2:06 ` Mani, Rajmohan
2019-01-12 2:30 ` Mani, Rajmohan
2019-01-12 15:10 ` Laurent Pinchart
[not found] ` <6F87890CF0F5204F892DEA1EF0D77A599B323499@fmsmsx122.amr.corp.intel.com>
2019-01-21 5:41 ` Tomasz Figa
2019-01-21 8:07 ` Laurent Pinchart
2019-01-22 16:21 ` Mani, Rajmohan
[not found] ` <6F87890CF0F5204F892DEA1EF0D77A599B31FAF4@fmsmsx122.amr.corp.intel.com>
2019-01-08 23:34 ` Laurent Pinchart
2018-12-12 4:55 ` Bingbu Cao
2018-12-13 22:24 ` Laurent Pinchart
2018-12-14 2:53 ` Bingbu Cao
2018-12-17 3:14 ` Bingbu Cao
2018-12-26 11:03 ` Laurent Pinchart
2019-01-02 2:38 ` Bingbu Cao
2019-01-02 8:20 ` Laurent Pinchart
2019-01-02 20:26 ` Sakari Ailus
2019-01-28 10:09 ` Jacopo Mondi
2019-01-29 8:56 ` Tomasz Figa
2019-02-01 10:04 ` Jacopo Mondi
2019-02-05 6:01 ` Tomasz Figa
2019-03-23 13:02 ` Jacopo Mondi
2019-03-25 3:45 ` Bingbu Cao
2019-03-25 4:06 ` Laurent Pinchart
2019-03-25 8:11 ` Jacopo Mondi
2019-03-25 10:07 ` Bingbu Cao
2019-03-26 11:16 ` Jacopo Mondi
2019-04-08 6:35 ` Bingbu Cao
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