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From: Fredrik Noring <noring@nocrew.org>
To: linux-mips@vger.kernel.org
Subject: [PATCH 083/120] MIPS: PS2: GS: Define Graphics Synthesizer primitive structures
Date: Sun, 1 Sep 2019 18:21:00 +0200
Message-ID: <25b6c975d334c0678ab3963d6c76584ed9471c35.1567326213.git.noring@nocrew.org> (raw)
In-Reply-To: <cover.1567326213.git.noring@nocrew.org>

The Graphics Synthesizer has 4 MiB of local frame buffer memory that is
not directly accessible from the main bus. All drawing operations must
be performed with serialized drawing primitives via the Graphics
Synthesizer interface (GIF), either by DMA or a vector processor[1].

The GS frame buffer is subdivided into rectangular pages, from left to
right, top to bottom. Pages are further subdivided into blocks, with
different arrangements for the PSMCT16 and PSMCT32 pixel storage modes.
Blocks are further subdivided into columns that are finally subdivided
into pixels.

The general purpose GS registers are used to set vertex information,
drawing environment and transmission between buffers for the drawing
primitives. All of them are write-only registers.

The following registers are available. Registers with "_1" and "_2"
suffixes are designed to operate in one of the two drawing contexts.

Register   | Description
-----------+--------------------------------------------------------
PRIM       | Drawing primitive setting
RGBAQ      | Vertex colour setting
ST         | Vertex texture coordinate setting (texture coordinates)
UV         | Vertex texture coordinate setting (texel coordinates)
XYZF2      | Vertex coordinate value setting
XYZ2       | Vertex coordinate value setting
TEX0_1     | Texture information setting
TEX0_2     | Texture information setting
CLAMP_1    | Texture wrap mode
CLAMP_2    | Texture wrap mode
FOG        | Vertex fog value setting
XYZF3      | Vertex coordinate value setting (without drawing kick)
XYZ3       | Vertex coordinate value setting (without drawing kick)
TEX1_1     | Texture information setting
TEX1_2     | Texture information setting
TEX2_1     | Texture information setting
TEX2_2     | Texture information setting
XYOFFSET_1 | Offset value setting
XYOFFSET_2 | Offset value setting
PRMODECONT | Specification of primitive attribute setting method
PRMODE     | Drawing primitive attribute setting
TEXCLUT    | Colour lookup table position setting
SCANMSK    | Raster address mask setting
MIPTBP1_1  | MIPMAP information setting (Level 1 – 3)
MIPTBP1_2  | MIPMAP information setting (Level 1 – 3)
MIPTBP2_1  | MIPMAP information setting (Level 4 – 6)
MIPTBP2_2  | MIPMAP information setting (Level 4 – 6)
TEXA       | Texture alpha value setting
FOGCOL     | Distant fog colour setting
TEXFLUSH   | Texture page buffer disabling
SCISSOR_1  | Scissoring area setting
SCISSOR_2  | Scissoring area setting
ALPHA_1    | Alpha blending setting
ALPHA_2    | Alpha blending setting
DIMX       | Dither matrix setting
DTHE       | Dither control
COLCLAMP   | Colour clamp control
TEST_1     | Pixel test control
TEST_2     | Pixel test control
PABE       | Alpha blending control in pixel units
FBA_1      | Alpha correction value
FBA_2      | Alpha correction value
FRAME_1    | Frame buffer setting
FRAME_2    | Frame buffer setting
ZBUF_1     | Z buffer setting
ZBUF_2     | Z buffer setting
BITBLTBUF  | Setting for transmission between buffers
TRXPOS     | Specification for transmission area in buffers
TRXREG     | Specification for transmission area in buffers
TRXDIR     | Activation of transmission between buffers
HWREG      | Data port for transmission between buffers
SIGNAL     | SIGNAL event occurrence request
FINISH     | FINISH event occurrence request
LABEL      | LABEL event occurrence request
-----------+--------------------------------------------------------

References:

[1] "GS User's Manual", version 6.0, Sony Computer Entertainment Inc.,
    pp. 158, 161-175.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
 arch/mips/include/uapi/asm/gs.h | 723 ++++++++++++++++++++++++++++++++
 1 file changed, 723 insertions(+)
 create mode 100644 arch/mips/include/uapi/asm/gs.h

diff --git a/arch/mips/include/uapi/asm/gs.h b/arch/mips/include/uapi/asm/gs.h
new file mode 100644
index 000000000000..074bb62a4bd0
--- /dev/null
+++ b/arch/mips/include/uapi/asm/gs.h
@@ -0,0 +1,723 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PlayStation 2 Graphics Synthesizer (GS)
+ *
+ * Copyright (C) 2019 Fredrik Noring
+ */
+
+#ifndef _UAPI_MIPS_ASM_GS_H
+#define _UAPI_MIPS_ASM_GS_H
+
+#include <asm/bitfield.h>
+
+/**
+ * DOC: The PlayStation 2 Graphics Synthesizer
+ *
+ * The Graphics Synthesizer frame buffer is subdivided into rectangular pages,
+ * from left to right, top to bottom. Pages are further subdivided into blocks,
+ * with different arrangements for the PSMCT16 and PSMCT32 pixel storage modes.
+ * Blocks are further subdivided into columns that are finally subdivided into
+ * pixels.
+ *
+ * The frame buffer width (FBW) is defined as the pixel width divided by 64,
+ * where 64 is the width of a page for PSMCT16 and PSMCT32.
+ *
+ * The texture base pointer (TBP), color base pointer (CBP), source base
+ * pointer (SBP) and destination base pointer (DBP) are all addressed by block.
+ *
+ * As an example, consider the frame buffer resolution 1920x1080@16 that uses
+ * 1920*1080*2 = 4147200 bytes of the 4 MiB = 4194304 bytes available memory.
+ * There are 4194304-4147200 = 47104 bytes of free memory. The FBW is 1920/64
+ * = 30, which means it is 30 pages wide. However, 1080/GS_PSM_CT32_PAGE_HEIGHT
+ * = 1080/64 = 16.875, which means that the last row of blocks are unused in
+ * the last page row. These make up 30*4 = 120 blocks of the 47104/256 = 184
+ * blocks available. To make effective use of free memory for this resolution
+ * in particular, it is essential to compute accurate block addresses.
+ */
+
+#define GS_COLUMNS_PER_BLOCK	  4
+#define GS_BLOCKS_PER_PAGE	 32
+
+#define GS_PAGE_COUNT		512
+#define GS_BLOCK_COUNT	(GS_PAGE_COUNT * GS_BLOCKS_PER_PAGE)
+#define GS_COLUMN_COUNT	(GS_BLOCK_COUNT * GS_COLUMNS_PER_PAGE)
+
+#define GS_COLUMN_SIZE		 64
+#define GS_BLOCK_SIZE	(GS_COLUMNS_PER_BLOCK * GS_COLUMN_SIZE)
+#define GS_PAGE_SIZE	(GS_BLOCKS_PER_PAGE * GS_BLOCK_SIZE)
+#define GS_MEMORY_SIZE	(GS_PAGE_COUNT * GS_PAGE_SIZE)	/* 4 MiB of memory */
+
+#define GS_FB_PAGE_WIDTH	  64
+#define GS_FB_BASE_DIVISOR	2048	/* FIXME: GS_FB_PAGE_WORDS */
+
+/* All pixel storage formats have 1 block column and 4 block rows. */
+#define GS_BLOCK_COLS			 1
+#define GS_BLOCK_ROWS			 4
+
+/* 4 bit (16 color) texture pixel storage format. */
+#define GS_PSMT4_PAGE_COLS		 4
+#define GS_PSMT4_PAGE_ROWS		 8
+#define GS_PSMT4_COLUMN_WIDTH		32
+#define GS_PSMT4_COLUMN_HEIGHT		 4
+#define GS_PSMT4_BLOCK_WIDTH	 (GS_PSMT4_COLUMN_WIDTH * GS_BLOCK_COLS)
+#define GS_PSMT4_BLOCK_HEIGHT	 (GS_PSMT4_COLUMN_HEIGHT * GS_BLOCK_ROWS)
+#define GS_PSMT4_PAGE_WIDTH	 (GS_PSMT4_BLOCK_WIDTH * GS_PSMT4_PAGE_COLS)
+#define GS_PSMT4_PAGE_HEIGHT	 (GS_PSMT4_BLOCK_HEIGHT * GS_PSMT4_PAGE_ROWS)
+
+/* 8 bit (256 color) texture pixel storage format. */
+#define GS_PSMT8_PAGE_COLS		 8
+#define GS_PSMT8_PAGE_ROWS		 4
+#define GS_PSMT8_COLUMN_WIDTH		16
+#define GS_PSMT8_COLUMN_HEIGHT		 4
+#define GS_PSMT8_BLOCK_WIDTH	 (GS_PSMT8_COLUMN_WIDTH * GS_BLOCK_COLS)
+#define GS_PSMT8_BLOCK_HEIGHT	 (GS_PSMT8_COLUMN_HEIGHT * GS_BLOCK_ROWS)
+#define GS_PSMT8_PAGE_WIDTH	 (GS_PSMT8_BLOCK_WIDTH * GS_PSMT8_PAGE_COLS)
+#define GS_PSMT8_PAGE_HEIGHT	 (GS_PSMT8_BLOCK_HEIGHT * GS_PSMT8_PAGE_ROWS)
+
+/* 16 bit (true color) frame buffer and texture pixel storage format. */
+#define GS_PSM_CT16_PAGE_COLS		 4
+#define GS_PSM_CT16_PAGE_ROWS		 8
+#define GS_PSM_CT16_COLUMN_WIDTH	 8
+#define GS_PSM_CT16_COLUMN_HEIGHT	 2
+#define GS_PSM_CT16_BLOCK_WIDTH	 (GS_PSM_CT16_COLUMN_WIDTH * GS_BLOCK_COLS)
+#define GS_PSM_CT16_BLOCK_HEIGHT (GS_PSM_CT16_COLUMN_HEIGHT * GS_BLOCK_ROWS)
+#define GS_PSM_CT16_PAGE_WIDTH	 (GS_PSM_CT16_BLOCK_WIDTH * GS_PSM_CT16_PAGE_COLS)
+#define GS_PSM_CT16_PAGE_HEIGHT	 (GS_PSM_CT16_BLOCK_HEIGHT * GS_PSM_CT16_PAGE_ROWS)
+
+/* 32 bit (true color) frame buffer and texture pixel storage format. */
+#define GS_PSM_CT32_PAGE_COLS		 8
+#define GS_PSM_CT32_PAGE_ROWS		 4
+#define GS_PSM_CT32_COLUMN_WIDTH	16
+#define GS_PSM_CT32_COLUMN_HEIGHT	 2
+#define GS_PSM_CT32_BLOCK_WIDTH	 (GS_PSM_CT32_COLUMN_WIDTH * GS_BLOCK_COLS)
+#define GS_PSM_CT32_BLOCK_HEIGHT (GS_PSM_CT32_COLUMN_HEIGHT * GS_BLOCK_ROWS)
+#define GS_PSM_CT32_PAGE_WIDTH	 (GS_PSM_CT32_BLOCK_WIDTH * GS_PSM_CT32_PAGE_COLS)
+#define GS_PSM_CT32_PAGE_HEIGHT	 (GS_PSM_CT32_BLOCK_HEIGHT * GS_PSM_CT32_PAGE_ROWS)
+
+#define GS_ALPHA_ONE 	0x80	/* Alpha 0x80 = 1.0 */
+
+/**
+ * struct gs_rgba16 - 16-bit red, green, blue colour and alpha transparency
+ * @a: 1-bit alpha transparency
+ * @b: 5-bit blue colour component
+ * @g: 5-bit green colour component
+ * @r: 5-bit red colour component
+ *
+ * Alpha is treated as 0 when @a is 0, and as %GS_ALPHA_ONE when @a is 1.
+ */
+struct gs_rgba16 {
+	__BITFIELD_FIELD(__u16 a : 1,
+	__BITFIELD_FIELD(__u16 b : 5,
+	__BITFIELD_FIELD(__u16 g : 5,
+	__BITFIELD_FIELD(__u16 r : 5,
+	;))))
+};
+
+/**
+ * struct gs_rgba32 - 32-bit red, green, blue colour and alpha transparency
+ * @a: 8-bit alpha transparency, with %GS_ALPHA_ONE representing 1.0
+ * @b: 8-bit blue colour component
+ * @g: 8-bit green colour component
+ * @r: 8-bit red colour component
+ */
+struct gs_rgba32 {
+	__BITFIELD_FIELD(__u32 a : 8,
+	__BITFIELD_FIELD(__u32 b : 8,
+	__BITFIELD_FIELD(__u32 g : 8,
+	__BITFIELD_FIELD(__u32 r : 8,
+	;))))
+};
+
+enum gs_register_address {
+	gs_addr_prim       = 0x00, gs_addr_rgbaq      = 0x01,
+	gs_addr_st         = 0x02, gs_addr_uv         = 0x03,
+	gs_addr_xyzf2      = 0x04, gs_addr_xyz2       = 0x05,
+	gs_addr_tex0_1     = 0x06, gs_addr_tex0_2     = 0x07,
+	gs_addr_clamp_1    = 0x08, gs_addr_clamp_2    = 0x09,
+	gs_addr_fog        = 0x0a, gs_addr_xyzf3      = 0x0c,
+	gs_addr_xyz3       = 0x0d, gs_addr_tex1_1     = 0x14,
+	gs_addr_tex1_2     = 0x15, gs_addr_tex2_1     = 0x16,
+	gs_addr_tex2_2     = 0x17, gs_addr_xyoffset_1 = 0x18,
+	gs_addr_xyoffset_2 = 0x19, gs_addr_prmodecont = 0x1a,
+	gs_addr_prmode     = 0x1b, gs_addr_texclut    = 0x1c,
+	gs_addr_scanmsk    = 0x22, gs_addr_miptbp1_1  = 0x34,
+	gs_addr_miptbp1_2  = 0x35, gs_addr_miptbp2_1  = 0x36,
+	gs_addr_miptbp2_2  = 0x37, gs_addr_texa       = 0x3b,
+	gs_addr_fogcol     = 0x3d, gs_addr_texflush   = 0x3f,
+	gs_addr_scissor_1  = 0x40, gs_addr_scissor_2  = 0x41,
+	gs_addr_alpha_1    = 0x42, gs_addr_alpha_2    = 0x43,
+	gs_addr_dimx       = 0x44, gs_addr_dthe       = 0x45,
+	gs_addr_colclamp   = 0x46, gs_addr_test_1     = 0x47,
+	gs_addr_test_2     = 0x48, gs_addr_pabe       = 0x49,
+	gs_addr_fba_1      = 0x4a, gs_addr_fba_2      = 0x4b,
+	gs_addr_frame_1    = 0x4c, gs_addr_frame_2    = 0x4d,
+	gs_addr_zbuf_1     = 0x4e, gs_addr_zbuf_2     = 0x4f,
+	gs_addr_bitbltbuf  = 0x50, gs_addr_trxpos     = 0x51,
+	gs_addr_trxreg     = 0x52, gs_addr_trxdir     = 0x53,
+	gs_addr_hwreg      = 0x54, gs_addr_signal     = 0x60,
+	gs_addr_finish     = 0x61, gs_addr_label      = 0x62,
+	gs_addr_nop        = 0x7f
+};
+
+enum gs_prim_fix { gs_fragment_unfixed, gs_fragment_fixed };
+enum gs_prim_ctxt { gs_context_1, gs_context_2 };
+enum gs_prim_fst { gs_texturing_stq, gs_texturing_uv };
+enum gs_prim_aa1 { gs_pass_antialiasing_off, gs_pass_antialiasing_on };
+enum gs_prim_abe { gs_blendning_off, gs_blendning_on };
+enum gs_prim_fge { gs_fogging_off, gs_fogging_on };
+enum gs_prim_tme { gs_texturing_off, gs_texturing_on };
+enum gs_prim_iip { gs_flat_shading, gs_gouraud_shading };
+enum gs_prim_type {
+	gs_point, gs_line, gs_linestrip, gs_triangle,
+	gs_trianglestrip, gs_trianglefan, gs_sprite
+};
+
+/**
+ * struct gs_prim - drawing primitive
+ * @fix: fragment value control
+ * @ctxt: context
+ * @fst: texture coordinate method
+ * @aa1: pass antialiasing
+ * @abe: alpha blendning
+ * @fge: fogging
+ * @tme: texture mapping
+ * @iip: shading method
+ * @prim: type of drawing primitive
+ *
+ * The IIP/TME/FGE/ABE/AA1/FST/CTXT/FIX fields are only enabled when AC is 1
+ * in the PRMODECONT register.
+ */
+struct gs_prim {
+	__BITFIELD_FIELD(__u64 : 53,
+	__BITFIELD_FIELD(__u64 fix : 1,
+	__BITFIELD_FIELD(__u64 ctxt : 1,
+	__BITFIELD_FIELD(__u64 fst : 1,
+	__BITFIELD_FIELD(__u64 aa1 : 1,
+	__BITFIELD_FIELD(__u64 abe : 1,
+	__BITFIELD_FIELD(__u64 fge : 1,
+	__BITFIELD_FIELD(__u64 tme : 1,
+	__BITFIELD_FIELD(__u64 iip : 1,
+	__BITFIELD_FIELD(__u64 prim : 3,
+	;))))))))))
+};
+
+/**
+ * struct gs_prmode - attributes of drawing primitives
+ * @fix: fragment value control
+ * @ctxt: context
+ * @fst: texture coordinate method
+ * @aa1: pass antialiasing
+ * @abe: alpha blendning
+ * @fge: fogging
+ * @tme: texture mapping
+ * @iip: shading method
+ *
+ * The IIP/TME/FGE/ABE/AA1/FST/CTXT/FIX fields are only enabled when AC is 0
+ * in the PRMODECONT register.
+ */
+struct gs_prmode {
+	__BITFIELD_FIELD(__u64 : 53,
+	__BITFIELD_FIELD(__u64 fix : 1,
+	__BITFIELD_FIELD(__u64 ctxt : 1,
+	__BITFIELD_FIELD(__u64 fst : 1,
+	__BITFIELD_FIELD(__u64 aa1 : 1,
+	__BITFIELD_FIELD(__u64 abe : 1,
+	__BITFIELD_FIELD(__u64 fge : 1,
+	__BITFIELD_FIELD(__u64 tme : 1,
+	__BITFIELD_FIELD(__u64 iip : 1,
+	__BITFIELD_FIELD(__u64 : 3,
+	;))))))))))
+};
+
+/**
+ * struct gs_prmodecont - primitive attribute setting method
+ * @ac: enable PRMODE (= 0) or PRIM (= 1)
+ */
+struct gs_prmodecont {
+	__BITFIELD_FIELD(__u64 : 63,
+	__BITFIELD_FIELD(__u64 ac : 1,
+	;))
+};
+
+enum gs_psm {
+	gs_psm_ct32  = 0x00, gs_psm_ct24  = 0x01, gs_psm_ct16 = 0x02,
+	gs_psm_ct16s = 0x0a, gs_psm_gpu24 = 0x12, gs_psm_t8   = 0x13,
+	gs_psm_t4    = 0x14, gs_psm_t8h   = 0x1b, gs_psm_t4hl = 0x24,
+	gs_psm_t4hh  = 0x2c, gs_psm_z32   = 0x30, gs_psm_z24  = 0x31,
+	gs_psm_z16   = 0x32, gs_psm_z16s  = 0x3a
+};
+
+/**
+ * struct gs_bitbltbuf - transmission between buffers
+ * @dpsm: destination pixel format
+ * @dbw: destination width/64
+ * @dbp: destination base word/64
+ * @spsm: source pixel format
+ * @sbw: source width/64
+ * @sbp: source base word/64
+ *
+ * Host -> local: Only destination fields are used.
+ *
+ * Local -> host: Only source fields are used. The pixel formats PSMT4,
+ * PSMT4HL and PSMT4HH cannot be used.
+ *
+ * Local -> local: Both source and destination fields are used. The bits
+ * per pixel for source and destination must be equal.
+ *
+ * The rectangular area wraps around when exceeding the buffer width.
+ *
+ * Limitations on TRXPOS start x coordinate transmissions (not applicable
+ * for local -> host):
+ *
+ *     Multiple of 2: PSMT8, PSMT8H
+ *     Multiple of 4: PSMT4, PSMT4HL, PSMT4HH
+ *
+ * Limitations on TRXREG width (not applicable for local -> host):
+ *
+ *     Multiple of 2: PSMCT32, PSMZ32
+ *     Multiple of 4: PSMCT16, PSMCT16S, PSMZ16, PSMZ16S
+ *     Multiple of 8: PSMCT24, PSMZ24, PSMT8, PSMT8H, PSMT4, PSMT4HL, PSMT4HH
+ */
+struct gs_bitbltbuf {
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 dpsm : 6,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 dbw : 6,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 dbp : 14,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 spsm : 6,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 sbw : 6,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 sbp : 14,
+	;))))))))))))
+};
+
+enum gs_clamp_mode {
+	gs_clamp_repeat, gs_clamp_clamp,
+	gs_clamp_region_clamp, gs_clamp_region_repeat
+};
+
+/**
+ * struct gs_clamp - texture wrap mode
+ * @maxv: upper v clamp parameter
+ * @minv: lower v clamp parameter
+ * @maxu: upper u clamp parameter
+ * @minu: lower u clamp parameter
+ * @wmt: vertical wrap mode
+ * @wms: horizontal wrap mode
+ */
+struct gs_clamp {
+	__BITFIELD_FIELD(__u64 : 20,
+	__BITFIELD_FIELD(__u64 maxv : 10,
+	__BITFIELD_FIELD(__u64 minv : 10,
+	__BITFIELD_FIELD(__u64 maxu : 10,
+	__BITFIELD_FIELD(__u64 minu : 10,
+	__BITFIELD_FIELD(__u64 wmt : 2,
+	__BITFIELD_FIELD(__u64 wms : 2,
+	;)))))))
+};
+
+/**
+ * struct gs_frame_12 - frame buffer
+ * @fbmsk: frame buffer drawing mask
+ * @psm: frame buffer pixel format
+ * @fbw: frame buffer width/64
+ * @fbp: frame buffer base/2048
+ */
+struct gs_frame_12 {
+	__BITFIELD_FIELD(__u64 fbmsk : 32,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 psm : 6,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 fbw : 6,
+	__BITFIELD_FIELD(__u64 : 7,
+	__BITFIELD_FIELD(__u64 fbp : 9,
+	;)))))))
+};
+
+/**
+ * enum gs_scanmsk - raster address mask
+ * @gs_scanmsk_normal: normal drawing (not masked)
+ * @gs_scanmsk_even: drawing of pixel with even y coordinate is prohibited
+ * @gs_scanmsk_odd: drawing of pixel with odd y coordinate is prohibited
+ */
+enum gs_scanmsk {
+	gs_scanmsk_normal,
+	/* Reserved */
+	gs_scanmsk_even = 2,
+	gs_scanmsk_odd
+};
+
+/**
+ * struct gs_scanmsk_12 - raster address mask
+ * @msk: raster address mask
+ */
+struct gs_scanmsk_12 {
+	__BITFIELD_FIELD(__u64 : 62,
+	__BITFIELD_FIELD(__u64 msk : 2,
+	;))
+};
+
+/**
+ * struct gs_scissor_12 - scissoring area
+ * @scay1: lower right y
+ * @scay0: upper left y
+ * @scax1: lower right x
+ * @scax0: upper left x
+ *
+ * All SCISSOR coordinates are in the window coordinate system.
+ */
+struct gs_scissor_12 {
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 scay1 : 11,
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 scay0 : 11,
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 scax1 : 11,
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 scax0 : 11,
+	;))))))))
+};
+
+/**
+ * enum gs_trxpos_dir - transmission direction
+ * @gs_trxpos_dir_ul_lr: upper left -> lower right
+ * @gs_trxpos_dir_ll_ur: lower left -> upper right
+ * @gs_trxpos_dir_ur_ll: upper right -> lower left
+ * @gs_trxpos_dir_lr_ul: lower right -> upper left
+ *
+ * The pixel transmission order is enabled only for local -> local.
+ */
+enum gs_trxpos_dir {
+	gs_trxpos_dir_ul_lr,
+	gs_trxpos_dir_ll_ur,
+	gs_trxpos_dir_ur_ll,
+	gs_trxpos_dir_lr_ul,
+};
+
+/**
+ * struct gs_trxpos - transmission areass in buffers
+ * @dir: Pixel transmission order
+ * @dsay: Destination start y
+ * @dsax: Destination start x
+ * @ssay: Source start y
+ * @ssax: Source start x
+ *
+ * Host -> local: Only destination fields are used. DIR is ignored and the
+ * pixel transmission order is always left to right and top to bottom.
+ *
+ * Local -> host: Only source fields are used. DIR is ignored and the pixel
+ * transmission order is always left to right and top to bottom.
+ *
+ * Local -> local: Both source and destination fields are used. The pixel
+ * transmission order DIR is used.
+ */
+struct gs_trxpos {
+	__BITFIELD_FIELD(__u64 : 3,
+	__BITFIELD_FIELD(__u64 dir : 2,
+	__BITFIELD_FIELD(__u64 dsay : 11,
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 dsax : 11,
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 ssay : 11,
+	__BITFIELD_FIELD(__u64 : 5,
+	__BITFIELD_FIELD(__u64 ssax : 11,
+	;)))))))))
+};
+
+/**
+ * struct gs_trxreg - transmission areas in buffers
+ * @rrh: transmission area height
+ * @rrw: transmission area width
+ *
+ * The transmission coordinates are modulo 2048 (wrap around).
+ */
+struct gs_trxreg {
+	__BITFIELD_FIELD(__u64 : 20,
+	__BITFIELD_FIELD(__u64 rrh : 12,
+	__BITFIELD_FIELD(__u64 : 20,
+	__BITFIELD_FIELD(__u64 rrw : 12,
+	;))))
+};
+
+enum gs_trxdir_xdir {
+	gs_trxdir_host_to_local,
+	gs_trxdir_local_to_host,
+	gs_trxdir_local_to_local,
+	gs_trxdir_nil,				/* Deactivated transmission */
+};
+
+/**
+ * struct gs_trxdir - activation of transmission between buffers
+ * @xdir: transmission direction
+ *
+ * The TRXDIR register specifies the transmission
+ * direction and activates the transmission.
+ */
+struct gs_trxdir {
+	__BITFIELD_FIELD(__u64 : 62,
+	__BITFIELD_FIELD(__u64 xdir : 2,
+	;))
+};
+
+enum gs_alpha_test { gs_alpha_test_off, gs_alpha_test_on };
+enum gs_alpha_method {
+	gs_alpha_method_fail, gs_alpha_method_pass, gs_alpha_method_less,
+	gs_alpha_method_lequal, gs_alpha_method_equal, gs_alpha_method_gequal,
+	gs_alpha_method_greater, gs_alpha_method_notequal
+};
+enum gs_alpha_failed {
+	gs_alpha_failed_keep, gs_alpha_failed_fb_only,
+	gs_alpha_failed_zb_only, gs_alpha_failed_rgb_only
+};
+enum gs_alpha_dst_test { gs_alpha_dst_test_off, gs_alpha_dst_test_on };
+enum gs_alpha_dst_method { gs_alpha_dst_pass0, gs_alpha_dst_pass1 };
+enum gs_depth_test { gs_depth_test_off, gs_depth_test_on };
+enum gs_depth_method {
+	gs_depth_fail, gs_depth_pass, gs_depth_gequal, gs_depth_greater
+};
+
+/**
+ * struct gs_test_12 - pixel test control
+ * @ztst: depth test method
+ * @zte: depth test (must be 1)
+ * @datm: destination alpha test mode
+ * @date: depth test
+ * @afail: destination alpha test
+ * @aref: alpha reference comparison
+ * @atst: alpha test method
+ * @ate: alpha test
+ *
+ * The ZTE field must at all times be ON (OFF is not allowed). To emulate
+ * ZTE OFF, set ZTST to PASS.
+ */
+struct gs_test_12 {
+	__BITFIELD_FIELD(__u64 : 45,
+	__BITFIELD_FIELD(__u64 ztst : 2,
+	__BITFIELD_FIELD(__u64 zte : 1,
+	__BITFIELD_FIELD(__u64 datm : 1,
+	__BITFIELD_FIELD(__u64 date : 1,
+	__BITFIELD_FIELD(__u64 afail : 2,
+	__BITFIELD_FIELD(__u64 aref : 8,
+	__BITFIELD_FIELD(__u64 atst : 3,
+	__BITFIELD_FIELD(__u64 ate : 1,
+	;)))))))))
+};
+
+/**
+ * struct gs_rgbaq - vertex color
+ * @q: normalized texture coordinate
+ * @a: alpha vertex value (0x80 = 1.0)
+ * @b: blue luminance element of vertex
+ * @g: green luminance element of vertex
+ * @r: red luminance element of vertex
+ *
+ * The Q field is used both for calculating texture coordinates and deciding
+ * level of detail (LOD).
+ */
+struct gs_rgbaq {
+	__BITFIELD_FIELD(__u64 q : 32,
+	__BITFIELD_FIELD(__u64 a : 8,
+	__BITFIELD_FIELD(__u64 b : 8,
+	__BITFIELD_FIELD(__u64 g : 8,
+	__BITFIELD_FIELD(__u64 r : 8,
+	;)))))
+};
+
+/**
+ * struct gs_uv - vertex texture coordinates
+ * @v: texel coordinate v*16
+ * @u: texel coordinate u*16
+ */
+struct gs_uv {
+	__BITFIELD_FIELD(__u64 : 34,
+	__BITFIELD_FIELD(__u64 v : 14,
+	__BITFIELD_FIELD(__u64 : 2,
+	__BITFIELD_FIELD(__u64 u : 14,
+	;))))
+};
+
+/**
+ * struct gs_xyz23 - vertex coordinates without a drawing kick
+ * @z: vertext coordinate z
+ * @y: vertext coordinate y*16
+ * @x: vertext coordinate x*16
+ *
+ * Assigning XYZ2 moves the vertex queue one step forward. Drawing is not
+ * started with XYZ3 (no Drawing Kick).
+ *
+ * X and Y are specified as fixed-point (4-bit scaling factor) in the
+ * primitive coordinate system.
+ */
+struct gs_xyz23 {
+	__BITFIELD_FIELD(__u64 z : 32,
+	__BITFIELD_FIELD(__u64 y : 16,
+	__BITFIELD_FIELD(__u64 x : 16,
+	;)))
+};
+
+/**
+ * struct gs_xyoffset_12 - primitive to window coordinate offsets
+ * @ofy: offset y*16
+ * @ofx: offset x*16
+ *
+ * Coordinate offsets from the primitive coordinate system to the window
+ * coordinate system.
+ */
+struct gs_xyoffset_12 {
+	__BITFIELD_FIELD(__u64 : 16,
+	__BITFIELD_FIELD(__u64 ofy : 16,
+	__BITFIELD_FIELD(__u64 : 16,
+	__BITFIELD_FIELD(__u64 ofx : 16,
+	;))))
+};
+
+enum gs_tfx {
+	gs_tfx_modulate, gs_tfx_decal,
+	gs_tfx_highlight, gs_tfx_highlight2
+};
+
+enum gs_tcc { gs_tcc_rgb, gs_tcc_rgba };
+enum gs_csm { gs_csm1, gs_csm2 };
+
+/**
+ * struct gs_tex0 - texture setting
+ * @cld: CLUT buffer load control
+ * @csa: CLUT entry offset
+ * @csm: CLUT storage mode
+ * @cpsm: CLUT pixel storage format
+ * @cbp: CLUT buffer base pointer
+ * @tfx: texture function
+ * @tcc: texture color component
+ * @th: texture height (2^h)
+ * @tw: texture width (2^w)
+ * @psm: texture storage format
+ * @tbw: texture buffer width
+ * @tbp0: texture base pointer
+ */
+struct gs_tex0 {
+	__BITFIELD_FIELD(__u64 cld : 3,
+	__BITFIELD_FIELD(__u64 csa : 5,
+	__BITFIELD_FIELD(__u64 csm : 1,
+	__BITFIELD_FIELD(__u64 cpsm : 4,
+	__BITFIELD_FIELD(__u64 cbp : 14,
+	__BITFIELD_FIELD(__u64 tfx : 2,
+	__BITFIELD_FIELD(__u64 tcc : 1,
+	__BITFIELD_FIELD(__u64 th : 4,
+	__BITFIELD_FIELD(__u64 tw : 4,
+	__BITFIELD_FIELD(__u64 psm : 6,
+	__BITFIELD_FIELD(__u64 tbw : 6,
+	__BITFIELD_FIELD(__u64 tbp0 : 14,
+	;))))))))))))
+};
+
+enum gs_lcm { gs_lcm_formula, gs_lcm_fixed };
+
+enum gs_lod {
+	gs_lod_nearest,
+	gs_lod_linear,
+	gs_lod_nearest_mipmap_nearest,
+	gs_lod_nearest_mipmap_linear,
+	gs_lod_linear_mipmap_nearest,
+	gs_lod_linear_mipmap_linear
+};
+
+enum gs_aem { gs_aem_normal, gs_aem_transparent };
+
+/**
+ * struct gs_texa - texture alpha value setting
+ * @ta1: alpha when A=1 in RGBA16
+ * @aem: alpha expanding method
+ * @ta0: alpha when A=0 in RGBA16
+ */
+struct gs_texa {
+	__BITFIELD_FIELD(__u64 : 24,
+	__BITFIELD_FIELD(__u64 ta1 : 8,
+	__BITFIELD_FIELD(__u64 : 16,
+	__BITFIELD_FIELD(__u64 aem : 1,
+	__BITFIELD_FIELD(__u64 : 7,
+	__BITFIELD_FIELD(__u64 ta0 : 8,
+	;))))))
+};
+
+/**
+ * struct gs_tex1 - texture setting
+ * @k: LOD parameter K
+ * @l: LOD parameter L
+ * @mtba: MIPMAP base address specification of level 1 or more
+ * @mmin: reduced texture filter
+ * @mmag: expanded texture filter
+ * @mxl: maximum MIP level
+ * @lcm: LOD calculation method
+ */
+struct gs_tex1 {
+	__BITFIELD_FIELD(__u64 k : 11,
+	__BITFIELD_FIELD(__u64 : 11,
+	__BITFIELD_FIELD(__u64 l : 2,
+	__BITFIELD_FIELD(__u64 : 9,
+	__BITFIELD_FIELD(__u64 mtba : 1,
+	__BITFIELD_FIELD(__u64 mmin : 3,
+	__BITFIELD_FIELD(__u64 mmag : 1,
+	__BITFIELD_FIELD(__u64 mxl : 3,
+	__BITFIELD_FIELD(__u64 : 1,
+	__BITFIELD_FIELD(__u64 lcm : 1,
+	;))))))))))
+};
+
+/**
+ * struct gs_tex2 - texture setting
+ * @cld: CLUT buffer load control
+ * @csa: CLUT entry offset
+ * @csm: CLUT storage mode
+ * @cpsm: CLUT pixel storage format
+ * @cbp: CLUT buffer base pointer
+ * @psm: Texture storage format
+ */
+struct gs_tex2 {
+	__BITFIELD_FIELD(__u64 cld : 3,
+	__BITFIELD_FIELD(__u64 csa : 5,
+	__BITFIELD_FIELD(__u64 csm : 1,
+	__BITFIELD_FIELD(__u64 cpsm : 4,
+	__BITFIELD_FIELD(__u64 cbp : 14,
+	__BITFIELD_FIELD(__u64 : 11,
+	__BITFIELD_FIELD(__u64 psm : 6,
+	__BITFIELD_FIELD(__u64 : 20,
+	;))))))))
+};
+
+enum gs_zmsk { gs_zbuf_on, gs_zbuf_off };
+
+/**
+ * struct gs_zbuf - z buffer setting
+ * @zmsk: z value drawing mask
+ * @psm: z value storage format (PSMZ32, PSMZ24, PSMZ16 or PSMZ16S)
+ * @zbp: z buffer base pointer/2048
+ */
+struct gs_zbuf {
+	__BITFIELD_FIELD(__u64 : 31,
+	__BITFIELD_FIELD(__u64 zmsk : 1,
+	__BITFIELD_FIELD(__u64 : 4,
+	__BITFIELD_FIELD(__u64 psm : 4,
+	__BITFIELD_FIELD(__u64 : 15,
+	__BITFIELD_FIELD(__u64 zbp : 9,
+	;))))))
+};
+
+enum gs_dthe_mode { gs_dthe_off, gs_dthe_on };
+
+/**
+ * struct gs_dthe - dither control
+ * @dthe: dithering off=0 or on=1
+ *
+ * If the pixel storage mode of the frame buffer is PSMCT32 or PSMCT24,
+ * dithering should be turned off.
+ */
+struct gs_dthe {
+	__BITFIELD_FIELD(__u64 : 63,
+	__BITFIELD_FIELD(__u64 dthe : 1,
+	;))
+};
+
+#endif /* _UAPI_MIPS_ASM_GS_H */
-- 
2.21.0


  parent reply index

Thread overview: 152+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-01 15:35 [PATCH 000/120] Linux for the PlayStation 2 Fredrik Noring
2019-09-01 15:35 ` [PATCH 001/120] MIPS: R5900: Initial support for the Emotion Engine in " Fredrik Noring
2019-09-01 21:14   ` Maciej W. Rozycki
2019-09-02 15:09     ` Fredrik Noring
2019-09-01 15:36 ` [PATCH 002/120] MIPS: R5900: Trap the RDHWR instruction as an SQ address exception Fredrik Noring
2019-09-01 22:00   ` Maciej W. Rozycki
2019-09-01 15:36 ` [PATCH 003/120] MIPS: R5900: Sign-extend o32 system call registers Fredrik Noring
2019-09-01 15:37 ` [PATCH 004/120] MIPS: R5900: Reset bits 127..64 of GPRs in RESTORE_SOME Fredrik Noring
2019-09-01 15:38 ` [PATCH 005/120] MIPS: R5900: Reset the funnel shift amount (SA) register " Fredrik Noring
2019-09-01 15:38 ` [PATCH 006/120] MIPS: R5900: Workaround for the short loop bug Fredrik Noring
2019-09-01 15:39 ` [PATCH 007/120] MIPS: R5900: Add the SYNC.P instruction Fredrik Noring
2019-09-01 15:39 ` [PATCH 008/120] MIPS: R5900: Add implicit SYNC.P to the UASM_i_M[FT]C0 macros Fredrik Noring
2019-09-01 15:39 ` [PATCH 009/120] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring
2019-09-01 15:39 ` [PATCH 010/120] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring
2019-09-01 23:01   ` Philippe Mathieu-Daudé
2019-09-01 15:40 ` [PATCH 011/120] MIPS: R5900: Avoid pipeline hazard with the TLBP instruction Fredrik Noring
2019-09-01 17:15   ` Sergei Shtylyov
2019-09-01 17:36     ` Fredrik Noring
2019-09-01 15:40 ` [PATCH 012/120] MIPS: R5900: Avoid pipeline hazards with the TLBW[IR] instructions Fredrik Noring
2019-09-01 15:40 ` [PATCH 013/120] MIPS: R5900: Avoid pipeline hazard with the TLBR instruction Fredrik Noring
2019-09-01 15:41 ` [PATCH 014/120] MIPS: R5900: Install final length of TLB refill handler rather than 256 bytes Fredrik Noring
2019-09-01 15:41 ` [PATCH 015/120] MIPS: R5900: Verify that the TLB refill handler does not overflow Fredrik Noring
2019-09-01 15:41 ` [PATCH 016/120] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring
2019-09-01 15:42 ` [PATCH 017/120] MIPS: R5900: Define CACHE instruction operation field encodings Fredrik Noring
2019-09-01 15:42 ` [PATCH 018/120] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring
2019-09-01 15:42 ` [PATCH 019/120] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for " Fredrik Noring
2019-09-01 15:43 ` [PATCH 020/120] MIPS: R5900: Define CP0.Config register fields Fredrik Noring
2019-09-01 23:04   ` Philippe Mathieu-Daudé
2019-09-01 15:43 ` [PATCH 021/120] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring
2019-09-01 15:46 ` [PATCH 022/120] MIPS: R5900: Support 64-bit inq() and outq() macros in 32-bit kernels Fredrik Noring
2019-09-04  1:04   ` Jiaxun Yang
2019-09-04 16:00     ` Maciej W. Rozycki
2019-09-01 15:46 ` [PATCH 023/120] MIPS: R5900: Add MFSA and MTSA instructions for the special SA register Fredrik Noring
2019-09-01 15:46 ` [PATCH 024/120] MIPS: PS2: Define PlayStation 2 I/O port, ROM and RAM address spaces Fredrik Noring
2019-09-01 15:47 ` [PATCH 025/120] MIPS: PS2: Define interrupt controller, DMA and timer IRQs Fredrik Noring
2019-09-01 15:47 ` [PATCH 026/120] MIPS: PS2: Interrupt controller (INTC) IRQ support Fredrik Noring
2019-09-01 15:47 ` [PATCH 027/120] MIPS: PS2: DMAC: Define DMA controller registers Fredrik Noring
2019-09-01 15:47 ` [PATCH 028/120] MIPS: PS2: DMAC: Define tag structures Fredrik Noring
2019-09-01 15:48 ` [PATCH 029/120] MIPS: PS2: DMAC: IRQ support Fredrik Noring
2019-09-01 15:48 ` [PATCH 030/120] MIPS: PS2: Timer support Fredrik Noring
2019-09-01 15:48 ` [PATCH 031/120] MIPS: PS2: SCMD: System command support Fredrik Noring
2019-09-01 15:48 ` [PATCH 032/120] MIPS: PS2: SCMD: System power off command Fredrik Noring
2019-09-01 15:48 ` [PATCH 033/120] MIPS: PS2: SCMD: Read system machine name command Fredrik Noring
2019-09-01 15:49 ` [PATCH 034/120] MIPS: PS2: SCMD: Read system command for the real-time clock (RTC) Fredrik Noring
2019-09-01 15:49 ` [PATCH 035/120] MIPS: PS2: SCMD: Set " Fredrik Noring
2019-09-01 15:49 ` [PATCH 036/120] MIPS: PS2: ROM: Iterate over the files in a given ROM directory Fredrik Noring
2019-09-01 15:49 ` [PATCH 037/120] MIPS: PS2: ROM: Find ROM files with a given name, if they exist Fredrik Noring
2019-09-01 15:50 ` [PATCH 038/120] MIPS: PS2: ROM: Read data for a given ROM file name Fredrik Noring
2019-09-02  9:05   ` Sergei Shtylyov
2019-09-04 11:46     ` Sergei Shtylyov
2019-09-06 13:07       ` Fredrik Noring
2019-09-01 15:50 ` [PATCH 039/120] MIPS: PS2: ROM: Read extended information for a given ROM file Fredrik Noring
2019-09-01 15:50 ` [PATCH 040/120] MIPS: PS2: ROM: Read and decode the ROMVER file Fredrik Noring
2019-09-01 15:52 ` [PATCH 041/120] MIPS: PS2: ROM: Resolve the name for the type in " Fredrik Noring
2019-09-01 15:52 ` [PATCH 042/120] MIPS: PS2: ROM: Resolve the name for the region " Fredrik Noring
2019-09-01 15:53 ` [PATCH 043/120] MIPS: PS2: ROM: Permit /dev/mem to access read-only memory Fredrik Noring
2019-09-01 15:53 ` [PATCH 044/120] MIPS: PS2: ROM: Sysfs module to inspect ROM files Fredrik Noring
2019-09-01 15:54 ` [PATCH 045/120] MIPS: PS2: ROM: Provide extended file information via sysfs Fredrik Noring
2019-09-01 15:54 ` [PATCH 046/120] MIPS: PS2: Identify the machine by model name Fredrik Noring
2019-09-01 15:54 ` [PATCH 047/120] MIPS: PS2: Let the system type be Sony PlayStation 2 Fredrik Noring
2019-09-01 23:09   ` Philippe Mathieu-Daudé
2019-09-01 15:55 ` [PATCH 048/120] MIPS: Define and use cpu_relax_forever() for various halting loops Fredrik Noring
2019-09-01 15:55 ` [PATCH 049/120] MIPS: PS2: Power off support Fredrik Noring
2019-09-01 15:55 ` [PATCH 050/120] MIPS: PS2: Real-time clock (RTC) driver Fredrik Noring
2019-09-01 15:56 ` [PATCH 051/120] MIPS: PS2: IOP: I/O processor DMA register PCR2 set and clear Fredrik Noring
2019-09-01 15:57 ` [PATCH 052/120] MIPS: PS2: SIF: Sub-system interface reset of the I/O processor (IOP) Fredrik Noring
2019-09-01 15:57 ` [PATCH 053/120] MIPS: PS2: IOP: Define error numbers, descriptions and errno mapping Fredrik Noring
2019-09-01 15:58 ` [PATCH 054/120] MIPS: PS2: SIF: SIF register write command support Fredrik Noring
2019-09-01 15:58 ` [PATCH 055/120] MIPS: PS2: SIF: Respond to remote procedure call (RPC) bind command Fredrik Noring
2019-09-01 15:58 ` [PATCH 056/120] MIPS: PS2: SIF: Respond to RPC bind end command Fredrik Noring
2019-09-01 15:59 ` [PATCH 057/120] MIPS: PS2: SIF: Reset the SIF0 (sub-to-main) DMA controller Fredrik Noring
2019-09-01 15:59 ` [PATCH 058/120] MIPS: PS2: SIF: Handle SIF0 (sub-to-main) RPCs via interrupts Fredrik Noring
2019-09-01 15:59 ` [PATCH 059/120] MIPS: PS2: SIF: Enable the IOP to issue SIF commands Fredrik Noring
2019-09-01 16:00 ` [PATCH 060/120] MIPS: PS2: SIF: Enable the IOP to issue SIF RPCs Fredrik Noring
2019-09-01 16:01 ` [PATCH 061/120] MIPS: PS2: SIF: sif_rpc_bind() to request an RPC server connection Fredrik Noring
2019-09-01 16:02 ` [PATCH 062/120] MIPS: PS2: SIF: sif_rpc_unbind() to release " Fredrik Noring
2019-09-01 16:02 ` [PATCH 063/120] MIPS: PS2: SIF: sif_rpc() to issue a remote procedure call Fredrik Noring
2019-09-01 16:03 ` [PATCH 064/120] MIPS: PS2: IOP: Permit /dev/mem to access IOP memory Fredrik Noring
2019-09-01 16:03 ` [PATCH 065/120] MIPS: PS2: IOP: I/O processor memory support Fredrik Noring
2019-09-01 16:10 ` [PATCH 066/120] FIXME: Export _dma_cache_{wback,wback_inv,inv} Fredrik Noring
2019-09-01 16:10 ` [PATCH 067/120] MIPS: PS2: IOP: Module linking support Fredrik Noring
2019-09-01 16:11 ` [PATCH 068/120] MIPS: PS2: IOP: Verify that modules are IRX objects Fredrik Noring
2019-09-01 16:11 ` [PATCH 069/120] MIPS: PS2: IOP: Module version compatibility verification Fredrik Noring
2019-09-01 16:11 ` [PATCH 070/120] MIPS: PS2: IOP: Avoid linking already linked library modules Fredrik Noring
2019-09-01 16:12 ` [PATCH 071/120] MIPS: PS2: IOP: Resolve module dependencies Fredrik Noring
2019-09-01 16:12 ` [PATCH 072/120] MIPS: PS2: IOP: SIF printk command support Fredrik Noring
2019-09-01 17:44   ` Sergei Shtylyov
2019-09-01 18:08     ` Fredrik Noring
2019-09-01 16:16 ` [PATCH 073/120] MIPS: PS2: IOP: Heap memory allocate and free Fredrik Noring
2019-09-01 16:16 ` [PATCH 074/120] MIPS: PS2: SIF: Request RPC IRQ command Fredrik Noring
2019-09-01 16:17 ` [PATCH 075/120] MIPS: PS2: IOP: IRQ support Fredrik Noring
2019-09-01 16:17 ` [PATCH 076/120] MIPS: PS2: GS: Define privileged Graphics Synthesizer registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 077/120] MIPS: PS2: GS: Write privileged registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 078/120] MIPS: PS2: GS: Read " Fredrik Noring
2019-09-01 16:18 ` [PATCH 079/120] MIPS: PS2: GS: Define privileged register structures Fredrik Noring
2019-09-01 16:19 ` [PATCH 080/120] MIPS: PS2: GS: Define gs_xorq_imr() Fredrik Noring
2019-09-01 16:20 ` [PATCH 081/120] MIPS: PS2: GS: Privileged register write macros with named fields Fredrik Noring
2019-09-01 16:20 ` [PATCH 082/120] MIPS: PS2: GS: IRQ support Fredrik Noring
2019-09-01 16:21 ` Fredrik Noring [this message]
2019-09-01 16:21 ` [PATCH 084/120] MIPS: PS2: GIF: Define Graphics Synthesizer interface structures Fredrik Noring
2019-09-01 16:22 ` [PATCH 085/120] MIPS: PS2: GIF: Graphics Synthesizer interface support Fredrik Noring
2019-09-01 16:22 ` [PATCH 086/120] MIPS: PS2: GS: Graphics Synthesizer device init and video clock Fredrik Noring
2019-09-01 16:23 ` [PATCH 087/120] MIPS: PS2: GS: Compute block count and indices Fredrik Noring
2019-09-01 16:23 ` [PATCH 088/120] MIPS: PS2: GS: Primitive and texel coordinate transformations Fredrik Noring
2019-09-01 16:23 ` [PATCH 089/120] MIPS: PS2: GS: Approximate video region with ROM region Fredrik Noring
2019-09-01 16:24 ` [PATCH 090/120] macro: Extend COUNT_ARGS() from 12 to 32 arguments Fredrik Noring
2019-09-01 16:25 ` [PATCH 091/120] MIPS: PS2: GS: Show privileged registers with sysfs Fredrik Noring
2019-09-01 16:25 ` [PATCH 092/120] MIPS: PS2: GS: Store " Fredrik Noring
2019-09-01 16:25 ` [PATCH 093/120] fbdev: Add fb_warn_once() variant that only prints a warning once Fredrik Noring
2019-09-01 23:12   ` Philippe Mathieu-Daudé
2019-09-01 16:26 ` [PATCH 094/120] MIPS: PS2: FB: Frame buffer driver for the PlayStation 2 Fredrik Noring
2019-09-02  1:12   ` Jiaxun Yang
2019-09-02 14:40     ` Fredrik Noring
2019-09-02 17:47       ` Aaro Koskinen
2019-09-03 14:32         ` Fredrik Noring
2019-09-03  4:01       ` Jiaxun Yang
2019-09-03 17:42         ` Fredrik Noring
2019-09-03 17:59           ` Maciej W. Rozycki
2019-09-03 18:46             ` Fredrik Noring
2019-09-01 16:30 ` [PATCH 095/120] MIPS: PS2: FB: fb_set_par() standard-definition television support Fredrik Noring
2019-09-01 16:30 ` [PATCH 096/120] MIPS: PS2: FB: fb_set_par() high-definition " Fredrik Noring
2019-09-01 16:31 ` [PATCH 097/120] MIPS: PS2: FB: fb_set_par() VESA computer display mode support Fredrik Noring
2019-09-01 16:31 ` [PATCH 098/120] MIPS: PS2: FB: Preconfigure standard PAL, NTSC and VESA display modes Fredrik Noring
2019-09-01 16:31 ` [PATCH 099/120] MIPS: PS2: FB: Reset the Graphics Synthesizer drawing environment Fredrik Noring
2019-09-01 16:32 ` [PATCH 100/120] MIPS: PS2: FB: Clear the display buffer when changing video modes Fredrik Noring
2019-09-01 16:32 ` [PATCH 101/120] MIPS: PS2: FB: fb_setcolreg() 256 colour pseudo palette support Fredrik Noring
2019-09-01 16:32 ` [PATCH 102/120] MIPS: PS2: FB: fb_settile() with font stored as palette indexed textures Fredrik Noring
2019-09-01 16:32 ` [PATCH 103/120] MIPS: PS2: FB: Hardware accelerated fb_tilecopy() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 104/120] MIPS: PS2: FB: Hardware accelerated fb_tilefill() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 105/120] MIPS: PS2: FB: Simplified fb_tileblit() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 106/120] MIPS: PS2: FB: fb_tilecursor() placeholder Fredrik Noring
2019-09-01 16:33 ` [PATCH 107/120] MIPS: PS2: FB: Hardware accelerated fb_pan_display() support Fredrik Noring
2019-09-01 16:34 ` [PATCH 108/120] MIPS: PS2: FB: fb_blank() display power management signaling (DPMS) Fredrik Noring
2019-09-01 16:34 ` [PATCH 109/120] MIPS: PS2: FB: Disable GIF DMA completion interrupts Fredrik Noring
2019-09-01 16:34 ` [PATCH 110/120] MIPS: PS2: FB: PAL and NTSC grayscale support Fredrik Noring
2019-09-01 16:34 ` [PATCH 111/120] MIPS: PS2: FB: Analogue display mode adjustment module parameter Fredrik Noring
2019-09-01 16:35 ` [PATCH 112/120] USB: OHCI: Support for the PlayStation 2 Fredrik Noring
2019-09-01 16:35 ` [PATCH 113/120] USB: OHCI: OHCI_INTR_MIE workaround for freeze on " Fredrik Noring
2019-09-01 16:35 ` [PATCH 114/120] MIPS: PS2: Workaround for unexpected uLaunchELF CP0 Status user mode Fredrik Noring
2019-09-01 16:35 ` [PATCH 115/120] MIPS: PS2: Define initial PlayStation 2 devices Fredrik Noring
2019-09-01 16:35 ` [PATCH 116/120] MIPS: PS2: Define workarounds related to the PlayStation 2 Fredrik Noring
2019-09-01 16:36 ` [PATCH 117/120] MIPS: PS2: Define R5900 feature overrides Fredrik Noring
2019-09-01 16:36 ` [PATCH 118/120] MIPS: PS2: Define the PlayStation 2 platform Fredrik Noring
2019-09-01 16:36 ` [PATCH 119/120] MIPS: PS2: Initial support for the Sony PlayStation 2 Fredrik Noring
2019-09-01 16:37 ` [PATCH 120/120] MIPS: Fix name of BOOT_MEM_ROM_DATA Fredrik Noring
2019-09-01 23:15   ` Philippe Mathieu-Daudé
2019-09-02  1:02   ` Jiaxun Yang
2019-09-02 15:26     ` Fredrik Noring
2019-09-03  3:50       ` Jiaxun Yang
2019-09-03 16:06         ` Fredrik Noring
2019-09-04 14:19 ` [PATCH 000/120] Linux for the PlayStation 2 Paul Burton
2019-09-05 18:32   ` Fredrik Noring

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