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From: Fredrik Noring <noring@nocrew.org>
To: Paul Burton <paul.burton@mips.com>, linux-mips@vger.kernel.org
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>,
	"Jürgen Urban" <JuergenUrban@gmx.de>
Subject: [PATCH 019/120] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for instruction cache
Date: Sun, 1 Sep 2019 17:42:52 +0200
Message-ID: <4908071c89e101af477fefb28cdd1ba69ffb63d1.1567326213.git.noring@nocrew.org> (raw)
In-Reply-To: <cover.1567326213.git.noring@nocrew.org>

Toshiba TX79 manual programming notes[1]:

    For all CACHE sub-operations which operate on the instruction cache
    the following programming restrictions have to be followed:

    1. A sequence of CACHE instructions has to be directly preceded and
       followed by a SYNC.P instruction.
    2. Each individual FILL sub-operation has to be followed by a SYNC.L
       instruction.

    For all CACHE sub-operations which operate on the data cache the
    following programming restrictions have to be followed:

    1. A sequence of CACHE instructions have to be directly preceded and
       followed by a SYNC.L instruction.
    2. Each of the three WRITEBACK sub-operations have to be
       individually followed by a SYNC.L instruction.

    For all CACHE sub-operations which operate on the BTAC the following
    programming restrictions have to be followed:

    1. A sequence of CACHE instructions have to be directly preceded and
       followed by a SYNC.P instruction.

References:

[1] "TX System RISC TX79 Core Architecture" manual, revision 2.0,
    Toshiba Corporation, p. C-13, https://wiki.qemu.org/File:C790.pdf

Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
This is perhaps the most complex change for the R5900. The code comes from
the Linux 2.6 port to the PlayStation 2.
---
 arch/mips/include/asm/r4kcache.h | 239 ++++++++++++++++++++++++-------
 arch/mips/mm/c-r4k.c             |   8 +-
 2 files changed, 189 insertions(+), 58 deletions(-)

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index e00087db9d74..da9f55f36fcf 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -44,7 +44,7 @@ extern void (*r4k_blast_icache)(void);
 #define INDEX_BASE	CKSEG0
 #endif
 
-#define cache_op(op,addr)						\
+#define cache_op_s(op,addr)						\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
 	"	.set	noreorder				\n"	\
@@ -53,56 +53,85 @@ extern void (*r4k_blast_icache)(void);
 	"	.set	pop					\n"	\
 	:								\
 	: "i" (op), "R" (*(unsigned char *)(addr)))
+#ifdef CONFIG_CPU_R5900
+#define cache_op_d(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noreorder				\n"	\
+	"	.set	mips3\n\t				\n"	\
+	"	sync.l						\n"	\
+	"	cache	%0, %1					\n"	\
+	"	sync.l						\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
+#define cache_op_i(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noreorder				\n"	\
+	"	.set	mips3\n\t				\n"	\
+	"	sync.p						\n"	\
+	"	cache	%0, %1					\n"	\
+	"	sync.p						\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
+#else
+#define cache_op_d cache_op_s
+#define cache_op_i cache_op_s
+#define cache_op cache_op_s
+#endif
+#define cache_op_t cache_op_s
 
 static inline void flush_icache_line_indexed(unsigned long addr)
 {
-	cache_op(Index_Invalidate_I, addr);
+	cache_op_i(Index_Invalidate_I, addr);
 }
 
 static inline void flush_dcache_line_indexed(unsigned long addr)
 {
-	cache_op(Index_Writeback_Inv_D, addr);
+	cache_op_d(Index_Writeback_Inv_D, addr);
 }
 
 static inline void flush_scache_line_indexed(unsigned long addr)
 {
-	cache_op(Index_Writeback_Inv_SD, addr);
+	cache_op_s(Index_Writeback_Inv_SD, addr);
 }
 
 static inline void flush_icache_line(unsigned long addr)
 {
 	switch (boot_cpu_type()) {
 	case CPU_LOONGSON2:
-		cache_op(Hit_Invalidate_I_Loongson2, addr);
+		cache_op_i(Hit_Invalidate_I_Loongson2, addr);
 		break;
 
 	default:
-		cache_op(Hit_Invalidate_I, addr);
+		cache_op_i(Hit_Invalidate_I, addr);
 		break;
 	}
 }
 
 static inline void flush_dcache_line(unsigned long addr)
 {
-	cache_op(Hit_Writeback_Inv_D, addr);
+	cache_op_d(Hit_Writeback_Inv_D, addr);
 }
 
 static inline void invalidate_dcache_line(unsigned long addr)
 {
-	cache_op(Hit_Invalidate_D, addr);
+	cache_op_d(Hit_Invalidate_D, addr);
 }
 
 static inline void invalidate_scache_line(unsigned long addr)
 {
-	cache_op(Hit_Invalidate_SD, addr);
+	cache_op_s(Hit_Invalidate_SD, addr);
 }
 
 static inline void flush_scache_line(unsigned long addr)
 {
-	cache_op(Hit_Writeback_Inv_SD, addr);
+	cache_op_s(Hit_Writeback_Inv_SD, addr);
 }
 
-#define protected_cache_op(op,addr)				\
+#define protected_cache_op_s(op,addr)				\
 ({								\
 	int __err = 0;						\
 	__asm__ __volatile__(					\
@@ -124,6 +153,49 @@ static inline void flush_scache_line(unsigned long addr)
 	__err;							\
 })
 
+#ifdef CONFIG_CPU_R5900
+#define protected_cache_op_d(op,addr)				\
+({								\
+	int __err = 0;						\
+	__asm__ __volatile__(					\
+	"	.set	push			\n"		\
+	"	.set	noreorder		\n"		\
+	"	.set	mips3			\n"		\
+	"	sync.l				\n"		\
+	"1:	cache	%0, (%1)		\n"		\
+	"	sync.l				\n"		\
+	"2:	.set	pop			\n"		\
+	"	.section __ex_table,\"a\"	\n"		\
+	"	"STR(PTR)" 1b, 2b		\n"		\
+	"	.previous"					\
+	:							\
+	: "i" (op), "r" (addr));				\
+	__err;							\
+})
+
+#define protected_cache_op_i(op,addr)				\
+({								\
+	int __err = 0;						\
+	__asm__ __volatile__(					\
+	"	.set	push			\n"		\
+	"	.set	noreorder		\n"		\
+	"	.set	mips3			\n"		\
+	"	sync.p				\n"		\
+	"1:	cache	%0, (%1)		\n"		\
+	"	sync.p				\n"		\
+	"2:	.set	pop			\n"		\
+	"	.section __ex_table,\"a\"	\n"		\
+	"	"STR(PTR)" 1b, 2b		\n"		\
+	"	.previous"					\
+	:							\
+	: "i" (op), "r" (addr));				\
+	__err;							\
+})
+#else
+#define protected_cache_op_i protected_cache_op_s
+#define protected_cache_op_d protected_cache_op_s
+#define protected_cache_op protected_cache_op_s
+#endif
 
 #define protected_cachee_op(op,addr)				\
 ({								\
@@ -155,13 +227,13 @@ static inline int protected_flush_icache_line(unsigned long addr)
 {
 	switch (boot_cpu_type()) {
 	case CPU_LOONGSON2:
-		return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
+		return protected_cache_op_i(Hit_Invalidate_I_Loongson2, addr);
 
 	default:
 #ifdef CONFIG_EVA
-		return protected_cachee_op(Hit_Invalidate_I, addr);
+		return protected_cachee_op_i(Hit_Invalidate_I, addr);
 #else
-		return protected_cache_op(Hit_Invalidate_I, addr);
+		return protected_cache_op_i(Hit_Invalidate_I, addr);
 #endif
 	}
 }
@@ -175,18 +247,18 @@ static inline int protected_flush_icache_line(unsigned long addr)
 static inline int protected_writeback_dcache_line(unsigned long addr)
 {
 #ifdef CONFIG_EVA
-	return protected_cachee_op(Hit_Writeback_Inv_D, addr);
+	return protected_cachee_op_d(Hit_Writeback_Inv_D, addr);
 #else
-	return protected_cache_op(Hit_Writeback_Inv_D, addr);
+	return protected_cache_op_d(Hit_Writeback_Inv_D, addr);
 #endif
 }
 
 static inline int protected_writeback_scache_line(unsigned long addr)
 {
 #ifdef CONFIG_EVA
-	return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
+	return protected_cachee_op_s(Hit_Writeback_Inv_SD, addr);
 #else
-	return protected_cache_op(Hit_Writeback_Inv_SD, addr);
+	return protected_cache_op_s(Hit_Writeback_Inv_SD, addr);
 #endif
 }
 
@@ -195,7 +267,7 @@ static inline int protected_writeback_scache_line(unsigned long addr)
  */
 static inline void invalidate_tcache_page(unsigned long addr)
 {
-	cache_op(Page_Invalidate_T, addr);
+	cache_op_t(Page_Invalidate_T, addr);
 }
 
 #ifndef CONFIG_CPU_MIPSR6
@@ -276,6 +348,65 @@ static inline void invalidate_tcache_page(unsigned long addr)
 		:							\
 		: "r" (base),						\
 		  "i" (op));
+#ifdef CONFIG_CPU_R5900
+#define cache64_unroll32_d(base,op)					\
+	__asm__ __volatile__(						\
+	"	.set push					\n"	\
+	"	.set noreorder					\n"	\
+	"	.set mips3					\n"	\
+	"	sync.l						\n"	\
+	"	cache %1, 0x000(%0); sync.l; cache %1, 0x040(%0); sync.l	\n"	\
+	"	cache %1, 0x080(%0); sync.l; cache %1, 0x0c0(%0); sync.l	\n"	\
+	"	cache %1, 0x100(%0); sync.l; cache %1, 0x140(%0); sync.l	\n"	\
+	"	cache %1, 0x180(%0); sync.l; cache %1, 0x1c0(%0); sync.l	\n"	\
+	"	cache %1, 0x200(%0); sync.l; cache %1, 0x240(%0); sync.l	\n"	\
+	"	cache %1, 0x280(%0); sync.l; cache %1, 0x2c0(%0); sync.l	\n"	\
+	"	cache %1, 0x300(%0); sync.l; cache %1, 0x340(%0); sync.l	\n"	\
+	"	cache %1, 0x380(%0); sync.l; cache %1, 0x3c0(%0); sync.l	\n"	\
+	"	cache %1, 0x400(%0); sync.l; cache %1, 0x440(%0); sync.l	\n"	\
+	"	cache %1, 0x480(%0); sync.l; cache %1, 0x4c0(%0); sync.l	\n"	\
+	"	cache %1, 0x500(%0); sync.l; cache %1, 0x540(%0); sync.l	\n"	\
+	"	cache %1, 0x580(%0); sync.l; cache %1, 0x5c0(%0); sync.l	\n"	\
+	"	cache %1, 0x600(%0); sync.l; cache %1, 0x640(%0); sync.l	\n"	\
+	"	cache %1, 0x680(%0); sync.l; cache %1, 0x6c0(%0); sync.l	\n"	\
+	"	cache %1, 0x700(%0); sync.l; cache %1, 0x740(%0); sync.l	\n"	\
+	"	cache %1, 0x780(%0); sync.l; cache %1, 0x7c0(%0); sync.l	\n"	\
+	"	.set pop					\n"	\
+		:							\
+		: "r" (base),						\
+		  "i" (op));
+
+#define cache64_unroll32_i(base,op)					\
+	__asm__ __volatile__(						\
+	"	.set push					\n"	\
+	"	.set noreorder					\n"	\
+	"	.set mips3					\n"	\
+	"	sync.p						\n"	\
+	"	cache %1, 0x000(%0); cache %1, 0x040(%0)	\n"	\
+	"	cache %1, 0x080(%0); cache %1, 0x0c0(%0)	\n"	\
+	"	cache %1, 0x100(%0); cache %1, 0x140(%0)	\n"	\
+	"	cache %1, 0x180(%0); cache %1, 0x1c0(%0)	\n"	\
+	"	cache %1, 0x200(%0); cache %1, 0x240(%0)	\n"	\
+	"	cache %1, 0x280(%0); cache %1, 0x2c0(%0)	\n"	\
+	"	cache %1, 0x300(%0); cache %1, 0x340(%0)	\n"	\
+	"	cache %1, 0x380(%0); cache %1, 0x3c0(%0)	\n"	\
+	"	cache %1, 0x400(%0); cache %1, 0x440(%0)	\n"	\
+	"	cache %1, 0x480(%0); cache %1, 0x4c0(%0)	\n"	\
+	"	cache %1, 0x500(%0); cache %1, 0x540(%0)	\n"	\
+	"	cache %1, 0x580(%0); cache %1, 0x5c0(%0)	\n"	\
+	"	cache %1, 0x600(%0); cache %1, 0x640(%0)	\n"	\
+	"	cache %1, 0x680(%0); cache %1, 0x6c0(%0)	\n"	\
+	"	cache %1, 0x700(%0); cache %1, 0x740(%0)	\n"	\
+	"	cache %1, 0x780(%0); cache %1, 0x7c0(%0)	\n"	\
+	"	sync.p						\n"	\
+	"	.set pop					\n"	\
+		:							\
+		: "r" (base),						\
+		  "i" (op));
+#else
+#define cache64_unroll32_i cache64_unroll32
+#define cache64_unroll32_d cache64_unroll32
+#endif
 
 #define cache128_unroll32(base,op)					\
 	__asm__ __volatile__(						\
@@ -532,7 +663,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
 		  "i" (op));
 
 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
+#define __BUILD_BLAST_CACHE(fn_pfx, pfx, desc, indexop, hitop, lsize, extra)	\
 static inline void extra##blast_##pfx##cache##lsize(void)		\
 {									\
 	unsigned long start = INDEX_BASE;				\
@@ -544,7 +675,7 @@ static inline void extra##blast_##pfx##cache##lsize(void)		\
 									\
 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
 		for (addr = start; addr < end; addr += lsize * 32)	\
-			cache##lsize##_unroll32(addr|ws, indexop);	\
+			cache##lsize##_unroll32##fn_pfx(addr|ws, indexop);	\
 }									\
 									\
 static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
@@ -553,7 +684,7 @@ static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
 	unsigned long end = page + PAGE_SIZE;				\
 									\
 	do {								\
-		cache##lsize##_unroll32(start, hitop);			\
+		cache##lsize##_unroll32##fn_pfx(start, hitop);			\
 		start += lsize * 32;					\
 	} while (start < end);						\
 }									\
@@ -570,29 +701,29 @@ static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long
 									\
 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
 		for (addr = start; addr < end; addr += lsize * 32)	\
-			cache##lsize##_unroll32(addr|ws, indexop);	\
+			cache##lsize##_unroll32##fn_pfx(addr|ws, indexop);	\
 }
 
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+__BUILD_BLAST_CACHE(, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+__BUILD_BLAST_CACHE(, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+__BUILD_BLAST_CACHE(_d, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+__BUILD_BLAST_CACHE(_i, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(, d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+__BUILD_BLAST_CACHE(, i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
+__BUILD_BLAST_CACHE(, s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+
+__BUILD_BLAST_CACHE(, inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+__BUILD_BLAST_CACHE(, inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+__BUILD_BLAST_CACHE(, inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
 
 #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
@@ -617,7 +748,7 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 
 /* build blast_xxx_range, protected_blast_xxx_range */
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
+#define __BUILD_BLAST_CACHE_RANGE(fn_pfx, pfx, desc, hitop, prot, extra)	\
 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
 						    unsigned long end)	\
 {									\
@@ -626,7 +757,7 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
 	unsigned long aend = (end - 1) & ~(lsize - 1);			\
 									\
 	while (1) {							\
-		prot##cache_op(hitop, addr);				\
+		prot##cache_op##fn_pfx(hitop, addr);			\
 		if (addr == aend)					\
 			break;						\
 		addr += lsize;						\
@@ -635,8 +766,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
 
 #ifndef CONFIG_EVA
 
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+__BUILD_BLAST_CACHE_RANGE(_d, d, dcache, Hit_Writeback_Inv_D, protected_, )
+__BUILD_BLAST_CACHE_RANGE(_i, i, icache, Hit_Invalidate_I, protected_, )
 
 #else
 
@@ -670,15 +801,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
 __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
 
 #endif
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+__BUILD_BLAST_CACHE_RANGE(_s, s, scache, Hit_Writeback_Inv_SD, protected_, )
+__BUILD_BLAST_CACHE_RANGE(_i, i, icache, Hit_Invalidate_I_Loongson2, \
 	protected_, loongson2_)
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
+__BUILD_BLAST_CACHE_RANGE(_d, d, dcache, Hit_Writeback_Inv_D, , )
+__BUILD_BLAST_CACHE_RANGE(_i, i, icache, Hit_Invalidate_I, , )
+__BUILD_BLAST_CACHE_RANGE(_s, s, scache, Hit_Writeback_Inv_SD, , )
 /* blast_inv_dcache_range */
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
+__BUILD_BLAST_CACHE_RANGE(_d, inv_d, dcache, Hit_Invalidate_D, , )
+__BUILD_BLAST_CACHE_RANGE(_d, inv_s, scache, Hit_Invalidate_SD, , )
 
 /* Currently, this is very specific to Loongson-3 */
 #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)	\
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 4f2cecbec722..ae79a78f3002 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1557,14 +1557,14 @@ static int probe_scache(void)
 	write_c0_taglo(0);
 	write_c0_taghi(0);
 	__asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
-	cache_op(Index_Store_Tag_I, begin);
-	cache_op(Index_Store_Tag_D, begin);
-	cache_op(Index_Store_Tag_SD, begin);
+	cache_op_i(Index_Store_Tag_I, begin);
+	cache_op_d(Index_Store_Tag_D, begin);
+	cache_op_s(Index_Store_Tag_SD, begin);
 
 	/* Now search for the wrap around point. */
 	pow2 = (128 * 1024);
 	for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
-		cache_op(Index_Load_Tag_SD, addr);
+		cache_op_s(Index_Load_Tag_SD, addr);
 		__asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
 		if (!read_c0_taglo())
 			break;
-- 
2.21.0


  parent reply index

Thread overview: 152+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-01 15:35 [PATCH 000/120] Linux for the PlayStation 2 Fredrik Noring
2019-09-01 15:35 ` [PATCH 001/120] MIPS: R5900: Initial support for the Emotion Engine in " Fredrik Noring
2019-09-01 21:14   ` Maciej W. Rozycki
2019-09-02 15:09     ` Fredrik Noring
2019-09-01 15:36 ` [PATCH 002/120] MIPS: R5900: Trap the RDHWR instruction as an SQ address exception Fredrik Noring
2019-09-01 22:00   ` Maciej W. Rozycki
2019-09-01 15:36 ` [PATCH 003/120] MIPS: R5900: Sign-extend o32 system call registers Fredrik Noring
2019-09-01 15:37 ` [PATCH 004/120] MIPS: R5900: Reset bits 127..64 of GPRs in RESTORE_SOME Fredrik Noring
2019-09-01 15:38 ` [PATCH 005/120] MIPS: R5900: Reset the funnel shift amount (SA) register " Fredrik Noring
2019-09-01 15:38 ` [PATCH 006/120] MIPS: R5900: Workaround for the short loop bug Fredrik Noring
2019-09-01 15:39 ` [PATCH 007/120] MIPS: R5900: Add the SYNC.P instruction Fredrik Noring
2019-09-01 15:39 ` [PATCH 008/120] MIPS: R5900: Add implicit SYNC.P to the UASM_i_M[FT]C0 macros Fredrik Noring
2019-09-01 15:39 ` [PATCH 009/120] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring
2019-09-01 15:39 ` [PATCH 010/120] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring
2019-09-01 23:01   ` Philippe Mathieu-Daudé
2019-09-01 15:40 ` [PATCH 011/120] MIPS: R5900: Avoid pipeline hazard with the TLBP instruction Fredrik Noring
2019-09-01 17:15   ` Sergei Shtylyov
2019-09-01 17:36     ` Fredrik Noring
2019-09-01 15:40 ` [PATCH 012/120] MIPS: R5900: Avoid pipeline hazards with the TLBW[IR] instructions Fredrik Noring
2019-09-01 15:40 ` [PATCH 013/120] MIPS: R5900: Avoid pipeline hazard with the TLBR instruction Fredrik Noring
2019-09-01 15:41 ` [PATCH 014/120] MIPS: R5900: Install final length of TLB refill handler rather than 256 bytes Fredrik Noring
2019-09-01 15:41 ` [PATCH 015/120] MIPS: R5900: Verify that the TLB refill handler does not overflow Fredrik Noring
2019-09-01 15:41 ` [PATCH 016/120] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring
2019-09-01 15:42 ` [PATCH 017/120] MIPS: R5900: Define CACHE instruction operation field encodings Fredrik Noring
2019-09-01 15:42 ` [PATCH 018/120] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring
2019-09-01 15:42 ` Fredrik Noring [this message]
2019-09-01 15:43 ` [PATCH 020/120] MIPS: R5900: Define CP0.Config register fields Fredrik Noring
2019-09-01 23:04   ` Philippe Mathieu-Daudé
2019-09-01 15:43 ` [PATCH 021/120] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring
2019-09-01 15:46 ` [PATCH 022/120] MIPS: R5900: Support 64-bit inq() and outq() macros in 32-bit kernels Fredrik Noring
2019-09-04  1:04   ` Jiaxun Yang
2019-09-04 16:00     ` Maciej W. Rozycki
2019-09-01 15:46 ` [PATCH 023/120] MIPS: R5900: Add MFSA and MTSA instructions for the special SA register Fredrik Noring
2019-09-01 15:46 ` [PATCH 024/120] MIPS: PS2: Define PlayStation 2 I/O port, ROM and RAM address spaces Fredrik Noring
2019-09-01 15:47 ` [PATCH 025/120] MIPS: PS2: Define interrupt controller, DMA and timer IRQs Fredrik Noring
2019-09-01 15:47 ` [PATCH 026/120] MIPS: PS2: Interrupt controller (INTC) IRQ support Fredrik Noring
2019-09-01 15:47 ` [PATCH 027/120] MIPS: PS2: DMAC: Define DMA controller registers Fredrik Noring
2019-09-01 15:47 ` [PATCH 028/120] MIPS: PS2: DMAC: Define tag structures Fredrik Noring
2019-09-01 15:48 ` [PATCH 029/120] MIPS: PS2: DMAC: IRQ support Fredrik Noring
2019-09-01 15:48 ` [PATCH 030/120] MIPS: PS2: Timer support Fredrik Noring
2019-09-01 15:48 ` [PATCH 031/120] MIPS: PS2: SCMD: System command support Fredrik Noring
2019-09-01 15:48 ` [PATCH 032/120] MIPS: PS2: SCMD: System power off command Fredrik Noring
2019-09-01 15:48 ` [PATCH 033/120] MIPS: PS2: SCMD: Read system machine name command Fredrik Noring
2019-09-01 15:49 ` [PATCH 034/120] MIPS: PS2: SCMD: Read system command for the real-time clock (RTC) Fredrik Noring
2019-09-01 15:49 ` [PATCH 035/120] MIPS: PS2: SCMD: Set " Fredrik Noring
2019-09-01 15:49 ` [PATCH 036/120] MIPS: PS2: ROM: Iterate over the files in a given ROM directory Fredrik Noring
2019-09-01 15:49 ` [PATCH 037/120] MIPS: PS2: ROM: Find ROM files with a given name, if they exist Fredrik Noring
2019-09-01 15:50 ` [PATCH 038/120] MIPS: PS2: ROM: Read data for a given ROM file name Fredrik Noring
2019-09-02  9:05   ` Sergei Shtylyov
2019-09-04 11:46     ` Sergei Shtylyov
2019-09-06 13:07       ` Fredrik Noring
2019-09-01 15:50 ` [PATCH 039/120] MIPS: PS2: ROM: Read extended information for a given ROM file Fredrik Noring
2019-09-01 15:50 ` [PATCH 040/120] MIPS: PS2: ROM: Read and decode the ROMVER file Fredrik Noring
2019-09-01 15:52 ` [PATCH 041/120] MIPS: PS2: ROM: Resolve the name for the type in " Fredrik Noring
2019-09-01 15:52 ` [PATCH 042/120] MIPS: PS2: ROM: Resolve the name for the region " Fredrik Noring
2019-09-01 15:53 ` [PATCH 043/120] MIPS: PS2: ROM: Permit /dev/mem to access read-only memory Fredrik Noring
2019-09-01 15:53 ` [PATCH 044/120] MIPS: PS2: ROM: Sysfs module to inspect ROM files Fredrik Noring
2019-09-01 15:54 ` [PATCH 045/120] MIPS: PS2: ROM: Provide extended file information via sysfs Fredrik Noring
2019-09-01 15:54 ` [PATCH 046/120] MIPS: PS2: Identify the machine by model name Fredrik Noring
2019-09-01 15:54 ` [PATCH 047/120] MIPS: PS2: Let the system type be Sony PlayStation 2 Fredrik Noring
2019-09-01 23:09   ` Philippe Mathieu-Daudé
2019-09-01 15:55 ` [PATCH 048/120] MIPS: Define and use cpu_relax_forever() for various halting loops Fredrik Noring
2019-09-01 15:55 ` [PATCH 049/120] MIPS: PS2: Power off support Fredrik Noring
2019-09-01 15:55 ` [PATCH 050/120] MIPS: PS2: Real-time clock (RTC) driver Fredrik Noring
2019-09-01 15:56 ` [PATCH 051/120] MIPS: PS2: IOP: I/O processor DMA register PCR2 set and clear Fredrik Noring
2019-09-01 15:57 ` [PATCH 052/120] MIPS: PS2: SIF: Sub-system interface reset of the I/O processor (IOP) Fredrik Noring
2019-09-01 15:57 ` [PATCH 053/120] MIPS: PS2: IOP: Define error numbers, descriptions and errno mapping Fredrik Noring
2019-09-01 15:58 ` [PATCH 054/120] MIPS: PS2: SIF: SIF register write command support Fredrik Noring
2019-09-01 15:58 ` [PATCH 055/120] MIPS: PS2: SIF: Respond to remote procedure call (RPC) bind command Fredrik Noring
2019-09-01 15:58 ` [PATCH 056/120] MIPS: PS2: SIF: Respond to RPC bind end command Fredrik Noring
2019-09-01 15:59 ` [PATCH 057/120] MIPS: PS2: SIF: Reset the SIF0 (sub-to-main) DMA controller Fredrik Noring
2019-09-01 15:59 ` [PATCH 058/120] MIPS: PS2: SIF: Handle SIF0 (sub-to-main) RPCs via interrupts Fredrik Noring
2019-09-01 15:59 ` [PATCH 059/120] MIPS: PS2: SIF: Enable the IOP to issue SIF commands Fredrik Noring
2019-09-01 16:00 ` [PATCH 060/120] MIPS: PS2: SIF: Enable the IOP to issue SIF RPCs Fredrik Noring
2019-09-01 16:01 ` [PATCH 061/120] MIPS: PS2: SIF: sif_rpc_bind() to request an RPC server connection Fredrik Noring
2019-09-01 16:02 ` [PATCH 062/120] MIPS: PS2: SIF: sif_rpc_unbind() to release " Fredrik Noring
2019-09-01 16:02 ` [PATCH 063/120] MIPS: PS2: SIF: sif_rpc() to issue a remote procedure call Fredrik Noring
2019-09-01 16:03 ` [PATCH 064/120] MIPS: PS2: IOP: Permit /dev/mem to access IOP memory Fredrik Noring
2019-09-01 16:03 ` [PATCH 065/120] MIPS: PS2: IOP: I/O processor memory support Fredrik Noring
2019-09-01 16:10 ` [PATCH 066/120] FIXME: Export _dma_cache_{wback,wback_inv,inv} Fredrik Noring
2019-09-01 16:10 ` [PATCH 067/120] MIPS: PS2: IOP: Module linking support Fredrik Noring
2019-09-01 16:11 ` [PATCH 068/120] MIPS: PS2: IOP: Verify that modules are IRX objects Fredrik Noring
2019-09-01 16:11 ` [PATCH 069/120] MIPS: PS2: IOP: Module version compatibility verification Fredrik Noring
2019-09-01 16:11 ` [PATCH 070/120] MIPS: PS2: IOP: Avoid linking already linked library modules Fredrik Noring
2019-09-01 16:12 ` [PATCH 071/120] MIPS: PS2: IOP: Resolve module dependencies Fredrik Noring
2019-09-01 16:12 ` [PATCH 072/120] MIPS: PS2: IOP: SIF printk command support Fredrik Noring
2019-09-01 17:44   ` Sergei Shtylyov
2019-09-01 18:08     ` Fredrik Noring
2019-09-01 16:16 ` [PATCH 073/120] MIPS: PS2: IOP: Heap memory allocate and free Fredrik Noring
2019-09-01 16:16 ` [PATCH 074/120] MIPS: PS2: SIF: Request RPC IRQ command Fredrik Noring
2019-09-01 16:17 ` [PATCH 075/120] MIPS: PS2: IOP: IRQ support Fredrik Noring
2019-09-01 16:17 ` [PATCH 076/120] MIPS: PS2: GS: Define privileged Graphics Synthesizer registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 077/120] MIPS: PS2: GS: Write privileged registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 078/120] MIPS: PS2: GS: Read " Fredrik Noring
2019-09-01 16:18 ` [PATCH 079/120] MIPS: PS2: GS: Define privileged register structures Fredrik Noring
2019-09-01 16:19 ` [PATCH 080/120] MIPS: PS2: GS: Define gs_xorq_imr() Fredrik Noring
2019-09-01 16:20 ` [PATCH 081/120] MIPS: PS2: GS: Privileged register write macros with named fields Fredrik Noring
2019-09-01 16:20 ` [PATCH 082/120] MIPS: PS2: GS: IRQ support Fredrik Noring
2019-09-01 16:21 ` [PATCH 083/120] MIPS: PS2: GS: Define Graphics Synthesizer primitive structures Fredrik Noring
2019-09-01 16:21 ` [PATCH 084/120] MIPS: PS2: GIF: Define Graphics Synthesizer interface structures Fredrik Noring
2019-09-01 16:22 ` [PATCH 085/120] MIPS: PS2: GIF: Graphics Synthesizer interface support Fredrik Noring
2019-09-01 16:22 ` [PATCH 086/120] MIPS: PS2: GS: Graphics Synthesizer device init and video clock Fredrik Noring
2019-09-01 16:23 ` [PATCH 087/120] MIPS: PS2: GS: Compute block count and indices Fredrik Noring
2019-09-01 16:23 ` [PATCH 088/120] MIPS: PS2: GS: Primitive and texel coordinate transformations Fredrik Noring
2019-09-01 16:23 ` [PATCH 089/120] MIPS: PS2: GS: Approximate video region with ROM region Fredrik Noring
2019-09-01 16:24 ` [PATCH 090/120] macro: Extend COUNT_ARGS() from 12 to 32 arguments Fredrik Noring
2019-09-01 16:25 ` [PATCH 091/120] MIPS: PS2: GS: Show privileged registers with sysfs Fredrik Noring
2019-09-01 16:25 ` [PATCH 092/120] MIPS: PS2: GS: Store " Fredrik Noring
2019-09-01 16:25 ` [PATCH 093/120] fbdev: Add fb_warn_once() variant that only prints a warning once Fredrik Noring
2019-09-01 23:12   ` Philippe Mathieu-Daudé
2019-09-01 16:26 ` [PATCH 094/120] MIPS: PS2: FB: Frame buffer driver for the PlayStation 2 Fredrik Noring
2019-09-02  1:12   ` Jiaxun Yang
2019-09-02 14:40     ` Fredrik Noring
2019-09-02 17:47       ` Aaro Koskinen
2019-09-03 14:32         ` Fredrik Noring
2019-09-03  4:01       ` Jiaxun Yang
2019-09-03 17:42         ` Fredrik Noring
2019-09-03 17:59           ` Maciej W. Rozycki
2019-09-03 18:46             ` Fredrik Noring
2019-09-01 16:30 ` [PATCH 095/120] MIPS: PS2: FB: fb_set_par() standard-definition television support Fredrik Noring
2019-09-01 16:30 ` [PATCH 096/120] MIPS: PS2: FB: fb_set_par() high-definition " Fredrik Noring
2019-09-01 16:31 ` [PATCH 097/120] MIPS: PS2: FB: fb_set_par() VESA computer display mode support Fredrik Noring
2019-09-01 16:31 ` [PATCH 098/120] MIPS: PS2: FB: Preconfigure standard PAL, NTSC and VESA display modes Fredrik Noring
2019-09-01 16:31 ` [PATCH 099/120] MIPS: PS2: FB: Reset the Graphics Synthesizer drawing environment Fredrik Noring
2019-09-01 16:32 ` [PATCH 100/120] MIPS: PS2: FB: Clear the display buffer when changing video modes Fredrik Noring
2019-09-01 16:32 ` [PATCH 101/120] MIPS: PS2: FB: fb_setcolreg() 256 colour pseudo palette support Fredrik Noring
2019-09-01 16:32 ` [PATCH 102/120] MIPS: PS2: FB: fb_settile() with font stored as palette indexed textures Fredrik Noring
2019-09-01 16:32 ` [PATCH 103/120] MIPS: PS2: FB: Hardware accelerated fb_tilecopy() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 104/120] MIPS: PS2: FB: Hardware accelerated fb_tilefill() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 105/120] MIPS: PS2: FB: Simplified fb_tileblit() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 106/120] MIPS: PS2: FB: fb_tilecursor() placeholder Fredrik Noring
2019-09-01 16:33 ` [PATCH 107/120] MIPS: PS2: FB: Hardware accelerated fb_pan_display() support Fredrik Noring
2019-09-01 16:34 ` [PATCH 108/120] MIPS: PS2: FB: fb_blank() display power management signaling (DPMS) Fredrik Noring
2019-09-01 16:34 ` [PATCH 109/120] MIPS: PS2: FB: Disable GIF DMA completion interrupts Fredrik Noring
2019-09-01 16:34 ` [PATCH 110/120] MIPS: PS2: FB: PAL and NTSC grayscale support Fredrik Noring
2019-09-01 16:34 ` [PATCH 111/120] MIPS: PS2: FB: Analogue display mode adjustment module parameter Fredrik Noring
2019-09-01 16:35 ` [PATCH 112/120] USB: OHCI: Support for the PlayStation 2 Fredrik Noring
2019-09-01 16:35 ` [PATCH 113/120] USB: OHCI: OHCI_INTR_MIE workaround for freeze on " Fredrik Noring
2019-09-01 16:35 ` [PATCH 114/120] MIPS: PS2: Workaround for unexpected uLaunchELF CP0 Status user mode Fredrik Noring
2019-09-01 16:35 ` [PATCH 115/120] MIPS: PS2: Define initial PlayStation 2 devices Fredrik Noring
2019-09-01 16:35 ` [PATCH 116/120] MIPS: PS2: Define workarounds related to the PlayStation 2 Fredrik Noring
2019-09-01 16:36 ` [PATCH 117/120] MIPS: PS2: Define R5900 feature overrides Fredrik Noring
2019-09-01 16:36 ` [PATCH 118/120] MIPS: PS2: Define the PlayStation 2 platform Fredrik Noring
2019-09-01 16:36 ` [PATCH 119/120] MIPS: PS2: Initial support for the Sony PlayStation 2 Fredrik Noring
2019-09-01 16:37 ` [PATCH 120/120] MIPS: Fix name of BOOT_MEM_ROM_DATA Fredrik Noring
2019-09-01 23:15   ` Philippe Mathieu-Daudé
2019-09-02  1:02   ` Jiaxun Yang
2019-09-02 15:26     ` Fredrik Noring
2019-09-03  3:50       ` Jiaxun Yang
2019-09-03 16:06         ` Fredrik Noring
2019-09-04 14:19 ` [PATCH 000/120] Linux for the PlayStation 2 Paul Burton
2019-09-05 18:32   ` Fredrik Noring

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