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From: Fredrik Noring <noring@nocrew.org>
To: linux-mips@vger.kernel.org
Subject: [PATCH 052/120] MIPS: PS2: SIF: Sub-system interface reset of the I/O processor (IOP)
Date: Sun, 1 Sep 2019 17:57:12 +0200
Message-ID: <fb79dab2db2bfa9a06e96c211d27423d0c51399c.1567326213.git.noring@nocrew.org> (raw)
In-Reply-To: <cover.1567326213.git.noring@nocrew.org>

The sub-system interface (SIF) is the interface to exchange data between
the sub (input/output) processor (IOP) and the main (R5900) processor and
other devices connected to the main bus[1]. The IOP handles, in whole or
in part, most of the peripheral devices, including for example USB OHCI
interrupts.

DMA controllers (DMACs) for the IOP and the R5900 operate in cooperation
through a bidirectional FIFO in the SIF. There are three DMA channels:
SIF0 (sub-to-main), SIF1 (main-to-sub) and SIF2 (bidirectional).

Data is transferred in packets with a tag attached to each packet. The
tag contains the memory addresses in the IOP and R5900 address spaces
and the size of the data to transfer.

There are two mailbox type registers, the SMFLAG (sub-to-main) and
MSFLAG (main-to-sub), used to indicate certain events. The MAINADDR
and SUBADDR registers indicate the R5900 and IOP addresses where SIF
commands are transferred by the DMAC.

The IOP can assert interrupts via IRQ_INTC_SBUS.

This SIF kernel module resets the IOP during initialisation. The IOP
follows a certain boot protocol, with the following steps:

1. The kernel allocates a DMA memory buffer that the IOP can use to send
   commands. The kernel advertises this buffer by writing to the MAINADDR
   register.

2. The kernel reads the provisional SUBADDR register to obtain the
   corresponding command buffer for the IOP.

3. The kernel clears the SIF_STATUS_BOOTEND flag in the SMFLAG register.

4. The kernel issues the SIF_CMD_RESET_CMD command to the IOP.

5. The kernel indicates that the SIF and system commands are ready by
   setting the SIF_STATUS_SIFINIT and SIF_STATUS_CMDINIT flags in the
   SMFLAG register.

6. The kernel waits for the IOP to set the SIF_STATUS_BOOTEND flag in
   the SMFLAG register.

7. The kernel indicates that the boot is completed by writing updating
   its MAINADDR and setting the SIF_STATUS_CMDINIT and SIF_STATUS_BOOTEND
   flags in the MSFLAG register. The SIF_UNKNF260 register is set to 0xff.

8. The kernel reads the final SUBADDR register to obtain the command
   buffer for the IOP.

References:

[1] "EE Overview", version 6.0, Sony Computer Entertainment Inc., p. 47.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
 arch/mips/include/asm/mach-ps2/sif.h |  72 +++++
 drivers/ps2/Makefile                 |   1 +
 drivers/ps2/sif.c                    | 414 +++++++++++++++++++++++++++
 3 files changed, 487 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-ps2/sif.h
 create mode 100644 drivers/ps2/sif.c

diff --git a/arch/mips/include/asm/mach-ps2/sif.h b/arch/mips/include/asm/mach-ps2/sif.h
new file mode 100644
index 000000000000..94da96bd21d1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ps2/sif.h
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PlayStation 2 sub-system interface (SIF)
+ *
+ * The SIF is an interface unit to the input/output processor (IOP).
+ *
+ * Copyright (C) 2019 Fredrik Noring
+ */
+
+#ifndef __ASM_MACH_PS2_SIF_H
+#define __ASM_MACH_PS2_SIF_H
+
+#include <linux/types.h>
+#include <linux/completion.h>
+
+#include "iop-memory.h"
+
+#define SIF_MAINADDR 		0x1000f200	/* EE to IOP command buffer */
+#define SIF_SUBADDR  		0x1000f210	/* IOP to EE command buffer */
+#define SIF_MSFLAG   		0x1000f220	/* EE to IOP flag */
+#define SIF_SMFLAG   		0x1000f230	/* IOP to EE flag */
+#define SIF_SUBCTRL  		0x1000f240
+#define SIF_UNKNF260		0x1000f260
+
+/* Status flags for the sub-to-main (SM) and main-to-sub (MS) SIF registers. */
+#define SIF_STATUS_SIFINIT	0x10000		/* SIF initialised */
+#define SIF_STATUS_CMDINIT	0x20000		/* SIF CMD initialised */
+#define SIF_STATUS_BOOTEND	0x40000		/* IOP bootup completed */
+
+#define	SIF_CMD_ID_SYS		0x80000000
+#define	SIF_CMD_ID_USR		0x00000000
+
+#define SIF_CMD_CHANGE_SADDR	(SIF_CMD_ID_SYS | 0x00)
+#define SIF_CMD_WRITE_SREG	(SIF_CMD_ID_SYS | 0x01)
+#define SIF_CMD_INIT_CMD	(SIF_CMD_ID_SYS | 0x02)
+#define SIF_CMD_RESET_CMD	(SIF_CMD_ID_SYS | 0x03)
+#define SIF_CMD_RPC_END		(SIF_CMD_ID_SYS | 0x08)
+#define SIF_CMD_RPC_BIND	(SIF_CMD_ID_SYS | 0x09)
+#define SIF_CMD_RPC_CALL	(SIF_CMD_ID_SYS | 0x0a)
+#define SIF_CMD_RPC_RDATA	(SIF_CMD_ID_SYS | 0x0c)
+#define SIF_CMD_IRQ_RELAY	(SIF_CMD_ID_SYS | 0x20)
+#define SIF_CMD_PRINTK		(SIF_CMD_ID_SYS | 0x21)
+
+#define	SIF_SID_ID_SYS		0x80000000
+#define	SIF_SID_ID_USR		0x00000000
+
+#define SIF_SID_FILE_IO		(SIF_SID_ID_SYS | 0x01)
+#define SIF_SID_HEAP		(SIF_SID_ID_SYS | 0x03)
+#define SIF_SID_LOAD_MODULE	(SIF_SID_ID_SYS | 0x06)
+#define SIF_SID_IRQ_RELAY	(SIF_SID_ID_SYS | 0x20)
+
+#define SIF_CMD_PACKET_MAX	112
+#define SIF_CMD_PACKET_DATA_MAX 96
+
+/**
+ * struct sif_cmd_header - 16-byte SIF command header
+ * @packet_size: min 1x16 for header only, max 7*16 bytes
+ * @data_size: data size in bytes
+ * @data_addr: data address or zero
+ * @cmd: command number
+ * @opt: optional argument
+ */
+struct sif_cmd_header
+{
+	u32 packet_size : 8;
+	u32 data_size : 24;
+	u32 data_addr;
+	u32 cmd;
+	u32 opt;
+};
+
+#endif /* __ASM_MACH_PS2_SIF_H */
diff --git a/drivers/ps2/Makefile b/drivers/ps2/Makefile
index e53976ddb3e4..ef561a802bdd 100644
--- a/drivers/ps2/Makefile
+++ b/drivers/ps2/Makefile
@@ -1 +1,2 @@
 obj-m				+= iop-registers.o
+obj-m				+= sif.o
diff --git a/drivers/ps2/sif.c b/drivers/ps2/sif.c
new file mode 100644
index 000000000000..6564af245880
--- /dev/null
+++ b/drivers/ps2/sif.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PlayStation 2 sub-system interface (SIF)
+ *
+ * Copyright (C) 2019 Fredrik Noring
+ */
+
+/**
+ * DOC: The sub-system interface (SIF) for the input/output processor (IOP)
+ *
+ * The SIF is the interface to exchange data between the sub (input/output)
+ * processor (IOP) and the main (R5900) processor and other devices connected
+ * to the main bus. The IOP handles, in whole or in part, most of the
+ * peripheral devices, including for example USB OHCI interrupts.
+ *
+ * DMA controllers (DMACs) for the IOP and the R5900 operate in cooperation
+ * through a bidirectional FIFO in the SIF. There are three DMA channels:
+ * SIF0 (sub-to-main), SIF1 (main-to-sub) and SIF2 (bidirectional).
+ *
+ * Data is transferred in packets with a tag attached to each packet. The
+ * tag contains the memory addresses in the IOP and R5900 address spaces
+ * and the size of the data to transfer.
+ *
+ * There are two mailbox type registers, the SMFLAG (sub-to-main) and
+ * MSFLAG (main-to-sub), used to indicate certain events. The MAINADDR
+ * and SUBADDR registers indicate the R5900 and IOP addresses where SIF
+ * commands are transferred by the DMAC.
+ *
+ * The IOP can assert interrupts via %IRQ_INTC_SBUS.
+ */
+
+#include <linux/build_bug.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/sched/signal.h>
+#include <linux/types.h>
+
+#include <asm/io.h>
+
+#include <asm/mach-ps2/dmac.h>
+#include <asm/mach-ps2/irq.h>
+#include <asm/mach-ps2/sif.h>
+
+#define IOP_RESET_ARGS "rom0:UDNL rom0:OSDCNF"
+
+#define SIF0_BUFFER_SIZE	PAGE_SIZE
+#define SIF1_BUFFER_SIZE	PAGE_SIZE
+
+static iop_addr_t iop_buffer; /* Address of IOP SIF DMA receive address */
+static void *sif0_buffer;
+static void *sif1_buffer;
+
+/**
+ * sif_write_msflag - write to set main-to-sub flag register bits
+ * @mask: MSFLAG register bit values to set
+ */
+static void sif_write_msflag(u32 mask)
+{
+	outl(mask, SIF_MSFLAG);
+}
+
+/**
+ * sif_write_smflag - write to clear sub-to-main flag register bits
+ * @mask: SMFLAG register bit values to clear
+ */
+static void sif_write_smflag(u32 mask)
+{
+	outl(mask, SIF_SMFLAG);
+}
+
+/**
+ * sif_read_smflag - read the sub-to-main flag register
+ *
+ * Return: SMFLAG register value
+ */
+static u32 sif_read_smflag(void)
+{
+	u32 a = inl(SIF_SMFLAG);
+	u32 b;
+
+	do {
+		b = a;
+
+		a = inl(SIF_SMFLAG);
+	} while (a != b);	/* Ensure SMFLAG reading is stable */
+
+	return a;
+}
+
+static bool completed(bool (*condition)(void))
+{
+	const unsigned long timeout = jiffies + 5*HZ;
+
+	do {
+		if (condition())
+			return true;
+
+		msleep(1);
+	} while (time_is_after_jiffies(timeout));
+
+	return false;
+}
+
+static bool sif_smflag_cmdinit(void)
+{
+	return (sif_read_smflag() & SIF_STATUS_CMDINIT) != 0;
+}
+
+static bool sif_smflag_bootend(void)
+{
+	return (sif_read_smflag() & SIF_STATUS_BOOTEND) != 0;
+}
+
+static bool sif1_busy(void)
+{
+	return (inl(DMAC_SIF1_CHCR) & DMAC_CHCR_BUSY) != 0;
+}
+
+static bool sif1_ready(void)
+{
+	size_t countout = 50000;	/* About 5 s */
+
+	while (sif1_busy() && countout > 0) {
+		udelay(100);
+		countout--;
+	}
+
+	return countout > 0;
+}
+
+/* Bytes to 32-bit word count. */
+static u32 nbytes_to_wc(size_t nbytes)
+{
+	const u32 wc = nbytes / 4;
+
+	BUG_ON(nbytes & 0x3);	/* Word count must align */
+	BUG_ON(nbytes != (size_t)wc * 4);
+
+	return wc;
+}
+
+/* Bytes to 128-bit quadword count. */
+static u32 nbytes_to_qwc(size_t nbytes)
+{
+	const size_t qwc = nbytes / 16;
+
+	BUG_ON(nbytes & 0xf);	/* Quadword count must align */
+	BUG_ON(qwc > 0xffff);	/* QWC DMA field is only 16 bits */
+
+	return qwc;
+}
+
+static int sif1_write_ert_int_0(const struct sif_cmd_header *header,
+	bool ert, bool int_0, iop_addr_t dst, const void *src, size_t nbytes)
+{
+	const size_t header_size = header != NULL ? sizeof(*header) : 0;
+	const size_t aligned_size = ALIGN(header_size + nbytes, 16);
+	const struct iop_dma_tag iop_dma_tag = {
+		.ert	= ert,
+		.int_0	= int_0,
+		.addr	= dst,
+		.wc	= nbytes_to_wc(aligned_size)
+	};
+	const size_t dma_nbytes = sizeof(iop_dma_tag) + aligned_size;
+	u8 *dma_buffer = sif1_buffer;
+	dma_addr_t madr;
+
+	if (!aligned_size)
+		return 0;
+	if (dma_nbytes > SIF1_BUFFER_SIZE)
+		return -EINVAL;
+	if (!sif1_ready())
+		return -EBUSY;
+
+	memcpy(&dma_buffer[0], &iop_dma_tag, sizeof(iop_dma_tag));
+	memcpy(&dma_buffer[sizeof(iop_dma_tag)], header, header_size);
+	memcpy(&dma_buffer[sizeof(iop_dma_tag) + header_size], src, nbytes);
+
+	madr = virt_to_phys(dma_buffer);
+	dma_cache_wback((unsigned long)dma_buffer, dma_nbytes);
+
+	outl(madr, DMAC_SIF1_MADR);
+	outl(nbytes_to_qwc(dma_nbytes), DMAC_SIF1_QWC);
+	outl(DMAC_CHCR_SENDN_TIE, DMAC_SIF1_CHCR);
+
+	return 0;
+}
+
+static int sif1_write(const struct sif_cmd_header *header,
+	iop_addr_t dst, const void *src, size_t nbytes)
+{
+	return sif1_write_ert_int_0(header, false, false, dst, src, nbytes);
+}
+
+static int sif1_write_irq(const struct sif_cmd_header *header,
+	iop_addr_t dst, const void *src, size_t nbytes)
+{
+	return sif1_write_ert_int_0(header, true, true, dst, src, nbytes);
+}
+
+static int sif_cmd_opt_copy(u32 cmd_id, u32 opt, const void *pkt,
+	size_t pktsize, iop_addr_t dst, const void *src, size_t nbytes)
+{
+	const struct sif_cmd_header header = {
+		.packet_size = sizeof(header) + pktsize,
+		.data_size   = nbytes,
+		.data_addr   = dst,
+		.cmd         = cmd_id,
+		.opt         = opt
+	};
+	int err;
+
+	if (pktsize > SIF_CMD_PACKET_DATA_MAX)
+		return -EINVAL;
+
+	err = sif1_write(NULL, dst, src, nbytes);
+	if (!err)
+		err = sif1_write_irq(&header, iop_buffer, pkt, pktsize);
+
+	return err;
+}
+
+static int sif_cmd_copy(u32 cmd_id, const void *pkt, size_t pktsize,
+	iop_addr_t dst, const void *src, size_t nbytes)
+{
+	return sif_cmd_opt_copy(cmd_id, 0, pkt, pktsize, dst, src, nbytes);
+}
+
+static int sif_cmd(u32 cmd_id, const void *pkt, size_t pktsize)
+{
+	return sif_cmd_copy(cmd_id, pkt, pktsize, 0, NULL, 0);
+}
+
+static int iop_reset_arg(const char *arg)
+{
+	const size_t arglen = strlen(arg) + 1;
+	struct {
+		u32 arglen;
+		u32 mode;
+		char arg[79 + 1];	/* Including NUL */
+	} reset_pkt = {
+		.arglen = arglen,
+		.mode = 0
+	};
+	int err;
+
+	if (arglen > sizeof(reset_pkt.arg))
+		return -EINVAL;
+	memcpy(reset_pkt.arg, arg, arglen);
+
+	sif_write_smflag(SIF_STATUS_BOOTEND);
+
+	err = sif_cmd(SIF_CMD_RESET_CMD, &reset_pkt, sizeof(reset_pkt));
+	if (err)
+		return err;
+
+	sif_write_smflag(SIF_STATUS_SIFINIT | SIF_STATUS_CMDINIT);
+
+	return completed(sif_smflag_bootend) ? 0 : -EIO;
+}
+
+static int iop_reset(void)
+{
+	return iop_reset_arg(IOP_RESET_ARGS);
+}
+
+static int sif_read_subaddr(dma_addr_t *subaddr)
+{
+	if (!completed(sif_smflag_cmdinit))
+		return -EIO;
+
+	*subaddr = inl(SIF_SUBADDR);
+
+	return 0;
+}
+
+static void sif_write_mainaddr_bootend(dma_addr_t mainaddr)
+{
+	outl(0xff, SIF_UNKNF260);
+	outl(mainaddr, SIF_MAINADDR);
+	sif_write_msflag(SIF_STATUS_CMDINIT | SIF_STATUS_BOOTEND);
+}
+
+static void put_dma_buffers(void)
+{
+	free_page((unsigned long)sif1_buffer);
+	free_page((unsigned long)sif0_buffer);
+}
+
+static int get_dma_buffers(void)
+{
+	sif0_buffer = (void *)__get_free_page(GFP_DMA);
+	sif1_buffer = (void *)__get_free_page(GFP_DMA);
+
+	if (sif0_buffer == NULL ||
+	    sif1_buffer == NULL) {
+		put_dma_buffers();
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void sif_disable_dma(void)
+{
+	outl(DMAC_CHCR_STOP, DMAC_SIF0_CHCR);
+	outl(0, DMAC_SIF0_MADR);
+	outl(0, DMAC_SIF0_QWC);
+	inl(DMAC_SIF0_QWC);
+
+	outl(DMAC_CHCR_STOP, DMAC_SIF1_CHCR);
+}
+
+/**
+ * sif_init - initialise the SIF with a reset
+ *
+ * The IOP follows a certain boot protocol, with the following steps:
+ *
+ *  1. The kernel allocates a DMA memory buffer that the IOP can use to send
+ *     commands. The kernel advertises this buffer by writing to the MAINADDR
+ *     register.
+ *
+ *  2. The kernel reads the provisional SUBADDR register to obtain the
+ *     corresponding command buffer for the IOP.
+ *
+ *  3. The kernel clears the %SIF_STATUS_BOOTEND flag in the SMFLAG register.
+ *
+ *  4. The kernel issues the %SIF_CMD_RESET_CMD command to the IOP.
+ *
+ *  5. The kernel indicates that the SIF and system commands are ready by
+ *     setting the %SIF_STATUS_SIFINIT and %SIF_STATUS_CMDINIT flags in the
+ *     SMFLAG register.
+ *
+ *  6. The kernel waits for the IOP to set the %SIF_STATUS_BOOTEND flag in
+ *     the SMFLAG register.
+ *
+ *  7. The kernel indicates that the boot is completed by writing updating
+ *     its MAINADDR and setting the %SIF_STATUS_CMDINIT and %SIF_STATUS_BOOTEND
+ *     flags in the MSFLAG register. The %SIF_UNKNF260 register is set to 0xff.
+ *
+ *  8. The kernel reads the final SUBADDR register to obtain the command
+ *     buffer for the IOP.
+ *
+ * Return: 0 on success, otherwise a negative error number
+ */
+static int __init sif_init(void)
+{
+	int err;
+
+	BUILD_BUG_ON(sizeof(struct sif_cmd_header) != 16);
+
+	sif_disable_dma();
+
+	err = get_dma_buffers();
+	if (err) {
+		pr_err("sif: Failed to allocate DMA buffers with %d\n", err);
+		goto err_dma_buffers;
+	}
+
+	/* Read provisional SUBADDR in preparation for the IOP reset. */
+	err = sif_read_subaddr(&iop_buffer);
+	if (err) {
+		pr_err("sif: Failed to read provisional SUBADDR with %d\n",
+			err);
+		goto err_provisional_subaddr;
+	}
+
+	/* Write provisional MAINADDR in preparation for the IOP reset. */
+	sif_write_mainaddr_bootend(virt_to_phys(sif0_buffer));
+
+	err = iop_reset();
+	if (err) {
+		pr_err("sif: Failed to reset the IOP with %d\n", err);
+		goto err_iop_reset;
+	}
+
+	/* Write final MAINADDR and indicate end of boot. */
+	sif_write_mainaddr_bootend(virt_to_phys(sif0_buffer));
+
+	/* Read final SUBADDR. */
+	err = sif_read_subaddr(&iop_buffer);
+	if (err) {
+		pr_err("sif: Failed to read final SUBADDR with %d\n", err);
+		goto err_final_subaddr;
+	}
+
+	return 0;
+
+err_final_subaddr:
+err_iop_reset:
+err_provisional_subaddr:
+	put_dma_buffers();
+
+err_dma_buffers:
+	return err;
+}
+
+static void __exit sif_exit(void)
+{
+	sif_disable_dma();
+
+	put_dma_buffers();
+}
+
+module_init(sif_init);
+module_exit(sif_exit);
+
+MODULE_DESCRIPTION("PlayStation 2 sub-system interface (SIF)");
+MODULE_AUTHOR("Fredrik Noring");
+MODULE_LICENSE("GPL");
-- 
2.21.0


  parent reply index

Thread overview: 152+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-01 15:35 [PATCH 000/120] Linux for the PlayStation 2 Fredrik Noring
2019-09-01 15:35 ` [PATCH 001/120] MIPS: R5900: Initial support for the Emotion Engine in " Fredrik Noring
2019-09-01 21:14   ` Maciej W. Rozycki
2019-09-02 15:09     ` Fredrik Noring
2019-09-01 15:36 ` [PATCH 002/120] MIPS: R5900: Trap the RDHWR instruction as an SQ address exception Fredrik Noring
2019-09-01 22:00   ` Maciej W. Rozycki
2019-09-01 15:36 ` [PATCH 003/120] MIPS: R5900: Sign-extend o32 system call registers Fredrik Noring
2019-09-01 15:37 ` [PATCH 004/120] MIPS: R5900: Reset bits 127..64 of GPRs in RESTORE_SOME Fredrik Noring
2019-09-01 15:38 ` [PATCH 005/120] MIPS: R5900: Reset the funnel shift amount (SA) register " Fredrik Noring
2019-09-01 15:38 ` [PATCH 006/120] MIPS: R5900: Workaround for the short loop bug Fredrik Noring
2019-09-01 15:39 ` [PATCH 007/120] MIPS: R5900: Add the SYNC.P instruction Fredrik Noring
2019-09-01 15:39 ` [PATCH 008/120] MIPS: R5900: Add implicit SYNC.P to the UASM_i_M[FT]C0 macros Fredrik Noring
2019-09-01 15:39 ` [PATCH 009/120] MIPS: R5900: Add mandatory SYNC.P to all M[FT]C0 instructions Fredrik Noring
2019-09-01 15:39 ` [PATCH 010/120] MIPS: R5900: Workaround exception NOP execution bug (FLX05) Fredrik Noring
2019-09-01 23:01   ` Philippe Mathieu-Daudé
2019-09-01 15:40 ` [PATCH 011/120] MIPS: R5900: Avoid pipeline hazard with the TLBP instruction Fredrik Noring
2019-09-01 17:15   ` Sergei Shtylyov
2019-09-01 17:36     ` Fredrik Noring
2019-09-01 15:40 ` [PATCH 012/120] MIPS: R5900: Avoid pipeline hazards with the TLBW[IR] instructions Fredrik Noring
2019-09-01 15:40 ` [PATCH 013/120] MIPS: R5900: Avoid pipeline hazard with the TLBR instruction Fredrik Noring
2019-09-01 15:41 ` [PATCH 014/120] MIPS: R5900: Install final length of TLB refill handler rather than 256 bytes Fredrik Noring
2019-09-01 15:41 ` [PATCH 015/120] MIPS: R5900: Verify that the TLB refill handler does not overflow Fredrik Noring
2019-09-01 15:41 ` [PATCH 016/120] MIPS: R5900: The ERET instruction has issues with delay slot and CACHE Fredrik Noring
2019-09-01 15:42 ` [PATCH 017/120] MIPS: R5900: Define CACHE instruction operation field encodings Fredrik Noring
2019-09-01 15:42 ` [PATCH 018/120] MIPS: R5900: Workaround where MSB must be 0 for the instruction cache Fredrik Noring
2019-09-01 15:42 ` [PATCH 019/120] MIPS: R5900: Use SYNC.L for data cache and SYNC.P for " Fredrik Noring
2019-09-01 15:43 ` [PATCH 020/120] MIPS: R5900: Define CP0.Config register fields Fredrik Noring
2019-09-01 23:04   ` Philippe Mathieu-Daudé
2019-09-01 15:43 ` [PATCH 021/120] MIPS: R5900: Workaround for CACHE instruction near branch delay slot Fredrik Noring
2019-09-01 15:46 ` [PATCH 022/120] MIPS: R5900: Support 64-bit inq() and outq() macros in 32-bit kernels Fredrik Noring
2019-09-04  1:04   ` Jiaxun Yang
2019-09-04 16:00     ` Maciej W. Rozycki
2019-09-01 15:46 ` [PATCH 023/120] MIPS: R5900: Add MFSA and MTSA instructions for the special SA register Fredrik Noring
2019-09-01 15:46 ` [PATCH 024/120] MIPS: PS2: Define PlayStation 2 I/O port, ROM and RAM address spaces Fredrik Noring
2019-09-01 15:47 ` [PATCH 025/120] MIPS: PS2: Define interrupt controller, DMA and timer IRQs Fredrik Noring
2019-09-01 15:47 ` [PATCH 026/120] MIPS: PS2: Interrupt controller (INTC) IRQ support Fredrik Noring
2019-09-01 15:47 ` [PATCH 027/120] MIPS: PS2: DMAC: Define DMA controller registers Fredrik Noring
2019-09-01 15:47 ` [PATCH 028/120] MIPS: PS2: DMAC: Define tag structures Fredrik Noring
2019-09-01 15:48 ` [PATCH 029/120] MIPS: PS2: DMAC: IRQ support Fredrik Noring
2019-09-01 15:48 ` [PATCH 030/120] MIPS: PS2: Timer support Fredrik Noring
2019-09-01 15:48 ` [PATCH 031/120] MIPS: PS2: SCMD: System command support Fredrik Noring
2019-09-01 15:48 ` [PATCH 032/120] MIPS: PS2: SCMD: System power off command Fredrik Noring
2019-09-01 15:48 ` [PATCH 033/120] MIPS: PS2: SCMD: Read system machine name command Fredrik Noring
2019-09-01 15:49 ` [PATCH 034/120] MIPS: PS2: SCMD: Read system command for the real-time clock (RTC) Fredrik Noring
2019-09-01 15:49 ` [PATCH 035/120] MIPS: PS2: SCMD: Set " Fredrik Noring
2019-09-01 15:49 ` [PATCH 036/120] MIPS: PS2: ROM: Iterate over the files in a given ROM directory Fredrik Noring
2019-09-01 15:49 ` [PATCH 037/120] MIPS: PS2: ROM: Find ROM files with a given name, if they exist Fredrik Noring
2019-09-01 15:50 ` [PATCH 038/120] MIPS: PS2: ROM: Read data for a given ROM file name Fredrik Noring
2019-09-02  9:05   ` Sergei Shtylyov
2019-09-04 11:46     ` Sergei Shtylyov
2019-09-06 13:07       ` Fredrik Noring
2019-09-01 15:50 ` [PATCH 039/120] MIPS: PS2: ROM: Read extended information for a given ROM file Fredrik Noring
2019-09-01 15:50 ` [PATCH 040/120] MIPS: PS2: ROM: Read and decode the ROMVER file Fredrik Noring
2019-09-01 15:52 ` [PATCH 041/120] MIPS: PS2: ROM: Resolve the name for the type in " Fredrik Noring
2019-09-01 15:52 ` [PATCH 042/120] MIPS: PS2: ROM: Resolve the name for the region " Fredrik Noring
2019-09-01 15:53 ` [PATCH 043/120] MIPS: PS2: ROM: Permit /dev/mem to access read-only memory Fredrik Noring
2019-09-01 15:53 ` [PATCH 044/120] MIPS: PS2: ROM: Sysfs module to inspect ROM files Fredrik Noring
2019-09-01 15:54 ` [PATCH 045/120] MIPS: PS2: ROM: Provide extended file information via sysfs Fredrik Noring
2019-09-01 15:54 ` [PATCH 046/120] MIPS: PS2: Identify the machine by model name Fredrik Noring
2019-09-01 15:54 ` [PATCH 047/120] MIPS: PS2: Let the system type be Sony PlayStation 2 Fredrik Noring
2019-09-01 23:09   ` Philippe Mathieu-Daudé
2019-09-01 15:55 ` [PATCH 048/120] MIPS: Define and use cpu_relax_forever() for various halting loops Fredrik Noring
2019-09-01 15:55 ` [PATCH 049/120] MIPS: PS2: Power off support Fredrik Noring
2019-09-01 15:55 ` [PATCH 050/120] MIPS: PS2: Real-time clock (RTC) driver Fredrik Noring
2019-09-01 15:56 ` [PATCH 051/120] MIPS: PS2: IOP: I/O processor DMA register PCR2 set and clear Fredrik Noring
2019-09-01 15:57 ` Fredrik Noring [this message]
2019-09-01 15:57 ` [PATCH 053/120] MIPS: PS2: IOP: Define error numbers, descriptions and errno mapping Fredrik Noring
2019-09-01 15:58 ` [PATCH 054/120] MIPS: PS2: SIF: SIF register write command support Fredrik Noring
2019-09-01 15:58 ` [PATCH 055/120] MIPS: PS2: SIF: Respond to remote procedure call (RPC) bind command Fredrik Noring
2019-09-01 15:58 ` [PATCH 056/120] MIPS: PS2: SIF: Respond to RPC bind end command Fredrik Noring
2019-09-01 15:59 ` [PATCH 057/120] MIPS: PS2: SIF: Reset the SIF0 (sub-to-main) DMA controller Fredrik Noring
2019-09-01 15:59 ` [PATCH 058/120] MIPS: PS2: SIF: Handle SIF0 (sub-to-main) RPCs via interrupts Fredrik Noring
2019-09-01 15:59 ` [PATCH 059/120] MIPS: PS2: SIF: Enable the IOP to issue SIF commands Fredrik Noring
2019-09-01 16:00 ` [PATCH 060/120] MIPS: PS2: SIF: Enable the IOP to issue SIF RPCs Fredrik Noring
2019-09-01 16:01 ` [PATCH 061/120] MIPS: PS2: SIF: sif_rpc_bind() to request an RPC server connection Fredrik Noring
2019-09-01 16:02 ` [PATCH 062/120] MIPS: PS2: SIF: sif_rpc_unbind() to release " Fredrik Noring
2019-09-01 16:02 ` [PATCH 063/120] MIPS: PS2: SIF: sif_rpc() to issue a remote procedure call Fredrik Noring
2019-09-01 16:03 ` [PATCH 064/120] MIPS: PS2: IOP: Permit /dev/mem to access IOP memory Fredrik Noring
2019-09-01 16:03 ` [PATCH 065/120] MIPS: PS2: IOP: I/O processor memory support Fredrik Noring
2019-09-01 16:10 ` [PATCH 066/120] FIXME: Export _dma_cache_{wback,wback_inv,inv} Fredrik Noring
2019-09-01 16:10 ` [PATCH 067/120] MIPS: PS2: IOP: Module linking support Fredrik Noring
2019-09-01 16:11 ` [PATCH 068/120] MIPS: PS2: IOP: Verify that modules are IRX objects Fredrik Noring
2019-09-01 16:11 ` [PATCH 069/120] MIPS: PS2: IOP: Module version compatibility verification Fredrik Noring
2019-09-01 16:11 ` [PATCH 070/120] MIPS: PS2: IOP: Avoid linking already linked library modules Fredrik Noring
2019-09-01 16:12 ` [PATCH 071/120] MIPS: PS2: IOP: Resolve module dependencies Fredrik Noring
2019-09-01 16:12 ` [PATCH 072/120] MIPS: PS2: IOP: SIF printk command support Fredrik Noring
2019-09-01 17:44   ` Sergei Shtylyov
2019-09-01 18:08     ` Fredrik Noring
2019-09-01 16:16 ` [PATCH 073/120] MIPS: PS2: IOP: Heap memory allocate and free Fredrik Noring
2019-09-01 16:16 ` [PATCH 074/120] MIPS: PS2: SIF: Request RPC IRQ command Fredrik Noring
2019-09-01 16:17 ` [PATCH 075/120] MIPS: PS2: IOP: IRQ support Fredrik Noring
2019-09-01 16:17 ` [PATCH 076/120] MIPS: PS2: GS: Define privileged Graphics Synthesizer registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 077/120] MIPS: PS2: GS: Write privileged registers Fredrik Noring
2019-09-01 16:18 ` [PATCH 078/120] MIPS: PS2: GS: Read " Fredrik Noring
2019-09-01 16:18 ` [PATCH 079/120] MIPS: PS2: GS: Define privileged register structures Fredrik Noring
2019-09-01 16:19 ` [PATCH 080/120] MIPS: PS2: GS: Define gs_xorq_imr() Fredrik Noring
2019-09-01 16:20 ` [PATCH 081/120] MIPS: PS2: GS: Privileged register write macros with named fields Fredrik Noring
2019-09-01 16:20 ` [PATCH 082/120] MIPS: PS2: GS: IRQ support Fredrik Noring
2019-09-01 16:21 ` [PATCH 083/120] MIPS: PS2: GS: Define Graphics Synthesizer primitive structures Fredrik Noring
2019-09-01 16:21 ` [PATCH 084/120] MIPS: PS2: GIF: Define Graphics Synthesizer interface structures Fredrik Noring
2019-09-01 16:22 ` [PATCH 085/120] MIPS: PS2: GIF: Graphics Synthesizer interface support Fredrik Noring
2019-09-01 16:22 ` [PATCH 086/120] MIPS: PS2: GS: Graphics Synthesizer device init and video clock Fredrik Noring
2019-09-01 16:23 ` [PATCH 087/120] MIPS: PS2: GS: Compute block count and indices Fredrik Noring
2019-09-01 16:23 ` [PATCH 088/120] MIPS: PS2: GS: Primitive and texel coordinate transformations Fredrik Noring
2019-09-01 16:23 ` [PATCH 089/120] MIPS: PS2: GS: Approximate video region with ROM region Fredrik Noring
2019-09-01 16:24 ` [PATCH 090/120] macro: Extend COUNT_ARGS() from 12 to 32 arguments Fredrik Noring
2019-09-01 16:25 ` [PATCH 091/120] MIPS: PS2: GS: Show privileged registers with sysfs Fredrik Noring
2019-09-01 16:25 ` [PATCH 092/120] MIPS: PS2: GS: Store " Fredrik Noring
2019-09-01 16:25 ` [PATCH 093/120] fbdev: Add fb_warn_once() variant that only prints a warning once Fredrik Noring
2019-09-01 23:12   ` Philippe Mathieu-Daudé
2019-09-01 16:26 ` [PATCH 094/120] MIPS: PS2: FB: Frame buffer driver for the PlayStation 2 Fredrik Noring
2019-09-02  1:12   ` Jiaxun Yang
2019-09-02 14:40     ` Fredrik Noring
2019-09-02 17:47       ` Aaro Koskinen
2019-09-03 14:32         ` Fredrik Noring
2019-09-03  4:01       ` Jiaxun Yang
2019-09-03 17:42         ` Fredrik Noring
2019-09-03 17:59           ` Maciej W. Rozycki
2019-09-03 18:46             ` Fredrik Noring
2019-09-01 16:30 ` [PATCH 095/120] MIPS: PS2: FB: fb_set_par() standard-definition television support Fredrik Noring
2019-09-01 16:30 ` [PATCH 096/120] MIPS: PS2: FB: fb_set_par() high-definition " Fredrik Noring
2019-09-01 16:31 ` [PATCH 097/120] MIPS: PS2: FB: fb_set_par() VESA computer display mode support Fredrik Noring
2019-09-01 16:31 ` [PATCH 098/120] MIPS: PS2: FB: Preconfigure standard PAL, NTSC and VESA display modes Fredrik Noring
2019-09-01 16:31 ` [PATCH 099/120] MIPS: PS2: FB: Reset the Graphics Synthesizer drawing environment Fredrik Noring
2019-09-01 16:32 ` [PATCH 100/120] MIPS: PS2: FB: Clear the display buffer when changing video modes Fredrik Noring
2019-09-01 16:32 ` [PATCH 101/120] MIPS: PS2: FB: fb_setcolreg() 256 colour pseudo palette support Fredrik Noring
2019-09-01 16:32 ` [PATCH 102/120] MIPS: PS2: FB: fb_settile() with font stored as palette indexed textures Fredrik Noring
2019-09-01 16:32 ` [PATCH 103/120] MIPS: PS2: FB: Hardware accelerated fb_tilecopy() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 104/120] MIPS: PS2: FB: Hardware accelerated fb_tilefill() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 105/120] MIPS: PS2: FB: Simplified fb_tileblit() support Fredrik Noring
2019-09-01 16:33 ` [PATCH 106/120] MIPS: PS2: FB: fb_tilecursor() placeholder Fredrik Noring
2019-09-01 16:33 ` [PATCH 107/120] MIPS: PS2: FB: Hardware accelerated fb_pan_display() support Fredrik Noring
2019-09-01 16:34 ` [PATCH 108/120] MIPS: PS2: FB: fb_blank() display power management signaling (DPMS) Fredrik Noring
2019-09-01 16:34 ` [PATCH 109/120] MIPS: PS2: FB: Disable GIF DMA completion interrupts Fredrik Noring
2019-09-01 16:34 ` [PATCH 110/120] MIPS: PS2: FB: PAL and NTSC grayscale support Fredrik Noring
2019-09-01 16:34 ` [PATCH 111/120] MIPS: PS2: FB: Analogue display mode adjustment module parameter Fredrik Noring
2019-09-01 16:35 ` [PATCH 112/120] USB: OHCI: Support for the PlayStation 2 Fredrik Noring
2019-09-01 16:35 ` [PATCH 113/120] USB: OHCI: OHCI_INTR_MIE workaround for freeze on " Fredrik Noring
2019-09-01 16:35 ` [PATCH 114/120] MIPS: PS2: Workaround for unexpected uLaunchELF CP0 Status user mode Fredrik Noring
2019-09-01 16:35 ` [PATCH 115/120] MIPS: PS2: Define initial PlayStation 2 devices Fredrik Noring
2019-09-01 16:35 ` [PATCH 116/120] MIPS: PS2: Define workarounds related to the PlayStation 2 Fredrik Noring
2019-09-01 16:36 ` [PATCH 117/120] MIPS: PS2: Define R5900 feature overrides Fredrik Noring
2019-09-01 16:36 ` [PATCH 118/120] MIPS: PS2: Define the PlayStation 2 platform Fredrik Noring
2019-09-01 16:36 ` [PATCH 119/120] MIPS: PS2: Initial support for the Sony PlayStation 2 Fredrik Noring
2019-09-01 16:37 ` [PATCH 120/120] MIPS: Fix name of BOOT_MEM_ROM_DATA Fredrik Noring
2019-09-01 23:15   ` Philippe Mathieu-Daudé
2019-09-02  1:02   ` Jiaxun Yang
2019-09-02 15:26     ` Fredrik Noring
2019-09-03  3:50       ` Jiaxun Yang
2019-09-03 16:06         ` Fredrik Noring
2019-09-04 14:19 ` [PATCH 000/120] Linux for the PlayStation 2 Paul Burton
2019-09-05 18:32   ` Fredrik Noring

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