From: Pratyush Yadav <p.yadav@ti.com>
To: <Tudor.Ambarus@microchip.com>
Cc: vigneshr@ti.com, richard@nod.at, nsekhar@ti.com,
linux-kernel@vger.kernel.org, boris.brezillon@collabora.com,
linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com
Subject: Re: [PATCH v13 06/15] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
Date: Wed, 30 Sep 2020 12:23:27 +0530 [thread overview]
Message-ID: <20200930065325.umw6kf3m3vzq4r5z@ti.com> (raw)
In-Reply-To: <c4ff4fba-cad5-de10-93e8-97a4e2edecf0@microchip.com>
On 30/09/20 06:44AM, Tudor.Ambarus@microchip.com wrote:
> On 9/16/20 3:44 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > This table is indication that the flash is xSPI compliant and hence
> > supports octal DTR mode. Extract information like the fast read opcode,
> > dummy cycles, the number of dummy cycles needed for a Read Status
> > Register command, and the number of address bytes needed for a Read
> > Status Register command.
> >
> > We don't know what speed the controller is running at. Find the fast
> > read dummy cycles for the fastest frequency the flash can run at to be
> > sure we are never short of dummy cycles. If nothing is available,
> > default to 20. Flashes that use a different value should update it in
> > their fixup hooks.
> >
> > Since we want to set read settings, expose spi_nor_set_read_settings()
> > in core.h.
> >
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> > drivers/mtd/spi-nor/core.c | 2 +-
> > drivers/mtd/spi-nor/core.h | 10 +++++
> > drivers/mtd/spi-nor/sfdp.c | 91 ++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 102 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> > index 7445d7122304..cbb1aab27d03 100644
> > --- a/drivers/mtd/spi-nor/core.c
> > +++ b/drivers/mtd/spi-nor/core.c
...
> > @@ -1108,6 +1110,91 @@ static int spi_nor_parse_4bait(struct spi_nor
> > *nor,
> > return ret;
> > }
> >
> > +#define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
> > +#define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
> > +#define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
> > +#define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
> > +#define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
> > +#define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
> > +#define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
> > +#define PROFILE1_DUMMY_DEFAULT 20
> > +
> > +/**
> > + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
> > + * @nor: pointer to a 'struct spi_nor'
> > + * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
> > + * the 4-Byte Address Instruction Table length and version.
>
> Profile 1.0 Table
Oops! Will fix.
> > + * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
> > + *
> > + * Return: 0 on success, -errno otherwise.
> > + */
...
> > + /*
> > + * We don't know what speed the controller is running at. Find the
> > + * dummy cycles for the fastest frequency the flash can run at to be
> > + * sure we are never short of dummy cycles. A value of 0 means the
> > + * frequency is not supported.
> > + *
> > + * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
> > + * flashes set the correct value if needed in their fixup hooks.
> > + */
> > + dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, dwords[3]);
> > + if (!dummy)
> > + dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, dwords[4]);
> > + if (!dummy)
> > + dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, dwords[4]);
> > + if (!dummy)
> > + dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, dwords[4]);
> > + if (!dummy)
> > + dummy = PROFILE1_DUMMY_DEFAULT;
>
> just a dev_dbg here, without assuming what default value means
And we leave dummy to 0, correct?
--
Regards,
Pratyush Yadav
Texas Instruments India
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next prev parent reply other threads:[~2020-09-30 6:54 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 12:44 [PATCH v13 00/15] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 01/15] mtd: spi-nor: core: use EOPNOTSUPP instead of ENOTSUPP Pratyush Yadav
2020-09-29 11:30 ` Tudor.Ambarus
2020-09-16 12:44 ` [PATCH v13 02/15] mtd: spi-nor: core: add spi_nor_{read, write}_reg() helpers Pratyush Yadav
2020-09-29 11:38 ` [PATCH v13 02/15] mtd: spi-nor: core: add spi_nor_{read,write}_reg() helpers Tudor.Ambarus
2020-09-29 12:54 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 03/15] mtd: spi-nor: core: add spi_nor_controller_ops_erase helper Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 04/15] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 05/15] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-09-30 6:17 ` Tudor.Ambarus
2020-09-16 12:44 ` [PATCH v13 06/15] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-09-30 6:44 ` Tudor.Ambarus
2020-09-30 6:53 ` Pratyush Yadav [this message]
2020-09-16 12:44 ` [PATCH v13 07/15] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-09-30 6:46 ` Tudor.Ambarus
2020-09-16 12:44 ` [PATCH v13 08/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-09-30 6:50 ` Tudor.Ambarus
2020-09-30 6:55 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 09/15] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-09-29 11:26 ` Tudor.Ambarus
2020-09-29 12:51 ` Pratyush Yadav
2020-09-29 13:05 ` Tudor.Ambarus
2020-09-30 7:11 ` Tudor.Ambarus
2020-09-16 12:44 ` [PATCH v13 10/15] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-09-30 7:23 ` Tudor.Ambarus
2020-09-30 7:31 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 11/15] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-09-29 13:08 ` Pratyush Yadav
2020-09-30 7:32 ` Tudor.Ambarus
2020-09-30 7:43 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 12/15] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-09-30 7:40 ` Tudor.Ambarus
2020-09-30 7:44 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 13/15] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-09-30 7:51 ` Tudor.Ambarus
2020-09-30 8:03 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 14/15] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-09-30 8:36 ` Tudor.Ambarus
2020-09-30 12:32 ` Pratyush Yadav
2020-09-16 12:44 ` [PATCH v13 15/15] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav
2020-09-30 9:12 ` Tudor.Ambarus
2020-09-29 9:59 ` [RFC PATCH 0/3] mtd: spi-nor: Tackle stateful modes Tudor Ambarus
2020-09-29 9:59 ` [RFC PATCH 1/3] mtd: spi-nor: Introduce SNOR_F_IO_MODE_EN_VOLATILE Tudor Ambarus
2020-09-29 16:45 ` Vignesh Raghavendra
2020-09-29 9:59 ` [RFC PATCH 2/3] mtd: spi-nor: Introduce MTD_SPI_NOR_ALLOW_STATEFUL_MODES Tudor Ambarus
2020-09-29 16:45 ` Vignesh Raghavendra
2020-09-29 9:59 ` [RFC PATCH 3/3] mtd: spi-nor: Parse SFDP SCCR Map Tudor Ambarus
2020-09-30 9:57 ` [PATCH v13 00/15] mtd: spi-nor: add xSPI Octal DTR support Tudor.Ambarus
2020-09-30 12:01 ` Pratyush Yadav
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