From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ira Weiny <ira.weiny@intel.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v6 06/10] cxl/pci: Add @base to cxl_register_map
Date: Fri, 15 Oct 2021 14:57:27 -0700 [thread overview]
Message-ID: <163433497228.889435.11271988238496181536.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <163416940205.816123.10667482871687420836.stgit@dwillia2-desk3.amr.corp.intel.com>
In addition to carrying @barno, @block_offset, and @reg_type, add @base
to keep all map/unmap parameters in one object. The helpers
cxl_{map,unmap}_regblock() handle adjusting @base to the @block_offset
at map and unmap time.
Document that @base incorporates @block_offset so that downstream
consumers of a mapped cxl_register_map instance do not need perform any
fixups / can use @base directly.
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
Changes since v5:
- add kernel-doc for cxl_register_map to explain the interaction between
@base and @block_offset. (Ira and Jonathan)
drivers/cxl/cxl.h | 10 ++++++++++
drivers/cxl/pci.c | 31 ++++++++++++++++---------------
2 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index a6687e7fd598..5e2e93451928 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -139,7 +139,17 @@ struct cxl_device_reg_map {
struct cxl_reg_map memdev;
};
+/**
+ * struct cxl_register_map - DVSEC harvested register block mapping parameters
+ * @base: virtual base of the register-block-BAR + @block_offset
+ * @block_offset: offset to start of register block in @barno
+ * @reg_type: see enum cxl_regloc_type
+ * @barno: PCI BAR number containing the register block
+ * @component_map: cxl_reg_map for component registers
+ * @device_map: cxl_reg_maps for device registers
+ */
struct cxl_register_map {
+ void __iomem *base;
u64 block_offset;
u8 reg_type;
u8 barno;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index eb0c2f1b9e65..7d5e5548b316 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -306,8 +306,7 @@ static int cxl_pci_setup_mailbox(struct cxl_mem *cxlm)
return 0;
}
-static void __iomem *cxl_pci_map_regblock(struct pci_dev *pdev,
- struct cxl_register_map *map)
+static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
{
void __iomem *addr;
int bar = map->barno;
@@ -318,24 +317,27 @@ static void __iomem *cxl_pci_map_regblock(struct pci_dev *pdev,
if (pci_resource_len(pdev, bar) < offset) {
dev_err(dev, "BAR%d: %pr: too small (offset: %pa)\n", bar,
&pdev->resource[bar], &offset);
- return NULL;
+ return -ENXIO;
}
addr = pci_iomap(pdev, bar, 0);
if (!addr) {
dev_err(dev, "failed to map registers\n");
- return addr;
+ return -ENOMEM;
}
dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %pa\n",
bar, &offset);
- return addr;
+ map->base = addr + map->block_offset;
+ return 0;
}
-static void cxl_pci_unmap_regblock(struct pci_dev *pdev, void __iomem *base)
+static void cxl_unmap_regblock(struct pci_dev *pdev,
+ struct cxl_register_map *map)
{
- pci_iounmap(pdev, base);
+ pci_iounmap(pdev, map->base - map->block_offset);
+ map->base = NULL;
}
static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
@@ -361,12 +363,12 @@ static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
return 0;
}
-static int cxl_probe_regs(struct pci_dev *pdev, void __iomem *base,
- struct cxl_register_map *map)
+static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map)
{
struct cxl_component_reg_map *comp_map;
struct cxl_device_reg_map *dev_map;
struct device *dev = &pdev->dev;
+ void __iomem *base = map->base;
switch (map->reg_type) {
case CXL_REGLOC_RBI_COMPONENT:
@@ -442,7 +444,6 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
*/
static int cxl_pci_setup_regs(struct cxl_mem *cxlm)
{
- void __iomem *base;
u32 regloc_size, regblocks;
int regloc, i, n_maps, ret = 0;
struct device *dev = cxlm->dev;
@@ -475,12 +476,12 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm)
if (map->reg_type > CXL_REGLOC_RBI_MEMDEV)
continue;
- base = cxl_pci_map_regblock(pdev, map);
- if (!base)
- return -ENOMEM;
+ ret = cxl_map_regblock(pdev, map);
+ if (ret)
+ return ret;
- ret = cxl_probe_regs(pdev, base + map->block_offset, map);
- cxl_pci_unmap_regblock(pdev, base);
+ ret = cxl_probe_regs(pdev, map);
+ cxl_unmap_regblock(pdev, map);
if (ret)
return ret;
next prev parent reply other threads:[~2021-10-15 21:57 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-09 16:43 [PATCH v3 00/10] cxl_pci refactor for reusability Dan Williams
2021-10-09 16:44 ` [PATCH v3 01/10] cxl/pci: Convert register block identifiers to an enum Dan Williams
2021-10-09 16:44 ` [PATCH v3 02/10] cxl/pci: Remove dev_dbg for unknown register blocks Dan Williams
2021-10-09 16:48 ` Joe Perches
2021-10-09 18:04 ` Ben Widawsky
2021-10-09 16:44 ` [PATCH v3 03/10] cxl/pci: Fix NULL vs ERR_PTR confusion Dan Williams
2021-10-10 3:44 ` Ira Weiny
2021-10-15 16:15 ` Jonathan Cameron
2021-10-15 20:16 ` Dan Williams
2021-10-15 21:29 ` [PATCH v6 " Dan Williams
2021-10-09 16:44 ` [PATCH v3 04/10] cxl/pci: Remove pci request/release regions Dan Williams
2021-10-09 16:44 ` [PATCH v3 05/10] cxl/pci: Make more use of cxl_register_map Dan Williams
2021-10-09 19:04 ` kernel test robot
2021-10-09 20:51 ` [PATCH v4 " Dan Williams
2021-10-10 4:03 ` Ira Weiny
2021-10-13 23:53 ` [PATCH v5 " Dan Williams
2021-10-09 16:44 ` [PATCH v3 06/10] cxl/pci: Add @base to cxl_register_map Dan Williams
2021-10-10 4:20 ` Ira Weiny
2021-10-13 22:53 ` Dan Williams
2021-10-15 16:29 ` Jonathan Cameron
2021-10-15 16:56 ` Dan Williams
2021-10-13 23:57 ` [PATCH v5 " Dan Williams
2021-10-15 21:57 ` Dan Williams [this message]
2021-10-18 9:30 ` [PATCH v6 " Jonathan Cameron
2021-10-15 16:27 ` [PATCH v3 " Jonathan Cameron
2021-10-15 16:55 ` Dan Williams
2021-10-18 9:30 ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 07/10] cxl/pci: Split cxl_pci_setup_regs() Dan Williams
2021-10-10 4:44 ` Ira Weiny
2021-10-13 22:45 ` Ben Widawsky
2021-10-13 22:49 ` Dan Williams
2021-10-14 0:12 ` Ben Widawsky
2021-10-14 0:48 ` Dan Williams
2021-10-15 16:44 ` Jonathan Cameron
2021-10-15 17:00 ` Dan Williams
2021-10-15 23:30 ` [PATCH v6 " Dan Williams
2021-11-10 17:14 ` Jonathan Cameron
2021-11-10 17:30 ` Ben Widawsky
2021-11-10 17:43 ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 08/10] PCI: Add pci_find_dvsec_capability to find designated VSEC Dan Williams
2021-10-09 16:44 ` [PATCH v3 09/10] cxl/pci: Use pci core's DVSEC functionality Dan Williams
2021-10-11 13:35 ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 10/10] ocxl: " Dan Williams
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