linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Dan Williams <dan.j.williams@intel.com>
To: Ira Weiny <ira.weiny@intel.com>
Cc: linux-cxl@vger.kernel.org, Linux PCI <linux-pci@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH v3 06/10] cxl/pci: Add @base to cxl_register_map
Date: Wed, 13 Oct 2021 15:53:20 -0700	[thread overview]
Message-ID: <CAPcyv4hP5ohs10-xC+h=QOH7yiUXji55ubwVG1XfMA006tjR8A@mail.gmail.com> (raw)
In-Reply-To: <20211010042056.GJ3114988@iweiny-DESK2.sc.intel.com>

On Sat, Oct 9, 2021 at 9:21 PM Ira Weiny <ira.weiny@intel.com> wrote:
>
> On Sat, Oct 09, 2021 at 09:44:29AM -0700, Dan Williams wrote:
> > In addition to carrying @barno, @block_offset, and @reg_type, add @base
> > to keep all map/unmap parameters in one object. The helpers
> > cxl_{map,unmap}_regblock() handle adjusting @base to the @block_offset
> > at map and unmap time.
> >
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > ---
> >  drivers/cxl/cxl.h |    1 +
> >  drivers/cxl/pci.c |   31 ++++++++++++++++---------------
> >  2 files changed, 17 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index a6687e7fd598..7cd16ef144dd 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -140,6 +140,7 @@ struct cxl_device_reg_map {
> >  };
> >
> >  struct cxl_register_map {
> > +     void __iomem *base;
> >       u64 block_offset;
> >       u8 reg_type;
> >       u8 barno;
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 9f006299a0e3..b42407d067ac 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -306,8 +306,7 @@ static int cxl_pci_setup_mailbox(struct cxl_mem *cxlm)
> >       return 0;
> >  }
> >
> > -static void __iomem *cxl_pci_map_regblock(struct pci_dev *pdev,
> > -                                       struct cxl_register_map *map)
> > +static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
> >  {
> >       void __iomem *addr;
> >       int bar = map->barno;
> > @@ -318,24 +317,27 @@ static void __iomem *cxl_pci_map_regblock(struct pci_dev *pdev,
> >       if (pci_resource_len(pdev, bar) < offset) {
> >               dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar,
> >                       &pdev->resource[bar], (unsigned long long)offset);
> > -             return NULL;
> > +             return -ENXIO;
> >       }
> >
> >       addr = pci_iomap(pdev, bar, 0);
> >       if (!addr) {
> >               dev_err(dev, "failed to map registers\n");
> > -             return addr;
> > +             return -ENOMEM;
> >       }
> >
> >       dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
> >               bar, offset);
> >
> > -     return addr;
> > +     map->base = addr + map->block_offset;
> > +     return 0;
> >  }
> >
> > -static void cxl_pci_unmap_regblock(struct pci_dev *pdev, void __iomem *base)
> > +static void cxl_unmap_regblock(struct pci_dev *pdev,
> > +                            struct cxl_register_map *map)
> >  {
> > -     pci_iounmap(pdev, base);
> > +     pci_iounmap(pdev, map->base - map->block_offset);
>
> I know we need to get these in soon.  But I think map->base should be 'base'
> and map->block_offset should be handled in cxl_probe_regs() rather than
> subtract it here..

But why? The goal of the cxl_register_map cleanups is to reduce the
open-coding for details that can just be passed around in a @map
instance. Once cxl_map_regblock() sets up @base there's little reason
to consider the hardware regblock details.

> Either way this is cleaner than what it was.
>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>

Thanks!

  reply	other threads:[~2021-10-13 22:53 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-09 16:43 [PATCH v3 00/10] cxl_pci refactor for reusability Dan Williams
2021-10-09 16:44 ` [PATCH v3 01/10] cxl/pci: Convert register block identifiers to an enum Dan Williams
2021-10-09 16:44 ` [PATCH v3 02/10] cxl/pci: Remove dev_dbg for unknown register blocks Dan Williams
2021-10-09 16:48   ` Joe Perches
2021-10-09 18:04     ` Ben Widawsky
2021-10-09 16:44 ` [PATCH v3 03/10] cxl/pci: Fix NULL vs ERR_PTR confusion Dan Williams
2021-10-10  3:44   ` Ira Weiny
2021-10-15 16:15   ` Jonathan Cameron
2021-10-15 20:16     ` Dan Williams
2021-10-15 21:29   ` [PATCH v6 " Dan Williams
2021-10-09 16:44 ` [PATCH v3 04/10] cxl/pci: Remove pci request/release regions Dan Williams
2021-10-09 16:44 ` [PATCH v3 05/10] cxl/pci: Make more use of cxl_register_map Dan Williams
2021-10-09 19:04   ` kernel test robot
2021-10-09 20:51   ` [PATCH v4 " Dan Williams
2021-10-10  4:03     ` Ira Weiny
2021-10-13 23:53     ` [PATCH v5 " Dan Williams
2021-10-09 16:44 ` [PATCH v3 06/10] cxl/pci: Add @base to cxl_register_map Dan Williams
2021-10-10  4:20   ` Ira Weiny
2021-10-13 22:53     ` Dan Williams [this message]
2021-10-15 16:29       ` Jonathan Cameron
2021-10-15 16:56         ` Dan Williams
2021-10-13 23:57   ` [PATCH v5 " Dan Williams
2021-10-15 21:57     ` [PATCH v6 " Dan Williams
2021-10-18  9:30       ` Jonathan Cameron
2021-10-15 16:27   ` [PATCH v3 " Jonathan Cameron
2021-10-15 16:55     ` Dan Williams
2021-10-18  9:30       ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 07/10] cxl/pci: Split cxl_pci_setup_regs() Dan Williams
2021-10-10  4:44   ` Ira Weiny
2021-10-13 22:45   ` Ben Widawsky
2021-10-13 22:49     ` Dan Williams
2021-10-14  0:12       ` Ben Widawsky
2021-10-14  0:48         ` Dan Williams
2021-10-15 16:44   ` Jonathan Cameron
2021-10-15 17:00     ` Dan Williams
2021-10-15 23:30   ` [PATCH v6 " Dan Williams
2021-11-10 17:14     ` Jonathan Cameron
2021-11-10 17:30       ` Ben Widawsky
2021-11-10 17:43         ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 08/10] PCI: Add pci_find_dvsec_capability to find designated VSEC Dan Williams
2021-10-09 16:44 ` [PATCH v3 09/10] cxl/pci: Use pci core's DVSEC functionality Dan Williams
2021-10-11 13:35   ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 10/10] ocxl: " Dan Williams

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAPcyv4hP5ohs10-xC+h=QOH7yiUXji55ubwVG1XfMA006tjR8A@mail.gmail.com' \
    --to=dan.j.williams@intel.com \
    --cc=hch@lst.de \
    --cc=ira.weiny@intel.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).