From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org
Cc: dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
rafael@kernel.org, bhelgaas@google.com, robert.moore@intel.com
Subject: [PATCH 15/18] cxl: Move identify and partition query from pci probe to port probe
Date: Mon, 06 Feb 2023 13:51:37 -0700 [thread overview]
Message-ID: <167571669593.587790.12939497495344674151.stgit@djiang5-mobl3.local> (raw)
In-Reply-To: <167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local>
Move the enumeration of device capacity to cxl_port_probe() from
cxl_pci_probe(). The size and capacity information should be read
after cxl_await_media_ready() so the data is valid.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/pci.c | 8 --------
drivers/cxl/port.c | 8 ++++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 258004f34281..e35ed250214e 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -484,14 +484,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
- rc = cxl_dev_state_identify(cxlds);
- if (rc)
- return rc;
-
- rc = cxl_mem_create_range_info(cxlds);
- if (rc)
- return rc;
-
cxlmd = devm_cxl_add_memdev(cxlds);
if (IS_ERR(cxlmd))
return PTR_ERR(cxlmd);
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 03380c18fc52..b7a4a1be2945 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -127,6 +127,14 @@ static int cxl_port_probe(struct device *dev)
if (rc)
dev_dbg(dev, "Failed to do QoS calculations\n");
}
+
+ rc = cxl_dev_state_identify(cxlds);
+ if (rc)
+ return rc;
+
+ rc = cxl_mem_create_range_info(cxlds);
+ if (rc)
+ return rc;
}
rc = devm_cxl_enumerate_decoders(cxlhdm);
next prev parent reply other threads:[~2023-02-06 20:51 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:49 [PATCH 00/18] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-02-06 20:49 ` [PATCH 01/18] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-02-09 11:15 ` Jonathan Cameron
2023-02-09 17:28 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 02/18] ACPICA: Export acpi_ut_verify_cdat_checksum() Dave Jiang
2023-02-07 14:19 ` Rafael J. Wysocki
2023-02-07 15:47 ` Dave Jiang
2023-02-09 11:30 ` Jonathan Cameron
2023-02-06 20:49 ` [PATCH 03/18] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-02-09 11:34 ` Jonathan Cameron
2023-02-09 17:31 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 04/18] cxl: Add common helpers for cdat parsing Dave Jiang
2023-02-09 11:58 ` Jonathan Cameron
2023-02-09 22:57 ` Dave Jiang
2023-02-11 10:18 ` Lukas Wunner
2023-02-14 13:17 ` Jonathan Cameron
2023-02-14 20:36 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 05/18] ACPICA: Fix 'struct acpi_cdat_dsmas' spelling mistake Dave Jiang
2023-02-06 22:00 ` Lukas Wunner
2023-02-06 20:50 ` [PATCH 06/18] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-02-09 13:29 ` Jonathan Cameron
2023-02-13 22:55 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 07/18] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-02-09 13:50 ` Jonathan Cameron
2023-02-14 0:24 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 08/18] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-02-09 14:02 ` Jonathan Cameron
2023-02-14 21:07 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 09/18] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-02-09 14:10 ` Jonathan Cameron
2023-02-14 21:29 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 10/18] PCI: Export pcie_get_speed() using the code from sysfs PCI link speed show function Dave Jiang
2023-02-06 22:27 ` Lukas Wunner
2023-02-07 20:29 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 11/18] PCI: Export pcie_get_width() using the code from sysfs PCI link width " Dave Jiang
2023-02-06 22:43 ` Bjorn Helgaas
2023-02-07 20:35 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 12/18] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-02-06 22:39 ` Bjorn Helgaas
2023-02-07 20:51 ` Dave Jiang
2023-02-08 22:15 ` Bjorn Helgaas
2023-02-08 23:56 ` Dave Jiang
2023-02-09 15:10 ` Jonathan Cameron
2023-02-14 22:22 ` Dave Jiang
2023-02-15 12:13 ` Jonathan Cameron
2023-02-22 17:54 ` Dave Jiang
2023-02-09 15:16 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 13/18] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-02-09 15:24 ` Jonathan Cameron
2023-02-14 23:03 ` Dave Jiang
2023-02-15 13:17 ` Jonathan Cameron
2023-02-15 16:38 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 14/18] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` Dave Jiang [this message]
2023-02-09 15:29 ` [PATCH 15/18] cxl: Move identify and partition query from pci probe to port probe Jonathan Cameron
2023-02-06 20:51 ` [PATCH 16/18] cxl: Move reading of CDAT data from device to after media is ready Dave Jiang
2023-02-06 22:17 ` Lukas Wunner
2023-02-07 20:55 ` Dave Jiang
2023-02-09 15:31 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 17/18] cxl: Attach QTG IDs to the DPA ranges for the device Dave Jiang
2023-02-09 15:34 ` Jonathan Cameron
2023-02-06 20:52 ` [PATCH 18/18] cxl: Export sysfs attributes for device QTG IDs Dave Jiang
2023-02-09 15:41 ` Jonathan Cameron
2023-03-23 23:20 ` Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=167571669593.587790.12939497495344674151.stgit@djiang5-mobl3.local \
--to=dave.jiang@intel.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=robert.moore@intel.com \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).