From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <rafael@kernel.org>,
<bhelgaas@google.com>, <robert.moore@intel.com>
Subject: Re: [PATCH 06/18] cxl: Add callback to parse the DSMAS subtables from CDAT
Date: Thu, 9 Feb 2023 13:29:25 +0000 [thread overview]
Message-ID: <20230209132925.00006711@Huawei.com> (raw)
In-Reply-To: <167571661375.587790.16681436923769338643.stgit@djiang5-mobl3.local>
On Mon, 06 Feb 2023 13:50:15 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Provide a callback function to the CDAT parser in order to parse the Device
> Scoped Memory Affinity Structure (DSMAS). Each DSMAS structure contains the
> DPA range and its associated attributes in each entry. See the CDAT
> specification for details.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Hi Dave,
A few minor questions / comments inline,
Jonathan
> ---
> drivers/cxl/core/cdat.c | 25 +++++++++++++++++++++++++
> drivers/cxl/core/port.c | 2 ++
> drivers/cxl/cxl.h | 11 +++++++++++
> drivers/cxl/port.c | 8 ++++++++
> 4 files changed, 46 insertions(+)
>
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index be09c8a690f5..f9a64a0f1ee4 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -96,3 +96,28 @@ int cdat_table_parse_dslbis(void *table, cdat_tbl_entry_handler handler, void *a
> return cdat_table_parse_entries(ACPI_CDAT_TYPE_DSLBIS, header, &proc, 0);
> }
> EXPORT_SYMBOL_NS_GPL(cdat_table_parse_dslbis, CXL);
> +
> +int cxl_dsmas_parse_entry(struct acpi_cdat_header *header, void *arg)
> +{
> + struct cxl_port *port = (struct cxl_port *)arg;
> + struct dsmas_entry *dent;
> + struct acpi_cdat_dsmas *dsmas;
> +
> + if (header->type != ACPI_CDAT_TYPE_DSMAS)
> + return -EINVAL;
> +
> + dent = devm_kzalloc(&port->dev, sizeof(*dent), GFP_KERNEL);
> + if (!dent)
> + return -ENOMEM;
> +
> + dsmas = (struct acpi_cdat_dsmas *)((unsigned long)header + sizeof(*header));
I'd prefer header + 1
> + dent->handle = dsmas->dsmad_handle;
> + dent->dpa_range.start = dsmas->dpa_base_address;
> + dent->dpa_range.end = dsmas->dpa_base_address + dsmas->dpa_length - 1;
> +
> + mutex_lock(&port->cdat.dsmas_lock);
> + list_add_tail(&dent->list, &port->cdat.dsmas_list);
> + mutex_unlock(&port->cdat.dsmas_lock);
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dsmas_parse_entry, CXL);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index fe78daf7e7c8..2b27319cfd42 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -660,6 +660,8 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
> device_set_pm_not_required(dev);
> dev->bus = &cxl_bus_type;
> dev->type = &cxl_port_type;
> + INIT_LIST_HEAD(&port->cdat.dsmas_list);
> + mutex_init(&port->cdat.dsmas_lock);
>
> return port;
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 839a121c1997..1e5e69f08480 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -8,6 +8,7 @@
> #include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/log2.h>
> +#include <linux/list.h>
> #include <linux/io.h>
> #include <linux/acpi.h>
>
> @@ -520,6 +521,8 @@ struct cxl_port {
> struct cxl_cdat {
> void *table;
> size_t length;
> + struct list_head dsmas_list;
> + struct mutex dsmas_lock; /* lock for dsmas_list */
I'm curious, what might race with the dsmas_list changing and hence what is lock for?
> } cdat;
> bool cdat_available;
> };
> @@ -698,6 +701,12 @@ static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
> }
> #endif
>
> +struct dsmas_entry {
> + struct list_head list;
> + struct range dpa_range;
> + u16 handle;
handle is 1 byte in the spec. Why larger here?
> +};
> +
> typedef int (*cdat_tbl_entry_handler)(struct acpi_cdat_header *header, void *arg);
>
> u8 cdat_table_checksum(u8 *buffer, u32 length);
> @@ -706,6 +715,8 @@ int cdat_table_parse_dsmas(void *table, cdat_tbl_entry_handler handler,
> int cdat_table_parse_dslbis(void *table, cdat_tbl_entry_handler handler,
> void *arg);
>
> +int cxl_dsmas_parse_entry(struct acpi_cdat_header *header, void *arg);
> +
> /*
> * Unit test builds overrides this to __weak, find the 'strong' version
> * of these symbols in tools/testing/cxl/.
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 5453771bf330..b1da73e99bab 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -61,6 +61,14 @@ static int cxl_port_probe(struct device *dev)
> if (rc)
> return rc;
>
> + if (port->cdat.table) {
> + rc = cdat_table_parse_dsmas(port->cdat.table,
> + cxl_dsmas_parse_entry,
> + (void *)port);
> + if (rc < 0)
> + dev_dbg(dev, "Failed to parse DSMAS: %d\n", rc);
> + }
> +
> rc = cxl_hdm_decode_init(cxlds, cxlhdm);
> if (rc)
> return rc;
>
>
next prev parent reply other threads:[~2023-02-09 13:29 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:49 [PATCH 00/18] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-02-06 20:49 ` [PATCH 01/18] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-02-09 11:15 ` Jonathan Cameron
2023-02-09 17:28 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 02/18] ACPICA: Export acpi_ut_verify_cdat_checksum() Dave Jiang
2023-02-07 14:19 ` Rafael J. Wysocki
2023-02-07 15:47 ` Dave Jiang
2023-02-09 11:30 ` Jonathan Cameron
2023-02-06 20:49 ` [PATCH 03/18] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-02-09 11:34 ` Jonathan Cameron
2023-02-09 17:31 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 04/18] cxl: Add common helpers for cdat parsing Dave Jiang
2023-02-09 11:58 ` Jonathan Cameron
2023-02-09 22:57 ` Dave Jiang
2023-02-11 10:18 ` Lukas Wunner
2023-02-14 13:17 ` Jonathan Cameron
2023-02-14 20:36 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 05/18] ACPICA: Fix 'struct acpi_cdat_dsmas' spelling mistake Dave Jiang
2023-02-06 22:00 ` Lukas Wunner
2023-02-06 20:50 ` [PATCH 06/18] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-02-09 13:29 ` Jonathan Cameron [this message]
2023-02-13 22:55 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 07/18] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-02-09 13:50 ` Jonathan Cameron
2023-02-14 0:24 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 08/18] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-02-09 14:02 ` Jonathan Cameron
2023-02-14 21:07 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 09/18] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-02-09 14:10 ` Jonathan Cameron
2023-02-14 21:29 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 10/18] PCI: Export pcie_get_speed() using the code from sysfs PCI link speed show function Dave Jiang
2023-02-06 22:27 ` Lukas Wunner
2023-02-07 20:29 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 11/18] PCI: Export pcie_get_width() using the code from sysfs PCI link width " Dave Jiang
2023-02-06 22:43 ` Bjorn Helgaas
2023-02-07 20:35 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 12/18] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-02-06 22:39 ` Bjorn Helgaas
2023-02-07 20:51 ` Dave Jiang
2023-02-08 22:15 ` Bjorn Helgaas
2023-02-08 23:56 ` Dave Jiang
2023-02-09 15:10 ` Jonathan Cameron
2023-02-14 22:22 ` Dave Jiang
2023-02-15 12:13 ` Jonathan Cameron
2023-02-22 17:54 ` Dave Jiang
2023-02-09 15:16 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 13/18] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-02-09 15:24 ` Jonathan Cameron
2023-02-14 23:03 ` Dave Jiang
2023-02-15 13:17 ` Jonathan Cameron
2023-02-15 16:38 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 14/18] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 15/18] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 16/18] cxl: Move reading of CDAT data from device to after media is ready Dave Jiang
2023-02-06 22:17 ` Lukas Wunner
2023-02-07 20:55 ` Dave Jiang
2023-02-09 15:31 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 17/18] cxl: Attach QTG IDs to the DPA ranges for the device Dave Jiang
2023-02-09 15:34 ` Jonathan Cameron
2023-02-06 20:52 ` [PATCH 18/18] cxl: Export sysfs attributes for device QTG IDs Dave Jiang
2023-02-09 15:41 ` Jonathan Cameron
2023-03-23 23:20 ` Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230209132925.00006711@Huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=robert.moore@intel.com \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).