From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, dan.j.williams@intel.com,
ira.weiny@intel.com, vishal.l.verma@intel.com,
alison.schofield@intel.com, rafael@kernel.org,
bhelgaas@google.com, robert.moore@intel.com
Subject: Re: [PATCH 13/18] cxl: Add latency and bandwidth calculations for the CXL path
Date: Tue, 14 Feb 2023 16:03:27 -0700 [thread overview]
Message-ID: <8b2bbf7b-fe3f-c80b-163b-8247e0c47821@intel.com> (raw)
In-Reply-To: <20230209152417.00007f47@Huawei.com>
On 2/9/23 8:24 AM, Jonathan Cameron wrote:
> On Mon, 06 Feb 2023 13:51:19 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> CXL Memory Device SW Guide rev1.0 2.11.2 provides instruction on how to
>> caluclate latency and bandwidth for CXL memory device. Calculate minimum
>
> Spell check your descriptions (I often forget to do this as well!
> )
>> bandwidth and total latency for the path from the CXL device to the root
>> port. The calculates values are stored in the cached DSMAS entries attached
>> to the cxl_port of the CXL device.
>>
>> For example for a device that is directly attached to a host bus:
>> Total Latency = Device Latency (from CDAT) + Dev to Host Bus (HB) Link
>> Latency
>> Min Bandwidth = Link Bandwidth between Host Bus and CXL device
>>
>> For a device that has a switch in between host bus and CXL device:
>> Total Latency = Device (CDAT) Latency + Dev to Switch Link Latency +
>> Switch (CDAT) Latency + Switch to HB Link Latency
>
> For QTG purposes, are we also supposed to take into account HB to
> system interconnect type latency (or maybe nearest CPU?).
> That is likely to be non trivial.
Dan brought this ECN [1] to my attention. We can add this if we can find
a BIOS that implements the ECN. Or should we code a place holder for it
until this is available?
https://lore.kernel.org/linux-cxl/e1a52da9aec90766da5de51b1b839fd95d63a5af.camel@intel.com/
>
>> Min Bandwidth = min(dev to switch bandwidth, switch to HB bandwidth)
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
> Stray sign off.
>
>>
>> The internal latency for a switch can be retrieved from the CDAT of the
>> switch PCI device. However, since there's no easy way to retrieve that
>> right now on Linux, a guesstimated constant is used per switch to simplify
>> the driver code.
>
> I'd like to see that gap closed asap. I think it is fairly obvious how to do
> it, so shouldn't be too hard, just needs a dance to get the DOE for a switch
> port using Lukas' updated handling of DOE mailboxes.
Talked to Lukas and this may not be difficult with his latest changes. I
can take a look. Do we support switch CDAT in QEMU yet?
>
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> drivers/cxl/core/port.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/cxl.h | 9 +++++++
>> drivers/cxl/port.c | 42 +++++++++++++++++++++++++++++++++
>> 3 files changed, 111 insertions(+)
>>
>> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
>> index 2b27319cfd42..aa260361ba7d 100644
>> --- a/drivers/cxl/core/port.c
>> +++ b/drivers/cxl/core/port.c
>> @@ -1899,6 +1899,66 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
>> }
>> EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, CXL);
>>
>> +int cxl_port_get_downstream_qos(struct cxl_port *port, long *bw, long *lat)
>> +{
>> + long total_lat = 0, latency;
>
> Similar to before, not good for readability to hide asignments in a list all on one line.
>
next prev parent reply other threads:[~2023-02-14 23:05 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:49 [PATCH 00/18] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-02-06 20:49 ` [PATCH 01/18] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-02-09 11:15 ` Jonathan Cameron
2023-02-09 17:28 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 02/18] ACPICA: Export acpi_ut_verify_cdat_checksum() Dave Jiang
2023-02-07 14:19 ` Rafael J. Wysocki
2023-02-07 15:47 ` Dave Jiang
2023-02-09 11:30 ` Jonathan Cameron
2023-02-06 20:49 ` [PATCH 03/18] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-02-09 11:34 ` Jonathan Cameron
2023-02-09 17:31 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 04/18] cxl: Add common helpers for cdat parsing Dave Jiang
2023-02-09 11:58 ` Jonathan Cameron
2023-02-09 22:57 ` Dave Jiang
2023-02-11 10:18 ` Lukas Wunner
2023-02-14 13:17 ` Jonathan Cameron
2023-02-14 20:36 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 05/18] ACPICA: Fix 'struct acpi_cdat_dsmas' spelling mistake Dave Jiang
2023-02-06 22:00 ` Lukas Wunner
2023-02-06 20:50 ` [PATCH 06/18] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-02-09 13:29 ` Jonathan Cameron
2023-02-13 22:55 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 07/18] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-02-09 13:50 ` Jonathan Cameron
2023-02-14 0:24 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 08/18] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-02-09 14:02 ` Jonathan Cameron
2023-02-14 21:07 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 09/18] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-02-09 14:10 ` Jonathan Cameron
2023-02-14 21:29 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 10/18] PCI: Export pcie_get_speed() using the code from sysfs PCI link speed show function Dave Jiang
2023-02-06 22:27 ` Lukas Wunner
2023-02-07 20:29 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 11/18] PCI: Export pcie_get_width() using the code from sysfs PCI link width " Dave Jiang
2023-02-06 22:43 ` Bjorn Helgaas
2023-02-07 20:35 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 12/18] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-02-06 22:39 ` Bjorn Helgaas
2023-02-07 20:51 ` Dave Jiang
2023-02-08 22:15 ` Bjorn Helgaas
2023-02-08 23:56 ` Dave Jiang
2023-02-09 15:10 ` Jonathan Cameron
2023-02-14 22:22 ` Dave Jiang
2023-02-15 12:13 ` Jonathan Cameron
2023-02-22 17:54 ` Dave Jiang
2023-02-09 15:16 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 13/18] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-02-09 15:24 ` Jonathan Cameron
2023-02-14 23:03 ` Dave Jiang [this message]
2023-02-15 13:17 ` Jonathan Cameron
2023-02-15 16:38 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 14/18] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 15/18] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 16/18] cxl: Move reading of CDAT data from device to after media is ready Dave Jiang
2023-02-06 22:17 ` Lukas Wunner
2023-02-07 20:55 ` Dave Jiang
2023-02-09 15:31 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 17/18] cxl: Attach QTG IDs to the DPA ranges for the device Dave Jiang
2023-02-09 15:34 ` Jonathan Cameron
2023-02-06 20:52 ` [PATCH 18/18] cxl: Export sysfs attributes for device QTG IDs Dave Jiang
2023-02-09 15:41 ` Jonathan Cameron
2023-03-23 23:20 ` Dan Williams
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