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From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V10 01/15] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Wed, 12 Jun 2019 15:23:25 +0530	[thread overview]
Message-ID: <20190612095339.20118-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190612095339.20118-1-vidyas@nvidia.com>

Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes since [v9]:
* None

Changes since [v8]:
* None

Changes since [v7]:
* None

Changes since [v6]:
* None

Changes since [v5]:
* None

Changes since [v4]:
* None

Changes since [v3]:
* None

Changes since [v2]:
* Updated commit message and description to explicitly mention that defines are
  added only for some of the features and not all.

Changes since [v1]:
* None

 include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 27164769d184..95a1eeb22f49 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -709,7 +709,9 @@
 #define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
 #define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
 #define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL	0x26	/* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL
 
 #define PCI_EXT_CAP_DSN_SIZEOF	12
 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1049,4 +1051,22 @@
 #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
 #define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */
 
+/* Data Link Feature */
+#define PCI_DLF_CAP		0x04	/* Capabilities Register */
+#define  PCI_DLF_LOCAL_DLF_SUP_MASK	0x007fffff  /* Local Data Link Feature Supported */
+#define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS		0x08	/* Status Register */
+#define  PCI_DLF_REMOTE_DLF_SUP_MASK	0x007fffff  /* Remote Data Link Feature Supported */
+#define  PCI_DLF_REMOTE_DLF_SUP_VALID	0x80000000  /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP		0x04	/* Capabilities Register */
+#define PCI_PL_16GT_CTRL	0x08	/* Control Register */
+#define PCI_PL_16GT_STS		0x0c	/* Status Register */
+#define PCI_PL_16GT_LDPM_STS	0x10	/* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS	0x14	/* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS	0x18	/* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD	0x1C	/* Reserved */
+#define PCI_PL_16GT_LE_CTRL	0x20	/* Lane Equalization Control Register */
+
 #endif /* LINUX_PCI_REGS_H */
-- 
2.17.1


  reply	other threads:[~2019-06-12  9:53 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-12  9:53 [PATCH V10 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-06-12  9:53 ` Vidya Sagar [this message]
2019-06-12  9:53 ` [PATCH V10 02/15] PCI: Disable MSI for Tegra194 root port Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 03/15] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-06-18  6:34   ` Jingoo Han
2019-06-12  9:53 ` [PATCH V10 04/15] PCI: dwc: Move config space capability search API Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-06-20  7:22   ` Kishon Vijay Abraham I
2019-06-12  9:53 ` [PATCH V10 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-06-20 10:55   ` Thierry Reding
2019-06-24  7:32     ` Vidya Sagar
2019-06-25  7:33       ` Thierry Reding
2019-06-12  9:53 ` [PATCH V10 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-06-20 11:01   ` Thierry Reding
2019-06-12  9:53 ` [PATCH V10 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-06-20  7:24   ` Kishon Vijay Abraham I
2019-06-20 23:23     ` Dmitry Osipenko
2019-06-22 17:56       ` Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-06-12  9:53 ` [PATCH V10 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-06-20 11:03   ` Thierry Reding

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