From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <hch@infradead.org>,
<alison.schofield@intel.com>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>
Subject: Re: [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder
Date: Wed, 29 Jun 2022 16:56:52 +0100 [thread overview]
Message-ID: <20220629165652.00004ca3@Huawei.com> (raw)
In-Reply-To: <165603883814.551046.17226119386543525679.stgit@dwillia2-xfh>
On Thu, 23 Jun 2022 19:47:18 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> The region provisioning flow will roughly follow a sequence of:
>
> 1/ Allocate DPA to a set of decoders
>
> 2/ Allocate HPA to a region
>
> 3/ Associate decoders with a region and validate that the DPA allocations
> and topologies match the parameters of the region.
>
> For now, this change (step 1) arranges for DPA capacity to be allocated
> and deleted from non-committed decoders based on the decoder's mode /
> partition selection. Capacity is allocated from the lowest DPA in the
> partition and any 'pmem' allocation blocks out all remaining ram
> capacity in its 'skip' setting. DPA allocations are enforced in decoder
> instance order. I.e. decoder N + 1 always starts at a higher DPA than
> instance N, and deleting allocations must proceed from the
> highest-instance allocated decoder to the lowest.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
The error value setting in here might save a few lines, but to me it
is less readable than setting rc in each error path.
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 37 +++++++
> drivers/cxl/core/core.h | 7 +
> drivers/cxl/core/hdm.c | 160 +++++++++++++++++++++++++++++++
> drivers/cxl/core/port.c | 73 ++++++++++++++
> 4 files changed, 275 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 091459216e11..85844f9bc00b 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -171,7 +171,7 @@ Date: May, 2022
> KernelVersion: v5.20
> Contact: linux-cxl@vger.kernel.org
> Description:
> - (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
> + (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
> translates from a host physical address range, to a device local
> address range. Device-local address ranges are further split
> into a 'ram' (volatile memory) range and 'pmem' (persistent
> @@ -180,3 +180,38 @@ Description:
> when a decoder straddles the volatile/persistent partition
> boundary, and 'none' indicates the decoder is not actively
> decoding, or no DPA allocation policy has been set.
> +
> + 'mode' can be written, when the decoder is in the 'disabled'
> + state, with either 'ram' or 'pmem' to set the boundaries for the
> + next allocation.
> +
As before, documentation above this in the file only uses single line break between
entries.
> +
> +What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
> +Date: May, 2022
> +KernelVersion: v5.20
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
> + and its 'dpa_size' attribute is non-zero, this attribute
> + indicates the device physical address (DPA) base address of the
> + allocation.
Why _resource rather than _base or _start?
> +
> +
> +What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
> +Date: May, 2022
> +KernelVersion: v5.20
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
> + translates from a host physical address range, to a device local
> + address range. The range, base address plus length in bytes, of
> + DPA allocated to this decoder is conveyed in these 2 attributes.
> + Allocations can be mutated as long as the decoder is in the
> + disabled state. A write to 'size' releases the previous DPA
'dpa_size' ?
> + allocation and then attempts to allocate from the free capacity
> + in the device partition referred to by 'decoderX.Y/mode'.
> + Allocate and free requests can only be performed on the highest
> + instance number disabled decoder with non-zero size. I.e.
> + allocations are enforced to occur in increasing 'decoderX.Y/id'
> + order and frees are enforced to occur in decreasing
> + 'decoderX.Y/id' order.
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 1a50c0fc399c..47cf0c286fc3 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -17,6 +17,13 @@ int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s);
> void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> resource_size_t length);
>
> +int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
> + enum cxl_decoder_mode mode);
> +int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size);
> +int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
> +resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
> +resource_size_t cxl_dpa_resource(struct cxl_endpoint_decoder *cxled);
> +
> int cxl_memdev_init(void);
> void cxl_memdev_exit(void);
> void cxl_mbox_init(void);
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 8805afe63ebf..ceb4c28abc1b 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -248,6 +248,166 @@ static int cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
> return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled);
> }
>
> +resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled)
> +{
> + resource_size_t size = 0;
> +
> + down_read(&cxl_dpa_rwsem);
> + if (cxled->dpa_res)
> + size = resource_size(cxled->dpa_res);
> + up_read(&cxl_dpa_rwsem);
> +
> + return size;
> +}
> +
> +resource_size_t cxl_dpa_resource(struct cxl_endpoint_decoder *cxled)
Instinct would be to expect this to return the resource, not the start.
Rename?
> +{
> + resource_size_t base = -1;
> +
> + down_read(&cxl_dpa_rwsem);
> + if (cxled->dpa_res)
> + base = cxled->dpa_res->start;
> + up_read(&cxl_dpa_rwsem);
> +
> + return base;
> +}
> +
> +int cxl_dpa_free(struct cxl_endpoint_decoder *cxled)
> +{
> + int rc = -EBUSY;
> + struct device *dev = &cxled->cxld.dev;
> + struct cxl_port *port = to_cxl_port(dev->parent);
> +
> + down_write(&cxl_dpa_rwsem);
> + if (!cxled->dpa_res) {
> + rc = 0;
> + goto out;
> + }
> + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) {
> + dev_dbg(dev, "decoder enabled\n");
I'd prefer explicit setting of rc = -EBUSY in the two
'error' paths to make it really clear when looking at these
that they are treated as errors.
> + goto out;
> + }
> + if (cxled->cxld.id != port->dpa_end) {
> + dev_dbg(dev, "expected decoder%d.%d\n", port->id,
> + port->dpa_end);
> + goto out;
> + }
> + __cxl_dpa_release(cxled, true);
> + rc = 0;
> +out:
> + up_write(&cxl_dpa_rwsem);
> + return rc;
> +}
> +
> +int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
> + enum cxl_decoder_mode mode)
> +{
> + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> + struct device *dev = &cxled->cxld.dev;
> + int rc = -EBUSY;
As above, I'd prefer seeing error set in each error path rther
than it being set in a few locations and having to go look
for which value it currently has. To me having the
error code next to the condition is much easier to follow.
> +
> + switch (mode) {
> + case CXL_DECODER_RAM:
> + case CXL_DECODER_PMEM:
> + break;
> + default:
> + dev_dbg(dev, "unsupported mode: %d\n", mode);
> + return -EINVAL;
> + }
> +
> + down_write(&cxl_dpa_rwsem);
> + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE)
> + goto out;
> + /*
> + * Only allow modes that are supported by the current partition
> + * configuration
> + */
> + rc = -ENXIO;
> + if (mode == CXL_DECODER_PMEM && !resource_size(&cxlds->pmem_res)) {
> + dev_dbg(dev, "no available pmem capacity\n");
> + goto out;
> + }
> + if (mode == CXL_DECODER_RAM && !resource_size(&cxlds->ram_res)) {
> + dev_dbg(dev, "no available ram capacity\n");
> + goto out;
> + }
> +
> + cxled->mode = mode;
> + rc = 0;
> +out:
> + up_write(&cxl_dpa_rwsem);
> +
> + return rc;
> +}
> +
> +int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
> +{
> + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + resource_size_t free_ram_start, free_pmem_start;
> + struct cxl_port *port = cxled_to_port(cxled);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> + struct device *dev = &cxled->cxld.dev;
> + resource_size_t start, avail, skip;
> + struct resource *p, *last;
> + int rc = -EBUSY;
> +
> + down_write(&cxl_dpa_rwsem);
> + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) {
> + dev_dbg(dev, "decoder enabled\n");
> + goto out;
-EBUSY only used in this path, so clearer to me to push that setting down
to in this error path.
> + }
> +
> + for (p = cxlds->ram_res.child, last = NULL; p; p = p->sibling)
> + last = p;
> + if (last)
> + free_ram_start = last->end + 1;
> + else
> + free_ram_start = cxlds->ram_res.start;
> +
> + for (p = cxlds->pmem_res.child, last = NULL; p; p = p->sibling)
> + last = p;
> + if (last)
> + free_pmem_start = last->end + 1;
> + else
> + free_pmem_start = cxlds->pmem_res.start;
> +
> + if (cxled->mode == CXL_DECODER_RAM) {
> + start = free_ram_start;
> + avail = cxlds->ram_res.end - start + 1;
> + skip = 0;
> + } else if (cxled->mode == CXL_DECODER_PMEM) {
> + resource_size_t skip_start, skip_end;
> +
> + start = free_pmem_start;
> + avail = cxlds->pmem_res.end - start + 1;
> + skip_start = free_ram_start;
> + skip_end = start - 1;
> + skip = skip_end - skip_start + 1;
> + } else {
> + dev_dbg(dev, "mode not set\n");
> + rc = -EINVAL;
> + goto out;
> + }
> +
> + if (size > avail) {
> + dev_dbg(dev, "%pa exceeds available %s capacity: %pa\n", &size,
> + cxled->mode == CXL_DECODER_RAM ? "ram" : "pmem",
> + &avail);
> + rc = -ENOSPC;
> + goto out;
> + }
> +
> + rc = __cxl_dpa_reserve(cxled, start, size, skip);
> +out:
> + up_write(&cxl_dpa_rwsem);
> +
> + if (rc)
> + return rc;
> +
> + return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled);
> +}
> +
> static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
> int *target_map, void __iomem *hdm, int which,
> u64 *dpa_base)
>
>
next prev parent reply other threads:[~2022-06-29 15:57 UTC|newest]
Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 2:45 [PATCH 00/46] CXL PMEM Region Provisioning Dan Williams
2022-06-24 2:45 ` [PATCH 01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention Dan Williams
2022-06-28 10:37 ` Jonathan Cameron
[not found] ` <CGME20220629174147uscas1p211384ae262e099484440ef285be26c75@uscas1p2.samsung.com>
2022-06-29 17:41 ` Adam Manzanares
2022-07-09 20:06 ` Dan Williams
2022-07-12 22:11 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 02/46] cxl/port: Keep port->uport valid for the entire life of a port Dan Williams
2022-06-24 3:37 ` Alison Schofield
2022-06-28 11:47 ` Jonathan Cameron
2022-06-28 14:27 ` Dan Williams
[not found] ` <CGME20220629174622uscas1p2236a084ce25771a3ab57c6f006632f35@uscas1p2.samsung.com>
2022-06-29 17:46 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 03/46] cxl/hdm: Use local hdm variable Dan Williams
2022-06-24 3:38 ` Alison Schofield
2022-06-28 15:16 ` Jonathan Cameron
[not found] ` <CGME20220629200312uscas1p292303b9325dcbfe59293f002dc9e6b03@uscas1p2.samsung.com>
2022-06-29 20:03 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 04/46] cxl/core: Rename ->decoder_range ->hpa_range Dan Williams
2022-06-24 3:39 ` Alison Schofield
2022-06-28 15:17 ` Jonathan Cameron
[not found] ` <CGME20220629200652uscas1p2c1da644ea63a5de69e14e046379779b1@uscas1p2.samsung.com>
2022-06-29 20:06 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Dan Williams
2022-06-28 15:24 ` Jonathan Cameron
2022-07-09 23:33 ` Dan Williams
[not found] ` <CGME20220629202117uscas1p2892fb68ae60c4754e2f7d26882a92ae5@uscas1p2.samsung.com>
2022-06-29 20:21 ` Adam Manzanares
2022-07-09 23:38 ` Dan Williams
2022-06-24 2:45 ` [PATCH 06/46] cxl/core: Drop is_cxl_decoder() Dan Williams
2022-06-24 3:48 ` Alison Schofield
2022-06-28 15:25 ` Jonathan Cameron
[not found] ` <CGME20220629203448uscas1p264a7f79a1ed7f9257eefcb3064c7d943@uscas1p2.samsung.com>
2022-06-29 20:34 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 07/46] cxl: Introduce cxl_to_{ways,granularity} Dan Williams
2022-06-28 15:36 ` Jonathan Cameron
2022-07-09 23:52 ` Dan Williams
2022-06-24 2:45 ` [PATCH 08/46] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-06-28 16:12 ` Jonathan Cameron
2022-06-30 10:56 ` Jonathan Cameron
2022-07-10 0:49 ` Dan Williams
2022-07-10 0:33 ` Dan Williams
2022-06-24 2:46 ` [PATCH 09/46] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-06-28 16:43 ` Jonathan Cameron
2022-07-10 2:12 ` Dan Williams
2022-07-19 14:24 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources Dan Williams
2022-06-28 16:49 ` Jonathan Cameron
2022-07-10 2:20 ` Dan Williams
2022-06-28 16:53 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources Dan Williams
2022-06-28 16:55 ` Jonathan Cameron
2022-07-10 2:40 ` Dan Williams
2022-06-24 2:46 ` [PATCH 12/46] cxl/mem: Convert partition-info to resources Dan Williams
2022-06-28 17:02 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 13/46] cxl/hdm: Require all decoders to be enumerated Dan Williams
2022-06-28 17:04 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 14/46] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-06-29 14:43 ` Jonathan Cameron
2022-07-10 3:03 ` Dan Williams
2022-07-19 14:25 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 15/46] cxl/Documentation: List attribute permissions Dan Williams
2022-06-28 3:16 ` Alison Schofield
2022-06-29 14:59 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 16/46] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-06-29 15:28 ` Jonathan Cameron
2022-07-10 3:45 ` Dan Williams
2022-06-24 2:47 ` [PATCH 17/46] cxl/hdm: Track next decoder to allocate Dan Williams
2022-06-29 15:31 ` Jonathan Cameron
2022-07-10 3:55 ` Dan Williams
2022-07-19 14:27 ` Jonathan Cameron
2022-07-10 16:34 ` Dan Williams
2022-06-24 2:47 ` [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-06-29 15:56 ` Jonathan Cameron [this message]
2022-07-10 16:53 ` Dan Williams
2022-06-24 2:47 ` [PATCH 19/46] cxl/debug: Move debugfs init to cxl_core_init() Dan Williams
2022-06-29 15:58 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' Dan Williams
2022-06-29 16:08 ` Jonathan Cameron
2022-07-10 17:09 ` Dan Williams
2022-06-24 2:47 ` [PATCH 21/46] tools/testing/cxl: Move cxl_test resources to the top of memory Dan Williams
2022-06-29 16:11 ` Jonathan Cameron
2022-07-10 17:19 ` Dan Williams
2022-06-24 2:47 ` [PATCH 22/46] tools/testing/cxl: Expand CFMWS windows Dan Williams
2022-06-29 16:14 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 23/46] tools/testing/cxl: Add partition support Dan Williams
2022-06-29 16:20 ` Jonathan Cameron
2022-06-24 2:48 ` [PATCH 24/46] tools/testing/cxl: Fix decoder default state Dan Williams
2022-06-29 16:22 ` Jonathan Cameron
2022-07-10 17:33 ` Dan Williams
2022-06-24 2:48 ` [PATCH 25/46] cxl/port: Record dport in endpoint references Dan Williams
2022-06-29 16:49 ` Jonathan Cameron
2022-07-10 18:40 ` Dan Williams
2022-06-24 4:19 ` [PATCH 26/46] cxl/port: Record parent dport when adding ports Dan Williams
2022-06-29 17:02 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 27/46] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-06-29 17:19 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 28/46] cxl/port: Move dport tracking to an xarray Dan Williams
2022-06-30 9:18 ` Jonathan Cameron
2022-07-10 19:06 ` Dan Williams
2022-06-24 4:19 ` [PATCH 29/46] cxl/port: Cache CXL host bridge data Dan Williams
2022-06-30 9:21 ` Jonathan Cameron
2022-07-10 19:09 ` Dan Williams
2022-06-24 4:19 ` [PATCH 30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-06-30 9:26 ` Jonathan Cameron
2022-07-10 20:40 ` Dan Williams
2022-07-19 14:32 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 31/46] cxl/hdm: Initialize decoder type for memory expander devices Dan Williams
2022-06-30 9:33 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-06-30 9:48 ` Jonathan Cameron
2022-07-10 21:01 ` Dan Williams
2022-06-24 4:19 ` [PATCH 33/46] resource: Introduce alloc_free_mem_region() Dan Williams
2022-06-30 10:35 ` Jonathan Cameron
2022-07-10 21:58 ` Dan Williams
2022-06-24 4:19 ` [PATCH 34/46] cxl/region: Add region creation support Dan Williams
2022-06-30 13:17 ` Jonathan Cameron
2022-07-11 0:08 ` Dan Williams
2022-07-19 14:42 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 35/46] cxl/region: Add a 'uuid' attribute Dan Williams
2022-06-28 10:29 ` Jonathan Cameron
2022-06-28 14:24 ` Dan Williams
2022-06-24 4:19 ` [PATCH 36/46] cxl/region: Add interleave ways attribute Dan Williams
2022-06-30 13:44 ` Jonathan Cameron
2022-07-11 0:32 ` Dan Williams
2022-07-19 14:47 ` Jonathan Cameron
2022-07-19 22:15 ` Dan Williams
2022-07-20 9:59 ` Jonathan Cameron
2022-06-30 13:45 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions Dan Williams
2022-06-30 13:56 ` Jonathan Cameron
2022-07-11 0:47 ` Dan Williams
2022-06-24 4:19 ` [PATCH 38/46] cxl/region: Enable the assignment of endpoint decoders to regions Dan Williams
2022-06-30 14:31 ` Jonathan Cameron
2022-07-11 1:12 ` Dan Williams
2022-06-24 4:19 ` [PATCH 39/46] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-06-30 15:48 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 40/46] cxl/region: Attach endpoint decoders Dan Williams
2022-06-24 18:25 ` Jonathan Cameron
2022-06-24 18:49 ` Dan Williams
2022-06-24 20:51 ` Dan Williams
2022-06-24 23:21 ` Dan Williams
2022-06-30 16:34 ` Jonathan Cameron
2022-07-11 2:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 41/46] cxl/region: Program target lists Dan Williams
2022-06-24 4:19 ` [PATCH 42/46] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-06-30 17:05 ` Jonathan Cameron
2022-07-11 3:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 43/46] cxl/region: Add region driver boiler plate Dan Williams
2022-06-30 17:09 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 44/46] cxl/pmem: Delete unused nvdimm attribute Dan Williams
2022-06-30 17:10 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-06-30 17:14 ` Jonathan Cameron
2022-07-11 19:49 ` Dan Williams
2022-06-24 4:19 ` [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-06-30 17:34 ` Jonathan Cameron
2022-07-11 20:05 ` Dan Williams
2022-06-24 15:13 ` [PATCH 00/46] CXL PMEM Region Provisioning Jonathan Cameron
2022-06-24 15:32 ` Dan Williams
2022-06-28 3:12 ` Alison Schofield
2022-06-28 3:34 ` Dan Williams
2022-07-02 2:26 ` Alison Schofield
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