From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>,
<hch@lst.de>
Subject: Re: [PATCH 42/46] cxl/hdm: Commit decoder state to hardware
Date: Sun, 10 Jul 2022 20:02:20 -0700 [thread overview]
Message-ID: <62cb92bc27397_3535162945b@dwillia2-xfh.notmuch> (raw)
In-Reply-To: <20220630180541.0000259c@Huawei.com>
Jonathan Cameron wrote:
> On Thu, 23 Jun 2022 21:19:46 -0700
> Dan Williams <dan.j.williams@intel.com> wrote:
>
> > After all the soft validation of the region has completed, convey the
> > region configuration to hardware while being careful to commit decoders
> > in specification mandated order. In addition to programming the endpoint
> > decoder base-addres, intereleave ways and granularity, the switch
> > decoder target lists are also established.
> >
> > While the kernel can enforce spec-mandated commit order, it can not
> > enforce spec-mandated reset order. For example, the kernel can't stop
> > someone from removing an endpoint device that is occupying decoderN in a
> > switch decoder where decoderN+1 is also committed. To reset decoderN,
> > decoderN+1 must be torn down first. That "tear down the world"
> > implementation is saved for a follow-on patch.
> >
> > Callback operations are provided for the 'commit' and 'reset'
> > operations. While those callbacks may prove useful for CXL accelerators
> > (Type-2 devices with memory) the primary motivation is to enable a
> > simple way for cxl_test to intercept those operations.
> >
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
>
> Trivial comments only in this one.
>
> Jonathan
>
> > ---
> > Documentation/ABI/testing/sysfs-bus-cxl | 16 ++
> > drivers/cxl/core/hdm.c | 218 ++++++++++++++++++++++++
> > drivers/cxl/core/port.c | 1 +
> > drivers/cxl/core/region.c | 189 ++++++++++++++++++--
> > drivers/cxl/cxl.h | 11 ++
> > tools/testing/cxl/test/cxl.c | 46 +++++
> > 6 files changed, 471 insertions(+), 10 deletions(-)
> >
>
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index 2ee62dde8b23..72f98f1a782c 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
> > @@ -129,6 +129,8 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port)
> > return ERR_PTR(-ENXIO);
> > }
> >
> > + dev_set_drvdata(&port->dev, cxlhdm);
>
> Trivial, but dev == &port->dev I think so you might as well use dev.
Sure.
> This feels like a bit of a hack as it just so happens nothing else is
> in the port drvdata. Maybe it's better to add a pointer from
> port to cxlhdm?
It's only valid while the port is attached to the cxl_port driver which
sets it apart from other port data.
>
> > +
> > return cxlhdm;
> > }
> > EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_hdm, CXL);
> > @@ -444,6 +446,213 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
> > return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled);
> > }
> >
>
> > +static int cxl_decoder_commit(struct cxl_decoder *cxld)
> > +{
> > + struct cxl_port *port = to_cxl_port(cxld->dev.parent);
> > + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
> > + void __iomem *hdm = cxlhdm->regs.hdm_decoder;
> > + int id = cxld->id, rc;
> > + u64 base, size;
> > + u32 ctrl;
> > +
> > + if (cxld->flags & CXL_DECODER_F_ENABLE)
> > + return 0;
> > +
> > + if (port->commit_end + 1 != id) {
> > + dev_dbg(&port->dev,
> > + "%s: out of order commit, expected decoder%d.%d\n",
> > + dev_name(&cxld->dev), port->id, port->commit_end + 1);
> > + return -EBUSY;
> > + }
> > +
> > + down_read(&cxl_dpa_rwsem);
> > + /* common decoder settings */
> > + ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id));
> > + cxld_set_interleave(cxld, &ctrl);
> > + cxld_set_type(cxld, &ctrl);
> > + cxld_set_hpa(cxld, &base, &size);
> > +
> > + writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
> > + writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
> > + writel(upper_32_bits(size), hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id));
> > + writel(lower_32_bits(size), hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
> > +
> > + if (is_switch_decoder(&cxld->dev)) {
> > + struct cxl_switch_decoder *cxlsd =
> > + to_cxl_switch_decoder(&cxld->dev);
> > + void __iomem *tl_hi = hdm + CXL_HDM_DECODER0_TL_HIGH(id);
> > + void __iomem *tl_lo = hdm + CXL_HDM_DECODER0_TL_LOW(id);
> > + u64 targets;
> > +
> > + rc = cxlsd_set_targets(cxlsd, &targets);
> > + if (rc) {
> > + dev_dbg(&port->dev, "%s: target configuration error\n",
> > + dev_name(&cxld->dev));
> > + goto err;
> > + }
> > +
> > + writel(upper_32_bits(targets), tl_hi);
> > + writel(lower_32_bits(targets), tl_lo);
> > + } else {
> > + struct cxl_endpoint_decoder *cxled =
> > + to_cxl_endpoint_decoder(&cxld->dev);
> > + void __iomem *sk_hi = hdm + CXL_HDM_DECODER0_SKIP_HIGH(id);
> > + void __iomem *sk_lo = hdm + CXL_HDM_DECODER0_SKIP_LOW(id);
> > +
> > + writel(upper_32_bits(cxled->skip), sk_hi);
> > + writel(lower_32_bits(cxled->skip), sk_lo);
> > + }
> > +
> > + writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
> > + up_read(&cxl_dpa_rwsem);
> > +
> > + port->commit_end++;
>
> Obviously doesn't matter as resetting on error, but
> feels like the increment of commit_end++ should only follow
> succesful commit / await_commit();
Then it would need a special ->reset() flavor to do everything but the
commit_end management. As long as cxl_region_rwsem is held over the
combination, nothing can sneak in and observe the intermediate state.
> > + rc = cxld_await_commit(hdm, cxld->id);
> > +err:
> > + if (rc) {
> > + dev_dbg(&port->dev, "%s: error %d committing decoder\n",
> > + dev_name(&cxld->dev), rc);
> > + cxld->reset(cxld);
> > + return rc;
> > + }
> > + cxld->flags |= CXL_DECODER_F_ENABLE;
> > +
> > + return 0;
> > +}
> > +
> > +static int cxl_decoder_reset(struct cxl_decoder *cxld)
> > +{
> > + struct cxl_port *port = to_cxl_port(cxld->dev.parent);
> > + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
> > + void __iomem *hdm = cxlhdm->regs.hdm_decoder;
> > + int id = cxld->id;
> > + u32 ctrl;
> > +
> > + if ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)
>
> extra space after ==
got it.
>
> > + return 0;
> > +
>
> ...
>
>
> >
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index 7034300e72b2..eee1615d2319 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -630,6 +630,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
> > port->component_reg_phys = component_reg_phys;
> > ida_init(&port->decoder_ida);
> > port->dpa_end = -1;
> > + port->commit_end = -1;
> > xa_init(&port->dports);
> > xa_init(&port->endpoints);
> > xa_init(&port->regions);
> > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> > index 071b8cafe2bb..b90160c4f975 100644
> > --- a/drivers/cxl/core/region.c
> > +++ b/drivers/cxl/core/region.c
> > @@ -112,6 +112,168 @@ static ssize_t uuid_store(struct device *dev, struct device_attribute *attr,
> > }
> > static DEVICE_ATTR_RW(uuid);
>
> ...
>
>
> > +static int cxl_region_decode_reset(struct cxl_region *cxlr, int count)
> > +{
> > + struct cxl_region_params *p = &cxlr->params;
> > + int i;
> > +
> > + for (i = count - 1; i >= 0; i--) {
> > + struct cxl_endpoint_decoder *cxled = p->targets[i];
> > + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> > + struct cxl_port *iter = cxled_to_port(cxled);
> > + struct cxl_ep *ep;
> > + int rc;
> > +
> > + while (!is_cxl_root(to_cxl_port(iter->dev.parent)))
> > + iter = to_cxl_port(iter->dev.parent);
> > +
> > + for (ep = cxl_ep_load(iter, cxlmd); iter;
> > + iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
> > + struct cxl_region_ref *cxl_rr;
> > + struct cxl_decoder *cxld;
> > +
> > + cxl_rr = cxl_rr_load(iter, cxlr);
> > + cxld = cxl_rr->decoder;
> > + rc = cxld->reset(cxld);
> > + if (rc)
> > + return rc;
> > + }
> > +
> > + rc = cxled->cxld.reset(&cxled->cxld);
> > + if (rc)
> > + return rc;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int cxl_region_decode_commit(struct cxl_region *cxlr)
> > +{
> > + struct cxl_region_params *p = &cxlr->params;
> > + int i, rc;
> > +
> > + for (i = 0; i < p->nr_targets; i++) {
> > + struct cxl_endpoint_decoder *cxled = p->targets[i];
> > + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> > + struct cxl_region_ref *cxl_rr;
> > + struct cxl_decoder *cxld;
> > + struct cxl_port *iter;
> > + struct cxl_ep *ep;
> > +
> > + /* commit bottom up */
> > + for (iter = cxled_to_port(cxled); !is_cxl_root(iter);
> > + iter = to_cxl_port(iter->dev.parent)) {
> > + cxl_rr = cxl_rr_load(iter, cxlr);
> > + cxld = cxl_rr->decoder;
> > + rc = cxld->commit(cxld);
> > + if (rc)
> > + break;
> > + }
> > +
> > + if (is_cxl_root(iter))
> > + continue;
> > +
> > + /* teardown top down */
>
> Comment on why we are tearing down. I guess because previous
> somehow didn't end up at the root?
Correct, one of those commits in the loop above failed causing it to
break out. Added a comment.
>
> > + for (ep = cxl_ep_load(iter, cxlmd); ep && iter;
> > + iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
> > + cxl_rr = cxl_rr_load(iter, cxlr);
> > + cxld = cxl_rr->decoder;
> > + cxld->reset(cxld);
> > + }
> > +
> > + cxled->cxld.reset(&cxled->cxld);
> > + if (i == 0)
> > + return rc;
> > + break;
> > + }
> > +
> > + if (i >= p->nr_targets)
> > + return 0;
> > +
> > + /* undo the targets that were successfully committed */
> > + cxl_region_decode_reset(cxlr, i);
> > + return rc;
> > +}
> > +
> > +static ssize_t commit_store(struct device *dev, struct device_attribute *attr,
> > + const char *buf, size_t len)
> > +{
> > + struct cxl_region *cxlr = to_cxl_region(dev);
> > + struct cxl_region_params *p = &cxlr->params;
> > + bool commit;
> > + ssize_t rc;
> > +
> > + rc = kstrtobool(buf, &commit);
> > + if (rc)
> > + return rc;
> > +
> > + rc = down_write_killable(&cxl_region_rwsem);
> > + if (rc)
> > + return rc;
> > +
> > + /* Already in the requested state? */
> > + if (commit && p->state >= CXL_CONFIG_COMMIT)
> > + goto out;
> > + if (!commit && p->state < CXL_CONFIG_COMMIT)
> > + goto out;
> > +
> > + /* Not ready to commit? */
> > + if (commit && p->state < CXL_CONFIG_ACTIVE) {
> > + rc = -ENXIO;
> > + goto out;
> > + }
> > +
> > + if (commit)
> > + rc = cxl_region_decode_commit(cxlr);
> > + else {
> > + p->state = CXL_CONFIG_RESET_PENDING;
> > + up_write(&cxl_region_rwsem);
> > + device_release_driver(&cxlr->dev);
> > + down_write(&cxl_region_rwsem);
> > +
> > + if (p->state == CXL_CONFIG_RESET_PENDING)
>
> What path results in that changing in last few lines?
> Perhaps a comment if there is something we need to protect against?
The lock needs to be dropped before calling device_release_driver(),
after reacquiring the lock need to revalidate that the reset is still
pending. Added a comment.
>
>
> > + rc = cxl_region_decode_reset(cxlr, p->interleave_ways);
> > + }
> > +
> > + if (rc)
> > + goto out;
> > +
> > + if (commit)
> > + p->state = CXL_CONFIG_COMMIT;
> > + else if (p->state == CXL_CONFIG_RESET_PENDING)
> > + p->state = CXL_CONFIG_ACTIVE;
> > +
> > +out:
> > + up_write(&cxl_region_rwsem);
> > +
> > + if (rc)
> > + return rc;
> > + return len;
> > +}
>
>
> ...
>
>
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index a93d7c4efd1a..fc14f6805f2c 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -54,6 +54,7 @@
> > #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
> > #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
> > #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
> > +#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
> > #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12)
> > #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
> > #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
> > @@ -257,6 +258,8 @@ enum cxl_decoder_type {
> > * @target_type: accelerator vs expander (type2 vs type3) selector
> > * @region: currently assigned region for this decoder
> > * @flags: memory type capabilities and locking
> > + * @commit: device/decoder-type specific callback to commit settings to hw
> > + * @commit: device/decoder-type specific callback to reset hw settings
>
> @reset
Yup.
>
> > */
> > struct cxl_decoder {
> > struct device dev;
> > @@ -267,6 +270,8 @@ struct cxl_decoder {
> > enum cxl_decoder_type target_type;
> > struct cxl_region *region;
> > unsigned long flags;
> > + int (*commit)(struct cxl_decoder *cxld);
> > + int (*reset)(struct cxl_decoder *cxld);
> > };
> >
>
>
> > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> > index 51d517fa62ee..94653201631c 100644
> > --- a/tools/testing/cxl/test/cxl.c
> > +++ b/tools/testing/cxl/test/cxl.c
> > @@ -429,6 +429,50 @@ static int map_targets(struct device *dev, void *data)
> > return 0;
> > }
> >
>
> ...
>
> > +static int mock_decoder_reset(struct cxl_decoder *cxld)
> > +{
> > + struct cxl_port *port = to_cxl_port(cxld->dev.parent);
> > + int id = cxld->id;
> > +
> > + if ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)
>
> bonus space after ==
copy-pasta plus missed clang-format. Fixed.
next prev parent reply other threads:[~2022-07-11 3:02 UTC|newest]
Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 2:45 [PATCH 00/46] CXL PMEM Region Provisioning Dan Williams
2022-06-24 2:45 ` [PATCH 01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention Dan Williams
2022-06-28 10:37 ` Jonathan Cameron
[not found] ` <CGME20220629174147uscas1p211384ae262e099484440ef285be26c75@uscas1p2.samsung.com>
2022-06-29 17:41 ` Adam Manzanares
2022-07-09 20:06 ` Dan Williams
2022-07-12 22:11 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 02/46] cxl/port: Keep port->uport valid for the entire life of a port Dan Williams
2022-06-24 3:37 ` Alison Schofield
2022-06-28 11:47 ` Jonathan Cameron
2022-06-28 14:27 ` Dan Williams
[not found] ` <CGME20220629174622uscas1p2236a084ce25771a3ab57c6f006632f35@uscas1p2.samsung.com>
2022-06-29 17:46 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 03/46] cxl/hdm: Use local hdm variable Dan Williams
2022-06-24 3:38 ` Alison Schofield
2022-06-28 15:16 ` Jonathan Cameron
[not found] ` <CGME20220629200312uscas1p292303b9325dcbfe59293f002dc9e6b03@uscas1p2.samsung.com>
2022-06-29 20:03 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 04/46] cxl/core: Rename ->decoder_range ->hpa_range Dan Williams
2022-06-24 3:39 ` Alison Schofield
2022-06-28 15:17 ` Jonathan Cameron
[not found] ` <CGME20220629200652uscas1p2c1da644ea63a5de69e14e046379779b1@uscas1p2.samsung.com>
2022-06-29 20:06 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Dan Williams
2022-06-28 15:24 ` Jonathan Cameron
2022-07-09 23:33 ` Dan Williams
[not found] ` <CGME20220629202117uscas1p2892fb68ae60c4754e2f7d26882a92ae5@uscas1p2.samsung.com>
2022-06-29 20:21 ` Adam Manzanares
2022-07-09 23:38 ` Dan Williams
2022-06-24 2:45 ` [PATCH 06/46] cxl/core: Drop is_cxl_decoder() Dan Williams
2022-06-24 3:48 ` Alison Schofield
2022-06-28 15:25 ` Jonathan Cameron
[not found] ` <CGME20220629203448uscas1p264a7f79a1ed7f9257eefcb3064c7d943@uscas1p2.samsung.com>
2022-06-29 20:34 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 07/46] cxl: Introduce cxl_to_{ways,granularity} Dan Williams
2022-06-28 15:36 ` Jonathan Cameron
2022-07-09 23:52 ` Dan Williams
2022-06-24 2:45 ` [PATCH 08/46] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-06-28 16:12 ` Jonathan Cameron
2022-06-30 10:56 ` Jonathan Cameron
2022-07-10 0:49 ` Dan Williams
2022-07-10 0:33 ` Dan Williams
2022-06-24 2:46 ` [PATCH 09/46] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-06-28 16:43 ` Jonathan Cameron
2022-07-10 2:12 ` Dan Williams
2022-07-19 14:24 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources Dan Williams
2022-06-28 16:49 ` Jonathan Cameron
2022-07-10 2:20 ` Dan Williams
2022-06-28 16:53 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources Dan Williams
2022-06-28 16:55 ` Jonathan Cameron
2022-07-10 2:40 ` Dan Williams
2022-06-24 2:46 ` [PATCH 12/46] cxl/mem: Convert partition-info to resources Dan Williams
2022-06-28 17:02 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 13/46] cxl/hdm: Require all decoders to be enumerated Dan Williams
2022-06-28 17:04 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 14/46] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-06-29 14:43 ` Jonathan Cameron
2022-07-10 3:03 ` Dan Williams
2022-07-19 14:25 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 15/46] cxl/Documentation: List attribute permissions Dan Williams
2022-06-28 3:16 ` Alison Schofield
2022-06-29 14:59 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 16/46] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-06-29 15:28 ` Jonathan Cameron
2022-07-10 3:45 ` Dan Williams
2022-06-24 2:47 ` [PATCH 17/46] cxl/hdm: Track next decoder to allocate Dan Williams
2022-06-29 15:31 ` Jonathan Cameron
2022-07-10 3:55 ` Dan Williams
2022-07-19 14:27 ` Jonathan Cameron
2022-07-10 16:34 ` Dan Williams
2022-06-24 2:47 ` [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-06-29 15:56 ` Jonathan Cameron
2022-07-10 16:53 ` Dan Williams
2022-06-24 2:47 ` [PATCH 19/46] cxl/debug: Move debugfs init to cxl_core_init() Dan Williams
2022-06-29 15:58 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' Dan Williams
2022-06-29 16:08 ` Jonathan Cameron
2022-07-10 17:09 ` Dan Williams
2022-06-24 2:47 ` [PATCH 21/46] tools/testing/cxl: Move cxl_test resources to the top of memory Dan Williams
2022-06-29 16:11 ` Jonathan Cameron
2022-07-10 17:19 ` Dan Williams
2022-06-24 2:47 ` [PATCH 22/46] tools/testing/cxl: Expand CFMWS windows Dan Williams
2022-06-29 16:14 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 23/46] tools/testing/cxl: Add partition support Dan Williams
2022-06-29 16:20 ` Jonathan Cameron
2022-06-24 2:48 ` [PATCH 24/46] tools/testing/cxl: Fix decoder default state Dan Williams
2022-06-29 16:22 ` Jonathan Cameron
2022-07-10 17:33 ` Dan Williams
2022-06-24 2:48 ` [PATCH 25/46] cxl/port: Record dport in endpoint references Dan Williams
2022-06-29 16:49 ` Jonathan Cameron
2022-07-10 18:40 ` Dan Williams
2022-06-24 4:19 ` [PATCH 26/46] cxl/port: Record parent dport when adding ports Dan Williams
2022-06-29 17:02 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 27/46] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-06-29 17:19 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 28/46] cxl/port: Move dport tracking to an xarray Dan Williams
2022-06-30 9:18 ` Jonathan Cameron
2022-07-10 19:06 ` Dan Williams
2022-06-24 4:19 ` [PATCH 29/46] cxl/port: Cache CXL host bridge data Dan Williams
2022-06-30 9:21 ` Jonathan Cameron
2022-07-10 19:09 ` Dan Williams
2022-06-24 4:19 ` [PATCH 30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-06-30 9:26 ` Jonathan Cameron
2022-07-10 20:40 ` Dan Williams
2022-07-19 14:32 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 31/46] cxl/hdm: Initialize decoder type for memory expander devices Dan Williams
2022-06-30 9:33 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-06-30 9:48 ` Jonathan Cameron
2022-07-10 21:01 ` Dan Williams
2022-06-24 4:19 ` [PATCH 33/46] resource: Introduce alloc_free_mem_region() Dan Williams
2022-06-30 10:35 ` Jonathan Cameron
2022-07-10 21:58 ` Dan Williams
2022-06-24 4:19 ` [PATCH 34/46] cxl/region: Add region creation support Dan Williams
2022-06-30 13:17 ` Jonathan Cameron
2022-07-11 0:08 ` Dan Williams
2022-07-19 14:42 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 35/46] cxl/region: Add a 'uuid' attribute Dan Williams
2022-06-28 10:29 ` Jonathan Cameron
2022-06-28 14:24 ` Dan Williams
2022-06-24 4:19 ` [PATCH 36/46] cxl/region: Add interleave ways attribute Dan Williams
2022-06-30 13:44 ` Jonathan Cameron
2022-07-11 0:32 ` Dan Williams
2022-07-19 14:47 ` Jonathan Cameron
2022-07-19 22:15 ` Dan Williams
2022-07-20 9:59 ` Jonathan Cameron
2022-06-30 13:45 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions Dan Williams
2022-06-30 13:56 ` Jonathan Cameron
2022-07-11 0:47 ` Dan Williams
2022-06-24 4:19 ` [PATCH 38/46] cxl/region: Enable the assignment of endpoint decoders to regions Dan Williams
2022-06-30 14:31 ` Jonathan Cameron
2022-07-11 1:12 ` Dan Williams
2022-06-24 4:19 ` [PATCH 39/46] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-06-30 15:48 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 40/46] cxl/region: Attach endpoint decoders Dan Williams
2022-06-24 18:25 ` Jonathan Cameron
2022-06-24 18:49 ` Dan Williams
2022-06-24 20:51 ` Dan Williams
2022-06-24 23:21 ` Dan Williams
2022-06-30 16:34 ` Jonathan Cameron
2022-07-11 2:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 41/46] cxl/region: Program target lists Dan Williams
2022-06-24 4:19 ` [PATCH 42/46] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-06-30 17:05 ` Jonathan Cameron
2022-07-11 3:02 ` Dan Williams [this message]
2022-06-24 4:19 ` [PATCH 43/46] cxl/region: Add region driver boiler plate Dan Williams
2022-06-30 17:09 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 44/46] cxl/pmem: Delete unused nvdimm attribute Dan Williams
2022-06-30 17:10 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-06-30 17:14 ` Jonathan Cameron
2022-07-11 19:49 ` Dan Williams
2022-06-24 4:19 ` [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-06-30 17:34 ` Jonathan Cameron
2022-07-11 20:05 ` Dan Williams
2022-06-24 15:13 ` [PATCH 00/46] CXL PMEM Region Provisioning Jonathan Cameron
2022-06-24 15:32 ` Dan Williams
2022-06-28 3:12 ` Alison Schofield
2022-06-28 3:34 ` Dan Williams
2022-07-02 2:26 ` Alison Schofield
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