From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <nvdimm@lists.linux.dev>,
<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>,
<hch@lst.de>
Subject: Re: [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints
Date: Thu, 30 Jun 2022 10:48:20 +0100 [thread overview]
Message-ID: <20220630104820.00006d6e@Huawei.com> (raw)
In-Reply-To: <20220624041950.559155-7-dan.j.williams@intel.com>
On Thu, 23 Jun 2022 21:19:36 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> The port scanning algorithm in devm_cxl_enumerate_ports() walks up the
> topology and adds cxl_port objects starting from the root down to the
> endpoint. When those ports are initially created they know all their
> dports, but they do not know the downstream cxl_port instance that
> represents the next descendant in the topology. Rework create_endpoint()
> into devm_cxl_add_endpoint() that enumerates the downstream cxl_port
> topology into each port's 'struct cxl_ep' record for each endpoint it
> that the port is an ancestor.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
I'm doing my normal moaning about tidying up in a patch that makes
a more serious change. Ideally pull that out, but meh if it's a real pain
I can live with it as long as you call it out in the patch description.
With that
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/port.c | 41 +++++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 7 ++++++-
> drivers/cxl/mem.c | 30 +-----------------------------
> 3 files changed, 48 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 08a380d20cf1..2e56903399c2 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1089,6 +1089,47 @@ static struct cxl_ep *cxl_ep_load(struct cxl_port *port,
> return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
> }
>
> +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
> + struct cxl_dport *parent_dport)
> +{
> + struct cxl_port *parent_port = parent_dport->port;
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> + struct cxl_port *endpoint, *iter, *down;
> + int rc;
> +
> + /*
> + * Now that the path to the root is established record all the
> + * intervening ports in the chain.
> + */
> + for (iter = parent_port, down = NULL; !is_cxl_root(iter);
> + down = iter, iter = to_cxl_port(iter->dev.parent)) {
> + struct cxl_ep *ep;
> +
> + ep = cxl_ep_load(iter, cxlmd);
> + ep->next = down;
> + }
> +
> + endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
> + cxlds->component_reg_phys, parent_dport);
> + if (IS_ERR(endpoint))
> + return PTR_ERR(endpoint);
> +
> + dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
> +
> + rc = cxl_endpoint_autoremove(cxlmd, endpoint);
> + if (rc)
> + return rc;
> +
> + if (!endpoint->dev.driver) {
> + dev_err(&cxlmd->dev, "%s failed probe\n",
> + dev_name(&endpoint->dev));
> + return -ENXIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint, CXL);
> +
> static void cxl_detach_ep(void *data)
> {
> struct cxl_memdev *cxlmd = data;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 0211cf0d3574..f761cf78cc05 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -371,11 +371,14 @@ struct cxl_dport {
> /**
> * struct cxl_ep - track an endpoint's interest in a port
> * @ep: device that hosts a generic CXL endpoint (expander or accelerator)
> - * @dport: which dport routes to this endpoint on this port
> + * @dport: which dport routes to this endpoint on @port
fix is good, but shouldn't be in this patch really..
> + * @next: cxl switch port across the link attached to @dport NULL if
> + * attached to an endpoint
> */
> struct cxl_ep {
> struct device *ep;
> struct cxl_dport *dport;
> + struct cxl_port *next;
> };
>
> /*
> @@ -398,6 +401,8 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
> struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
> resource_size_t component_reg_phys,
> struct cxl_dport *parent_dport);
> +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
> + struct cxl_dport *parent_dport);
> struct cxl_port *find_cxl_root(struct device *dev);
> int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
> int cxl_bus_rescan(void);
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 2786d3402c9e..64ccf053d32c 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -25,34 +25,6 @@
> * in higher level operations.
> */
>
> -static int create_endpoint(struct cxl_memdev *cxlmd,
> - struct cxl_dport *parent_dport)
> -{
> - struct cxl_port *parent_port = parent_dport->port;
> - struct cxl_dev_state *cxlds = cxlmd->cxlds;
> - struct cxl_port *endpoint;
> - int rc;
> -
> - endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
> - cxlds->component_reg_phys, parent_dport);
> - if (IS_ERR(endpoint))
> - return PTR_ERR(endpoint);
> -
> - dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
> -
> - rc = cxl_endpoint_autoremove(cxlmd, endpoint);
> - if (rc)
> - return rc;
> -
> - if (!endpoint->dev.driver) {
> - dev_err(&cxlmd->dev, "%s failed probe\n",
> - dev_name(&endpoint->dev));
> - return -ENXIO;
> - }
> -
> - return 0;
> -}
> -
> static void enable_suspend(void *data)
> {
> cxl_mem_active_dec();
> @@ -116,7 +88,7 @@ static int cxl_mem_probe(struct device *dev)
> goto unlock;
> }
>
> - rc = create_endpoint(cxlmd, dport);
> + rc = devm_cxl_add_endpoint(cxlmd, dport);
> unlock:
> device_unlock(&parent_port->dev);
> put_device(&parent_port->dev);
next prev parent reply other threads:[~2022-06-30 9:48 UTC|newest]
Thread overview: 157+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 2:45 [PATCH 00/46] CXL PMEM Region Provisioning Dan Williams
2022-06-24 2:45 ` [PATCH 01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention Dan Williams
2022-06-28 10:37 ` Jonathan Cameron
[not found] ` <CGME20220629174147uscas1p211384ae262e099484440ef285be26c75@uscas1p2.samsung.com>
2022-06-29 17:41 ` Adam Manzanares
2022-07-09 20:06 ` Dan Williams
2022-07-12 22:11 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 02/46] cxl/port: Keep port->uport valid for the entire life of a port Dan Williams
2022-06-24 3:37 ` Alison Schofield
2022-06-28 11:47 ` Jonathan Cameron
2022-06-28 14:27 ` Dan Williams
[not found] ` <CGME20220629174622uscas1p2236a084ce25771a3ab57c6f006632f35@uscas1p2.samsung.com>
2022-06-29 17:46 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 03/46] cxl/hdm: Use local hdm variable Dan Williams
2022-06-24 3:38 ` Alison Schofield
2022-06-28 15:16 ` Jonathan Cameron
[not found] ` <CGME20220629200312uscas1p292303b9325dcbfe59293f002dc9e6b03@uscas1p2.samsung.com>
2022-06-29 20:03 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 04/46] cxl/core: Rename ->decoder_range ->hpa_range Dan Williams
2022-06-24 3:39 ` Alison Schofield
2022-06-28 15:17 ` Jonathan Cameron
[not found] ` <CGME20220629200652uscas1p2c1da644ea63a5de69e14e046379779b1@uscas1p2.samsung.com>
2022-06-29 20:06 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Dan Williams
2022-06-28 15:24 ` Jonathan Cameron
2022-07-09 23:33 ` Dan Williams
[not found] ` <CGME20220629202117uscas1p2892fb68ae60c4754e2f7d26882a92ae5@uscas1p2.samsung.com>
2022-06-29 20:21 ` Adam Manzanares
2022-07-09 23:38 ` Dan Williams
2022-06-24 2:45 ` [PATCH 06/46] cxl/core: Drop is_cxl_decoder() Dan Williams
2022-06-24 3:48 ` Alison Schofield
2022-06-28 15:25 ` Jonathan Cameron
[not found] ` <CGME20220629203448uscas1p264a7f79a1ed7f9257eefcb3064c7d943@uscas1p2.samsung.com>
2022-06-29 20:34 ` Adam Manzanares
2022-06-24 2:45 ` [PATCH 07/46] cxl: Introduce cxl_to_{ways,granularity} Dan Williams
2022-06-28 15:36 ` Jonathan Cameron
2022-07-09 23:52 ` Dan Williams
2022-06-24 2:45 ` [PATCH 08/46] cxl/core: Define a 'struct cxl_switch_decoder' Dan Williams
2022-06-28 16:12 ` Jonathan Cameron
2022-06-30 10:56 ` Jonathan Cameron
2022-07-10 0:49 ` Dan Williams
2022-07-10 0:33 ` Dan Williams
2022-06-24 2:46 ` [PATCH 09/46] cxl/acpi: Track CXL resources in iomem_resource Dan Williams
2022-06-28 16:43 ` Jonathan Cameron
2022-07-10 2:12 ` Dan Williams
2022-07-19 14:24 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources Dan Williams
2022-06-28 16:49 ` Jonathan Cameron
2022-07-10 2:20 ` Dan Williams
2022-06-28 16:53 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources Dan Williams
2022-06-28 16:55 ` Jonathan Cameron
2022-07-10 2:40 ` Dan Williams
2022-06-24 2:46 ` [PATCH 12/46] cxl/mem: Convert partition-info to resources Dan Williams
2022-06-28 17:02 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 13/46] cxl/hdm: Require all decoders to be enumerated Dan Williams
2022-06-28 17:04 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 14/46] cxl/hdm: Enumerate allocated DPA Dan Williams
2022-06-29 14:43 ` Jonathan Cameron
2022-07-10 3:03 ` Dan Williams
2022-07-19 14:25 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 15/46] cxl/Documentation: List attribute permissions Dan Williams
2022-06-28 3:16 ` Alison Schofield
2022-06-29 14:59 ` Jonathan Cameron
2022-06-24 2:46 ` [PATCH 16/46] cxl/hdm: Add 'mode' attribute to decoder objects Dan Williams
2022-06-29 15:28 ` Jonathan Cameron
2022-07-10 3:45 ` Dan Williams
2022-06-24 2:47 ` [PATCH 17/46] cxl/hdm: Track next decoder to allocate Dan Williams
2022-06-29 15:31 ` Jonathan Cameron
2022-07-10 3:55 ` Dan Williams
2022-07-19 14:27 ` Jonathan Cameron
2022-07-10 16:34 ` Dan Williams
2022-06-24 2:47 ` [PATCH 18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder Dan Williams
2022-06-29 15:56 ` Jonathan Cameron
2022-07-10 16:53 ` Dan Williams
2022-06-24 2:47 ` [PATCH 19/46] cxl/debug: Move debugfs init to cxl_core_init() Dan Williams
2022-06-29 15:58 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' Dan Williams
2022-06-29 16:08 ` Jonathan Cameron
2022-07-10 17:09 ` Dan Williams
2022-06-24 2:47 ` [PATCH 21/46] tools/testing/cxl: Move cxl_test resources to the top of memory Dan Williams
2022-06-29 16:11 ` Jonathan Cameron
2022-07-10 17:19 ` Dan Williams
2022-06-24 2:47 ` [PATCH 22/46] tools/testing/cxl: Expand CFMWS windows Dan Williams
2022-06-29 16:14 ` Jonathan Cameron
2022-06-24 2:47 ` [PATCH 23/46] tools/testing/cxl: Add partition support Dan Williams
2022-06-29 16:20 ` Jonathan Cameron
2022-06-24 2:48 ` [PATCH 24/46] tools/testing/cxl: Fix decoder default state Dan Williams
2022-06-29 16:22 ` Jonathan Cameron
2022-07-10 17:33 ` Dan Williams
2022-06-24 2:48 ` [PATCH 25/46] cxl/port: Record dport in endpoint references Dan Williams
2022-06-29 16:49 ` Jonathan Cameron
2022-07-10 18:40 ` Dan Williams
2022-06-24 4:19 ` [PATCH 26/46] cxl/port: Record parent dport when adding ports Dan Williams
2022-06-29 17:02 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 27/46] cxl/port: Move 'cxl_ep' references to an xarray per port Dan Williams
2022-06-29 17:19 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 28/46] cxl/port: Move dport tracking to an xarray Dan Williams
2022-06-30 9:18 ` Jonathan Cameron
2022-07-10 19:06 ` Dan Williams
2022-06-24 4:19 ` [PATCH 29/46] cxl/port: Cache CXL host bridge data Dan Williams
2022-06-30 9:21 ` Jonathan Cameron
2022-07-10 19:09 ` Dan Williams
2022-06-24 4:19 ` [PATCH 30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity Dan Williams
2022-06-30 9:26 ` Jonathan Cameron
2022-07-10 20:40 ` Dan Williams
2022-07-19 14:32 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 31/46] cxl/hdm: Initialize decoder type for memory expander devices Dan Williams
2022-06-30 9:33 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 32/46] cxl/mem: Enumerate port targets before adding endpoints Dan Williams
2022-06-30 9:48 ` Jonathan Cameron [this message]
2022-07-10 21:01 ` Dan Williams
2022-06-24 4:19 ` [PATCH 33/46] resource: Introduce alloc_free_mem_region() Dan Williams
2022-06-30 10:35 ` Jonathan Cameron
2022-07-10 21:58 ` Dan Williams
2022-06-24 4:19 ` [PATCH 34/46] cxl/region: Add region creation support Dan Williams
2022-06-30 13:17 ` Jonathan Cameron
2022-07-11 0:08 ` Dan Williams
2022-07-19 14:42 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 35/46] cxl/region: Add a 'uuid' attribute Dan Williams
2022-06-28 10:29 ` Jonathan Cameron
2022-06-28 14:24 ` Dan Williams
2022-06-24 4:19 ` [PATCH 36/46] cxl/region: Add interleave ways attribute Dan Williams
2022-06-30 13:44 ` Jonathan Cameron
2022-07-11 0:32 ` Dan Williams
2022-07-19 14:47 ` Jonathan Cameron
2022-07-19 22:15 ` Dan Williams
2022-07-20 9:59 ` Jonathan Cameron
2022-06-30 13:45 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions Dan Williams
2022-06-30 13:56 ` Jonathan Cameron
2022-07-11 0:47 ` Dan Williams
2022-06-24 4:19 ` [PATCH 38/46] cxl/region: Enable the assignment of endpoint decoders to regions Dan Williams
2022-06-30 14:31 ` Jonathan Cameron
2022-07-11 1:12 ` Dan Williams
2022-06-24 4:19 ` [PATCH 39/46] cxl/acpi: Add a host-bridge index lookup mechanism Dan Williams
2022-06-30 15:48 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 40/46] cxl/region: Attach endpoint decoders Dan Williams
2022-06-24 18:25 ` Jonathan Cameron
2022-06-24 18:49 ` Dan Williams
2022-06-24 20:51 ` Dan Williams
2022-06-24 23:21 ` Dan Williams
2022-06-30 16:34 ` Jonathan Cameron
2022-07-11 2:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 41/46] cxl/region: Program target lists Dan Williams
2022-06-24 4:19 ` [PATCH 42/46] cxl/hdm: Commit decoder state to hardware Dan Williams
2022-06-30 17:05 ` Jonathan Cameron
2022-07-11 3:02 ` Dan Williams
2022-06-24 4:19 ` [PATCH 43/46] cxl/region: Add region driver boiler plate Dan Williams
2022-06-30 17:09 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 44/46] cxl/pmem: Delete unused nvdimm attribute Dan Williams
2022-06-30 17:10 ` Jonathan Cameron
2022-06-24 4:19 ` [PATCH 45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge Dan Williams
2022-06-30 17:14 ` Jonathan Cameron
2022-07-11 19:49 ` Dan Williams
2022-06-24 4:19 ` [PATCH 46/46] cxl/region: Introduce cxl_pmem_region objects Dan Williams
2022-06-30 17:34 ` Jonathan Cameron
2022-07-11 20:05 ` Dan Williams
2022-06-24 15:13 ` [PATCH 00/46] CXL PMEM Region Provisioning Jonathan Cameron
2022-06-24 15:32 ` Dan Williams
2022-06-28 3:12 ` Alison Schofield
2022-06-28 3:34 ` Dan Williams
2022-07-02 2:26 ` Alison Schofield
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220630104820.00006d6e@Huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=dan.j.williams@intel.com \
--cc=hch@lst.de \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=nvdimm@lists.linux.dev \
--cc=patches@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).