* [PATCH v6 1/3] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
2022-02-07 14:51 [PATCH v6 0/3] PCI: IPQ6018 platform support Baruch Siach
@ 2022-02-07 14:51 ` Baruch Siach
2022-02-07 14:51 ` [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Baruch Siach
` (3 subsequent siblings)
4 siblings, 0 replies; 16+ messages in thread
From: Baruch Siach @ 2022-02-07 14:51 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Baruch Siach, Rob Herring, Selvam Sathappan Periakaruppan,
Kathiravan T, Bjorn Helgaas, Rob Herring, Thierry Reding,
Jonathan Hunter, Jingoo Han, Gustavo Pimentel, Robert Marko,
Bryan O'Donoghue, linux-pci, linux-arm-msm, linux-arm-kernel,
linux-tegra
From: Baruch Siach <baruch.siach@siklu.com>
These are common dwc macros that will be used for other platforms.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 7d6e9b7576be..ea87809ee298 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -74,6 +74,12 @@
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
+#define GEN3_RELATED_OFF 0x890
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
+
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b1b5f836a806..74bf66d9afeb 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -193,12 +193,6 @@
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
-#define GEN3_RELATED_OFF 0x890
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
-
#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
2022-02-07 14:51 [PATCH v6 0/3] PCI: IPQ6018 platform support Baruch Siach
2022-02-07 14:51 ` [PATCH v6 1/3] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
@ 2022-02-07 14:51 ` Baruch Siach
2022-06-08 23:00 ` Pali Rohár
2022-02-07 14:51 ` [PATCH v6 3/3] PCI: qcom: Add IPQ60xx support Baruch Siach
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Baruch Siach @ 2022-02-07 14:51 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Baruch Siach, Selvam Sathappan Periakaruppan, Kathiravan T,
Bjorn Helgaas, Rob Herring, Thierry Reding, Jonathan Hunter,
Jingoo Han, Gustavo Pimentel, Robert Marko, Bryan O'Donoghue,
linux-pci, linux-arm-msm, linux-arm-kernel, linux-tegra
From: Baruch Siach <baruch.siach@siklu.com>
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
describe its meaning.
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index c19cd506ed3f..01e58b057d2a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -69,7 +69,18 @@
#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
#define CFG_BRIDGE_SB_INIT BIT(0)
-#define PCIE_CAP_LINK1_VAL 0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
+ PCI_EXP_SLTCAP_PCP | \
+ PCI_EXP_SLTCAP_MRLSP | \
+ PCI_EXP_SLTCAP_AIP | \
+ PCI_EXP_SLTCAP_PIP | \
+ PCI_EXP_SLTCAP_HPS | \
+ PCI_EXP_SLTCAP_HPC | \
+ PCI_EXP_SLTCAP_EIP | \
+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
@@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
val &= ~PCI_EXP_LNKCAP_ASPMS;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
2022-02-07 14:51 ` [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Baruch Siach
@ 2022-06-08 23:00 ` Pali Rohár
2022-06-09 3:27 ` Baruch Siach
0 siblings, 1 reply; 16+ messages in thread
From: Pali Rohár @ 2022-06-08 23:00 UTC (permalink / raw)
To: Baruch Siach
Cc: Andy Gross, Bjorn Andersson, Baruch Siach,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Robert Marko, Bryan O'Donoghue, linux-pci,
linux-arm-msm, linux-arm-kernel, linux-tegra
On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
> From: Baruch Siach <baruch.siach@siklu.com>
>
> The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
> PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
> describe its meaning.
>
> Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c19cd506ed3f..01e58b057d2a 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -69,7 +69,18 @@
> #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
> #define CFG_BRIDGE_SB_INIT BIT(0)
>
> -#define PCIE_CAP_LINK1_VAL 0x2FD7F
> +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
> +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
Hello!
Please do not use hardcoded values for slot power limit value and scale
numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS
for composing mask:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79
And the important information: Slot power limit is board specific and
depends on how power supply and power regulators are designed. So slot
power limit **cannot** be hardcoded in driver. Instead this value should
be read from device tree file for the current board.
There is a new kernel function of_pci_get_slot_power_limit() which reads
it and compose PCIe slot power limit value and scale numbers. See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631
> +#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
> + PCI_EXP_SLTCAP_PCP | \
> + PCI_EXP_SLTCAP_MRLSP | \
> + PCI_EXP_SLTCAP_AIP | \
> + PCI_EXP_SLTCAP_PIP | \
> + PCI_EXP_SLTCAP_HPS | \
> + PCI_EXP_SLTCAP_HPC | \
> + PCI_EXP_SLTCAP_EIP | \
> + PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
> + PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
>
> #define PCIE20_PARF_Q2A_FLUSH 0x1AC
>
> @@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
>
> writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
> writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
> - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>
> val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> val &= ~PCI_EXP_LNKCAP_ASPMS;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
2022-06-08 23:00 ` Pali Rohár
@ 2022-06-09 3:27 ` Baruch Siach
2022-06-09 8:47 ` Pali Rohár
0 siblings, 1 reply; 16+ messages in thread
From: Baruch Siach @ 2022-06-09 3:27 UTC (permalink / raw)
To: Pali Rohár
Cc: Andy Gross, Bjorn Andersson, Selvam Sathappan Periakaruppan,
Kathiravan T, Bjorn Helgaas, Rob Herring, Thierry Reding,
Jonathan Hunter, Jingoo Han, Gustavo Pimentel, Robert Marko,
Bryan O'Donoghue, linux-pci, linux-arm-msm, linux-arm-kernel,
linux-tegra, Stanimir Varbanov
Hi Pali,
On Thu, Jun 09 2022, Pali Rohár wrote:
> On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
>> From: Baruch Siach <baruch.siach@siklu.com>
>>
>> The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
>> PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
>> describe its meaning.
>>
>> Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
>> 1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index c19cd506ed3f..01e58b057d2a 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -69,7 +69,18 @@
>> #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
>> #define CFG_BRIDGE_SB_INIT BIT(0)
>>
>> -#define PCIE_CAP_LINK1_VAL 0x2FD7F
>> +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
>> +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
>
> Hello!
>
> Please do not use hardcoded values for slot power limit value and scale
> numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS
> for composing mask:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
> Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79
Thanks for the tip.
> And the important information: Slot power limit is board specific and
> depends on how power supply and power regulators are designed. So slot
> power limit **cannot** be hardcoded in driver. Instead this value should
> be read from device tree file for the current board.
>
> There is a new kernel function of_pci_get_slot_power_limit() which reads
> it and compose PCIe slot power limit value and scale numbers. See:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631
The 'slot-power-limit-milliwatt' property appears to be undocumented as
of v5.19-rc1.
This patch should make no functional change. I guess we should keep the
default hard-coded driver value for compatibility with existing DTs with
no 'slot-power-limit-milliwatt'.
Thanks,
baruch
>> +#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
>> + PCI_EXP_SLTCAP_PCP | \
>> + PCI_EXP_SLTCAP_MRLSP | \
>> + PCI_EXP_SLTCAP_AIP | \
>> + PCI_EXP_SLTCAP_PIP | \
>> + PCI_EXP_SLTCAP_HPS | \
>> + PCI_EXP_SLTCAP_HPC | \
>> + PCI_EXP_SLTCAP_EIP | \
>> + PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
>> + PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
>>
>> #define PCIE20_PARF_Q2A_FLUSH 0x1AC
>>
>> @@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
>>
>> writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
>> writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
>> - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>>
>> val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> val &= ~PCI_EXP_LNKCAP_ASPMS;
>> --
>> 2.34.1
>>
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
2022-06-09 3:27 ` Baruch Siach
@ 2022-06-09 8:47 ` Pali Rohár
0 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-06-09 8:47 UTC (permalink / raw)
To: Baruch Siach
Cc: Andy Gross, Bjorn Andersson, Selvam Sathappan Periakaruppan,
Kathiravan T, Bjorn Helgaas, Rob Herring, Thierry Reding,
Jonathan Hunter, Jingoo Han, Gustavo Pimentel, Robert Marko,
Bryan O'Donoghue, linux-pci, linux-arm-msm, linux-arm-kernel,
linux-tegra, Stanimir Varbanov
On Thursday 09 June 2022 06:27:34 Baruch Siach wrote:
> Hi Pali,
>
> On Thu, Jun 09 2022, Pali Rohár wrote:
> > On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
> >> From: Baruch Siach <baruch.siach@siklu.com>
> >>
> >> The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
> >> PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
> >> describe its meaning.
> >>
> >> Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
> >> ---
> >> drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
> >> 1 file changed, 13 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> >> index c19cd506ed3f..01e58b057d2a 100644
> >> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> >> @@ -69,7 +69,18 @@
> >> #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
> >> #define CFG_BRIDGE_SB_INIT BIT(0)
> >>
> >> -#define PCIE_CAP_LINK1_VAL 0x2FD7F
> >> +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL 0x7D00
> >> +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE 0x8000
> >
> > Hello!
> >
> > Please do not use hardcoded values for slot power limit value and scale
> > numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS
> > for composing mask:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
> > Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79
>
> Thanks for the tip.
>
> > And the important information: Slot power limit is board specific and
> > depends on how power supply and power regulators are designed. So slot
> > power limit **cannot** be hardcoded in driver. Instead this value should
> > be read from device tree file for the current board.
> >
> > There is a new kernel function of_pci_get_slot_power_limit() which reads
> > it and compose PCIe slot power limit value and scale numbers. See:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631
>
> The 'slot-power-limit-milliwatt' property appears to be undocumented as
> of v5.19-rc1.
slot-power-limit-milliwatt is already documented in DT scheme pci-bus, see:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus.yaml
> This patch should make no functional change. I guess we should keep the
> default hard-coded driver value for compatibility with existing DTs with
> no 'slot-power-limit-milliwatt'.
>
> Thanks,
> baruch
>
> >> +#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
> >> + PCI_EXP_SLTCAP_PCP | \
> >> + PCI_EXP_SLTCAP_MRLSP | \
> >> + PCI_EXP_SLTCAP_AIP | \
> >> + PCI_EXP_SLTCAP_PIP | \
> >> + PCI_EXP_SLTCAP_HPS | \
> >> + PCI_EXP_SLTCAP_HPC | \
> >> + PCI_EXP_SLTCAP_EIP | \
> >> + PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
> >> + PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
> >>
> >> #define PCIE20_PARF_Q2A_FLUSH 0x1AC
> >>
> >> @@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
> >>
> >> writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
> >> writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
> >> - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> >> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> >>
> >> val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> >> val &= ~PCI_EXP_LNKCAP_ASPMS;
> >> --
> >> 2.34.1
> >>
>
>
> --
> ~. .~ Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
> - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 3/3] PCI: qcom: Add IPQ60xx support
2022-02-07 14:51 [PATCH v6 0/3] PCI: IPQ6018 platform support Baruch Siach
2022-02-07 14:51 ` [PATCH v6 1/3] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
2022-02-07 14:51 ` [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Baruch Siach
@ 2022-02-07 14:51 ` Baruch Siach
2022-02-11 16:06 ` [PATCH v6 0/3] PCI: IPQ6018 platform support Lorenzo Pieralisi
2022-04-12 16:12 ` Lorenzo Pieralisi
4 siblings, 0 replies; 16+ messages in thread
From: Baruch Siach @ 2022-02-07 14:51 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Selvam Sathappan Periakaruppan, Baruch Siach, Kathiravan T,
Bjorn Helgaas, Rob Herring, Thierry Reding, Jonathan Hunter,
Jingoo Han, Gustavo Pimentel, Robert Marko, Bryan O'Donoghue,
linux-pci, linux-arm-msm, linux-arm-kernel, linux-tegra
From: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
platform.
The code is based on downstream[1] Codeaurora kernel v5.4 (branch
win.linuxopenwrt.2.0).
Split out the DBI registers access part from .init into .post_init. DBI
registers are only accessible after phy_power_on().
[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
v6:
Address Bjorn Helgaas comments:
* Rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
v4:
* Rebase on v5.16-rc1
v3:
* Drop speed setup; rely on generic code (Rob Herring)
* Drop unused CLK_RATE macros (Bjorn Helgaas)
* Minor formatting fixes (Bjorn Helgaas)
* Add reference to downstream Codeaurora kernel tree (Bjorn Helgaas)
v2:
* Drop ATU configuration; rely on common code instead
* Use more common register macros
* Use bulk clk and reset APIs
---
drivers/pci/controller/dwc/pcie-designware.h | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 140 +++++++++++++++++++
2 files changed, 141 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ea87809ee298..279c3778a13b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -76,6 +76,7 @@
#define GEN3_RELATED_OFF 0x890
#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 01e58b057d2a..8dba74069180 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -52,6 +52,10 @@
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
+#define AHB_CLK_EN BIT(0)
+#define MSTR_AXI_CLK_EN BIT(1)
+#define BYPASS BIT(4)
+
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
#define PCIE20_PARF_LTSSM 0x1B0
@@ -182,6 +186,11 @@ struct qcom_pcie_resources_2_7_0 {
struct clk *ref_clk_src;
};
+struct qcom_pcie_resources_2_9_0 {
+ struct clk_bulk_data clks[5];
+ struct reset_control *rst;
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -189,6 +198,7 @@ union qcom_pcie_resources {
struct qcom_pcie_resources_2_3_3 v2_3_3;
struct qcom_pcie_resources_2_4_0 v2_4_0;
struct qcom_pcie_resources_2_7_0 v2_7_0;
+ struct qcom_pcie_resources_2_9_0 v2_9_0;
};
struct qcom_pcie;
@@ -1308,6 +1318,122 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
clk_disable_unprepare(res->pipe_clk);
}
+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int ret;
+
+ res->clks[0].id = "iface";
+ res->clks[1].id = "axi_m";
+ res->clks[2].id = "axi_s";
+ res->clks[3].id = "axi_bridge";
+ res->clks[4].id = "rchng";
+
+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+ if (ret < 0)
+ return ret;
+
+ res->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(res->rst))
+ return PTR_ERR(res->rst);
+
+ return 0;
+}
+
+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+ struct device *dev = pcie->pci->dev;
+ int ret;
+
+ ret = reset_control_assert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset assert failed (%d)\n", ret);
+ return ret;
+ }
+
+ /*
+ * Delay periods before and after reset deassert are working values
+ * from downstream Codeaurora kernel
+ */
+ usleep_range(2000, 2500);
+
+ ret = reset_control_deassert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset deassert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(2000, 2500);
+
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+ if (ret)
+ goto err_reset;
+
+ return 0;
+
+err_reset:
+ reset_control_assert(res->rst);
+
+ return ret;
+}
+
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct dw_pcie *pci = pcie->pci;
+ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ u32 val;
+ int i;
+
+ writel(SLV_ADDR_SPACE_SZ,
+ pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
+ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS
+ | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
+ pci->dbi_base + GEN3_RELATED_OFF);
+
+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
+ | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+ pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+ dw_pcie_dbi_ro_wr_en(pci);
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+
+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+ val &= ~PCI_EXP_LNKCAP_ASPMS;
+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
+
+ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+ PCI_EXP_DEVCTL2);
+
+ for (i = 0; i < 256; i++)
+ writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N
+ + (4 * i));
+
+ return 0;
+}
+
static int qcom_pcie_link_up(struct dw_pcie *pci)
{
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -1498,6 +1624,15 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
.config_sid = qcom_pcie_config_sid_sm8250,
};
+/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
+static const struct qcom_pcie_ops ops_2_9_0 = {
+ .get_resources = qcom_pcie_get_resources_2_9_0,
+ .init = qcom_pcie_init_2_9_0,
+ .post_init = qcom_pcie_post_init_2_9_0,
+ .deinit = qcom_pcie_deinit_2_9_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
static const struct qcom_pcie_cfg apq8084_cfg = {
.ops = &ops_1_0_0,
};
@@ -1531,6 +1666,10 @@ static const struct qcom_pcie_cfg sc7280_cfg = {
.pipe_clk_need_muxing = true,
};
+static const struct qcom_pcie_cfg ipq6018_cfg = {
+ .ops = &ops_2_9_0,
+};
+
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
@@ -1640,6 +1779,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
+ { .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
{ }
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-02-07 14:51 [PATCH v6 0/3] PCI: IPQ6018 platform support Baruch Siach
` (2 preceding siblings ...)
2022-02-07 14:51 ` [PATCH v6 3/3] PCI: qcom: Add IPQ60xx support Baruch Siach
@ 2022-02-11 16:06 ` Lorenzo Pieralisi
2022-03-15 13:04 ` Robert Marko
2022-04-12 16:12 ` Lorenzo Pieralisi
4 siblings, 1 reply; 16+ messages in thread
From: Lorenzo Pieralisi @ 2022-02-11 16:06 UTC (permalink / raw)
To: Baruch Siach, Andy Gross, Bjorn Andersson
Cc: Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Robert Marko, Bryan O'Donoghue, linux-pci,
linux-arm-msm, linux-arm-kernel, linux-tegra
On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> ported from downstream Codeaurora v5.4 kernel. The main difference from
> downstream code is the split of PCIe registers configuration from .init to
> .post_init, since it requires phy_power_on().
>
> Tested on IPQ6010 based hardware.
>
> Changes in v6:
>
> * Drop DT patch applied to the qcom tree
>
> * Normalize driver changes subject line
>
> * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
> and define it using PCI_EXP_SLTCAP_* macros
>
> * Drop a vague comment about ASPM configuration
>
> * Add a comment about the source of delay periods
>
> Changes in v5:
>
> * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
>
> Changes in v4:
>
> * Drop applied DT bits
>
> * Add max-link-speed that was missing from the applied v2 patch
>
> * Rebase the driver on v5.16-rc3
>
> Changes in v3:
>
> * Drop applied patches
>
> * Rely on generic code for speed setup
>
> * Drop unused macros
>
> * Formatting fixes
>
> Changes in v2:
>
> * Add patch moving GEN3_RELATED macros to a common header
>
> * Drop ATU configuration from pcie-qcom
>
> * Remove local definition of common registers
>
> * Use bulk clk and reset APIs
>
> * Remove msi-parent from device-tree
>
> Baruch Siach (2):
> PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
>
> Selvam Sathappan Periakaruppan (1):
> PCI: qcom: Add IPQ60xx support
>
> drivers/pci/controller/dwc/pcie-designware.h | 7 +
> drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> 3 files changed, 160 insertions(+), 8 deletions(-)
Bjorn, Andy,
Can you ACK please if this series is ready to be merged ?
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-02-11 16:06 ` [PATCH v6 0/3] PCI: IPQ6018 platform support Lorenzo Pieralisi
@ 2022-03-15 13:04 ` Robert Marko
2022-03-15 13:20 ` Baruch Siach
0 siblings, 1 reply; 16+ messages in thread
From: Robert Marko @ 2022-03-15 13:04 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Baruch Siach, Andy Gross, Bjorn Andersson,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Bryan O'Donoghue, linux-pci, linux-arm-msm,
Linux ARM, linux-tegra
On Fri, Feb 11, 2022 at 5:06 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> > ported from downstream Codeaurora v5.4 kernel. The main difference from
> > downstream code is the split of PCIe registers configuration from .init to
> > .post_init, since it requires phy_power_on().
> >
> > Tested on IPQ6010 based hardware.
> >
> > Changes in v6:
> >
> > * Drop DT patch applied to the qcom tree
> >
> > * Normalize driver changes subject line
> >
> > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
> > and define it using PCI_EXP_SLTCAP_* macros
> >
> > * Drop a vague comment about ASPM configuration
> >
> > * Add a comment about the source of delay periods
> >
> > Changes in v5:
> >
> > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
> >
> > Changes in v4:
> >
> > * Drop applied DT bits
> >
> > * Add max-link-speed that was missing from the applied v2 patch
> >
> > * Rebase the driver on v5.16-rc3
> >
> > Changes in v3:
> >
> > * Drop applied patches
> >
> > * Rely on generic code for speed setup
> >
> > * Drop unused macros
> >
> > * Formatting fixes
> >
> > Changes in v2:
> >
> > * Add patch moving GEN3_RELATED macros to a common header
> >
> > * Drop ATU configuration from pcie-qcom
> >
> > * Remove local definition of common registers
> >
> > * Use bulk clk and reset APIs
> >
> > * Remove msi-parent from device-tree
> >
> > Baruch Siach (2):
> > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> >
> > Selvam Sathappan Periakaruppan (1):
> > PCI: qcom: Add IPQ60xx support
> >
> > drivers/pci/controller/dwc/pcie-designware.h | 7 +
> > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> > 3 files changed, 160 insertions(+), 8 deletions(-)
>
> Bjorn, Andy,
>
> Can you ACK please if this series is ready to be merged ?
Hi,
This would also help the IPQ8074 which has the same controller for the
Gen3 port.
I have been using this for OpenWrt for a while and it works.
Regards,
Robert
>
> Thanks,
> Lorenzo
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-03-15 13:04 ` Robert Marko
@ 2022-03-15 13:20 ` Baruch Siach
2022-03-15 13:41 ` Robert Marko
0 siblings, 1 reply; 16+ messages in thread
From: Baruch Siach @ 2022-03-15 13:20 UTC (permalink / raw)
To: Robert Marko
Cc: Lorenzo Pieralisi, Andy Gross, Bjorn Andersson,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Bryan O'Donoghue, linux-pci, linux-arm-msm,
Linux ARM, linux-tegra
Hi Robert,
On Tue, Mar 15 2022, Robert Marko wrote:
> On Fri, Feb 11, 2022 at 5:06 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
>>
>> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
>> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
>> > ported from downstream Codeaurora v5.4 kernel. The main difference from
>> > downstream code is the split of PCIe registers configuration from .init to
>> > .post_init, since it requires phy_power_on().
>> >
>> > Tested on IPQ6010 based hardware.
[snip]
>> >
>> > Baruch Siach (2):
>> > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
>> > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
>> >
>> > Selvam Sathappan Periakaruppan (1):
>> > PCI: qcom: Add IPQ60xx support
>> >
>> > drivers/pci/controller/dwc/pcie-designware.h | 7 +
>> > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
>> > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
>> > 3 files changed, 160 insertions(+), 8 deletions(-)
>>
>> Bjorn, Andy,
>>
>> Can you ACK please if this series is ready to be merged ?
>
> This would also help the IPQ8074 which has the same controller for the
> Gen3 port.
>
> I have been using this for OpenWrt for a while and it works.
Thanks for your test report.
It would be nice to have a formal Tested-by for the pcie-qcom.c
patch. It might help to push the patch forward.
Can you also share the device-tree part? I'll add it to this series in
case it needs a respin.
Thanks,
baruch
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-03-15 13:20 ` Baruch Siach
@ 2022-03-15 13:41 ` Robert Marko
0 siblings, 0 replies; 16+ messages in thread
From: Robert Marko @ 2022-03-15 13:41 UTC (permalink / raw)
To: Baruch Siach
Cc: Lorenzo Pieralisi, Andy Gross, Bjorn Andersson,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Bryan O'Donoghue, linux-pci, linux-arm-msm,
Linux ARM, linux-tegra
On Tue, Mar 15, 2022 at 2:30 PM Baruch Siach <baruch@tkos.co.il> wrote:
>
> Hi Robert,
>
> On Tue, Mar 15 2022, Robert Marko wrote:
> > On Fri, Feb 11, 2022 at 5:06 PM Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com> wrote:
> >>
> >> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> >> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> >> > ported from downstream Codeaurora v5.4 kernel. The main difference from
> >> > downstream code is the split of PCIe registers configuration from .init to
> >> > .post_init, since it requires phy_power_on().
> >> >
> >> > Tested on IPQ6010 based hardware.
> [snip]
> >> >
> >> > Baruch Siach (2):
> >> > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> >> > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> >> >
> >> > Selvam Sathappan Periakaruppan (1):
> >> > PCI: qcom: Add IPQ60xx support
> >> >
> >> > drivers/pci/controller/dwc/pcie-designware.h | 7 +
> >> > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> >> > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> >> > 3 files changed, 160 insertions(+), 8 deletions(-)
> >>
> >> Bjorn, Andy,
> >>
> >> Can you ACK please if this series is ready to be merged ?
> >
> > This would also help the IPQ8074 which has the same controller for the
> > Gen3 port.
> >
> > I have been using this for OpenWrt for a while and it works.
>
> Thanks for your test report.
>
> It would be nice to have a formal Tested-by for the pcie-qcom.c
> patch. It might help to push the patch forward.
Hi Baruch, I am not sure whether a Tested-by would be applicable here as its
a different platform, that is why I left it out.
>
> Can you also share the device-tree part? I'll add it to this series in
> case it needs a respin.
Currently, the IPQ8074 DTS regarding QMP PCI PHY-s and PCI controllers is
incorrect, it was all based on v1 of the SoC which is not supported at all.
Gen3 QMP PHY support is currently missing for IPQ8074 and I am working on
upstreaming that and will fix up all of the PCI-related stuff in the
DTS after that.
So, I would prefer to keep those separate and let this series get
merged, especially
since the DTS part has already been merged.
Regards,
Robert
>
> Thanks,
> baruch
>
> --
> ~. .~ Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
> - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-02-07 14:51 [PATCH v6 0/3] PCI: IPQ6018 platform support Baruch Siach
` (3 preceding siblings ...)
2022-02-11 16:06 ` [PATCH v6 0/3] PCI: IPQ6018 platform support Lorenzo Pieralisi
@ 2022-04-12 16:12 ` Lorenzo Pieralisi
2022-05-11 14:03 ` Lorenzo Pieralisi
4 siblings, 1 reply; 16+ messages in thread
From: Lorenzo Pieralisi @ 2022-04-12 16:12 UTC (permalink / raw)
To: Baruch Siach, Bjorn Andersson, Andy Gross
Cc: Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Robert Marko, Bryan O'Donoghue, linux-pci,
linux-arm-msm, linux-arm-kernel, linux-tegra
On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> ported from downstream Codeaurora v5.4 kernel. The main difference from
> downstream code is the split of PCIe registers configuration from .init to
> .post_init, since it requires phy_power_on().
>
> Tested on IPQ6010 based hardware.
>
> Changes in v6:
>
> * Drop DT patch applied to the qcom tree
>
> * Normalize driver changes subject line
>
> * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
> and define it using PCI_EXP_SLTCAP_* macros
>
> * Drop a vague comment about ASPM configuration
>
> * Add a comment about the source of delay periods
>
> Changes in v5:
>
> * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
>
> Changes in v4:
>
> * Drop applied DT bits
>
> * Add max-link-speed that was missing from the applied v2 patch
>
> * Rebase the driver on v5.16-rc3
>
> Changes in v3:
>
> * Drop applied patches
>
> * Rely on generic code for speed setup
>
> * Drop unused macros
>
> * Formatting fixes
>
> Changes in v2:
>
> * Add patch moving GEN3_RELATED macros to a common header
>
> * Drop ATU configuration from pcie-qcom
>
> * Remove local definition of common registers
>
> * Use bulk clk and reset APIs
>
> * Remove msi-parent from device-tree
>
> Baruch Siach (2):
> PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
>
> Selvam Sathappan Periakaruppan (1):
> PCI: qcom: Add IPQ60xx support
>
> drivers/pci/controller/dwc/pcie-designware.h | 7 +
> drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> 3 files changed, 160 insertions(+), 8 deletions(-)
Hi Bjorn, Andy,
any feedback on this series please ?
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-04-12 16:12 ` Lorenzo Pieralisi
@ 2022-05-11 14:03 ` Lorenzo Pieralisi
2022-06-07 13:12 ` Robert Marko
0 siblings, 1 reply; 16+ messages in thread
From: Lorenzo Pieralisi @ 2022-05-11 14:03 UTC (permalink / raw)
To: Baruch Siach, Bjorn Andersson, Andy Gross
Cc: Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Robert Marko, Bryan O'Donoghue, linux-pci,
linux-arm-msm, linux-arm-kernel, linux-tegra
On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote:
> On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> > ported from downstream Codeaurora v5.4 kernel. The main difference from
> > downstream code is the split of PCIe registers configuration from .init to
> > .post_init, since it requires phy_power_on().
> >
> > Tested on IPQ6010 based hardware.
> >
> > Changes in v6:
> >
> > * Drop DT patch applied to the qcom tree
> >
> > * Normalize driver changes subject line
> >
> > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
> > and define it using PCI_EXP_SLTCAP_* macros
> >
> > * Drop a vague comment about ASPM configuration
> >
> > * Add a comment about the source of delay periods
> >
> > Changes in v5:
> >
> > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
> >
> > Changes in v4:
> >
> > * Drop applied DT bits
> >
> > * Add max-link-speed that was missing from the applied v2 patch
> >
> > * Rebase the driver on v5.16-rc3
> >
> > Changes in v3:
> >
> > * Drop applied patches
> >
> > * Rely on generic code for speed setup
> >
> > * Drop unused macros
> >
> > * Formatting fixes
> >
> > Changes in v2:
> >
> > * Add patch moving GEN3_RELATED macros to a common header
> >
> > * Drop ATU configuration from pcie-qcom
> >
> > * Remove local definition of common registers
> >
> > * Use bulk clk and reset APIs
> >
> > * Remove msi-parent from device-tree
> >
> > Baruch Siach (2):
> > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> >
> > Selvam Sathappan Periakaruppan (1):
> > PCI: qcom: Add IPQ60xx support
> >
> > drivers/pci/controller/dwc/pcie-designware.h | 7 +
> > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> > 3 files changed, 160 insertions(+), 8 deletions(-)
>
> Hi Bjorn, Andy,
>
> any feedback on this series please ?
Any feedback on these patches please ?
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-05-11 14:03 ` Lorenzo Pieralisi
@ 2022-06-07 13:12 ` Robert Marko
2022-06-08 20:24 ` Bjorn Helgaas
0 siblings, 1 reply; 16+ messages in thread
From: Robert Marko @ 2022-06-07 13:12 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Baruch Siach, Bjorn Andersson, Andy Gross,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Bryan O'Donoghue, linux-pci, linux-arm-msm,
Linux ARM, linux-tegra
On Wed, May 11, 2022 at 4:03 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote:
> > On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> > > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> > > ported from downstream Codeaurora v5.4 kernel. The main difference from
> > > downstream code is the split of PCIe registers configuration from .init to
> > > .post_init, since it requires phy_power_on().
> > >
> > > Tested on IPQ6010 based hardware.
> > >
> > > Changes in v6:
> > >
> > > * Drop DT patch applied to the qcom tree
> > >
> > > * Normalize driver changes subject line
> > >
> > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
> > > and define it using PCI_EXP_SLTCAP_* macros
> > >
> > > * Drop a vague comment about ASPM configuration
> > >
> > > * Add a comment about the source of delay periods
> > >
> > > Changes in v5:
> > >
> > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
> > >
> > > Changes in v4:
> > >
> > > * Drop applied DT bits
> > >
> > > * Add max-link-speed that was missing from the applied v2 patch
> > >
> > > * Rebase the driver on v5.16-rc3
> > >
> > > Changes in v3:
> > >
> > > * Drop applied patches
> > >
> > > * Rely on generic code for speed setup
> > >
> > > * Drop unused macros
> > >
> > > * Formatting fixes
> > >
> > > Changes in v2:
> > >
> > > * Add patch moving GEN3_RELATED macros to a common header
> > >
> > > * Drop ATU configuration from pcie-qcom
> > >
> > > * Remove local definition of common registers
> > >
> > > * Use bulk clk and reset APIs
> > >
> > > * Remove msi-parent from device-tree
> > >
> > > Baruch Siach (2):
> > > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> > > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> > >
> > > Selvam Sathappan Periakaruppan (1):
> > > PCI: qcom: Add IPQ60xx support
> > >
> > > drivers/pci/controller/dwc/pcie-designware.h | 7 +
> > > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> > > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> > > 3 files changed, 160 insertions(+), 8 deletions(-)
> >
> > Hi Bjorn, Andy,
> >
> > any feedback on this series please ?
>
> Any feedback on these patches please ?
Finally dug the CP01, and for me, it works, so:
Tested-by: Robert Marko <robert.marko@sartura.hr>
Can we finally get this merged or at least looked at.
IPQ8074 will also benefit from this.
Regards,
Robert
>
> Thanks,
> Lorenzo
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-06-07 13:12 ` Robert Marko
@ 2022-06-08 20:24 ` Bjorn Helgaas
2022-06-09 13:10 ` Baruch Siach
0 siblings, 1 reply; 16+ messages in thread
From: Bjorn Helgaas @ 2022-06-08 20:24 UTC (permalink / raw)
To: Robert Marko
Cc: Lorenzo Pieralisi, Baruch Siach, Bjorn Andersson, Andy Gross,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Bryan O'Donoghue, linux-pci, linux-arm-msm,
Linux ARM, linux-tegra, Stanimir Varbanov
[+cc Stanimir, beginning of thread at
https://lore.kernel.org/r/cover.1644234441.git.baruch@tkos.co.il]
On Tue, Jun 07, 2022 at 03:12:19PM +0200, Robert Marko wrote:
> On Wed, May 11, 2022 at 4:03 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> >
> > On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote:
> > > On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
> > > > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
> > > > ported from downstream Codeaurora v5.4 kernel. The main difference from
> > > > downstream code is the split of PCIe registers configuration from .init to
> > > > .post_init, since it requires phy_power_on().
> > > >
> > > > Tested on IPQ6010 based hardware.
> > > >
> > > > Changes in v6:
> > > >
> > > > * Drop DT patch applied to the qcom tree
> > > >
> > > > * Normalize driver changes subject line
> > > >
> > > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
> > > > and define it using PCI_EXP_SLTCAP_* macros
> > > >
> > > > * Drop a vague comment about ASPM configuration
> > > >
> > > > * Add a comment about the source of delay periods
> > > >
> > > > Changes in v5:
> > > >
> > > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
> > > >
> > > > Changes in v4:
> > > >
> > > > * Drop applied DT bits
> > > >
> > > > * Add max-link-speed that was missing from the applied v2 patch
> > > >
> > > > * Rebase the driver on v5.16-rc3
> > > >
> > > > Changes in v3:
> > > >
> > > > * Drop applied patches
> > > >
> > > > * Rely on generic code for speed setup
> > > >
> > > > * Drop unused macros
> > > >
> > > > * Formatting fixes
> > > >
> > > > Changes in v2:
> > > >
> > > > * Add patch moving GEN3_RELATED macros to a common header
> > > >
> > > > * Drop ATU configuration from pcie-qcom
> > > >
> > > > * Remove local definition of common registers
> > > >
> > > > * Use bulk clk and reset APIs
> > > >
> > > > * Remove msi-parent from device-tree
> > > >
> > > > Baruch Siach (2):
> > > > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> > > > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> > > >
> > > > Selvam Sathappan Periakaruppan (1):
> > > > PCI: qcom: Add IPQ60xx support
> > > >
> > > > drivers/pci/controller/dwc/pcie-designware.h | 7 +
> > > > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
> > > > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
> > > > 3 files changed, 160 insertions(+), 8 deletions(-)
> > >
> > > Hi Bjorn, Andy,
> > >
> > > any feedback on this series please ?
> >
> > Any feedback on these patches please ?
>
> Finally dug the CP01, and for me, it works, so:
> Tested-by: Robert Marko <robert.marko@sartura.hr>
This mainly affects pcie-qcom.c, so it looks like Stanimir should have
been copied on this, but wasn't. Please include him on the next
iteration.
This will also need to be updated to apply on v5.19-rc1:
03:21:47 ~/linux (next)$ git checkout -b wip/baruch-ipq6018-v6 v5.19-rc1
Switched to a new branch 'wip/baruch-ipq6018-v6'
03:21:55 ~/linux (wip/baruch-ipq6018-v6)$ git am m/v6_20220207_baruch_pci_ipq6018_platform_support.mbx
Applying: PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
Applying: PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Applying: PCI: qcom: Add IPQ60xx support
error: patch failed: drivers/pci/controller/dwc/pcie-qcom.c:1531
error: drivers/pci/controller/dwc/pcie-qcom.c: patch does not apply
Patch failed at 0003 PCI: qcom: Add IPQ60xx support
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 0/3] PCI: IPQ6018 platform support
2022-06-08 20:24 ` Bjorn Helgaas
@ 2022-06-09 13:10 ` Baruch Siach
0 siblings, 0 replies; 16+ messages in thread
From: Baruch Siach @ 2022-06-09 13:10 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Robert Marko, Lorenzo Pieralisi, Bjorn Andersson, Andy Gross,
Selvam Sathappan Periakaruppan, Kathiravan T, Bjorn Helgaas,
Rob Herring, Thierry Reding, Jonathan Hunter, Jingoo Han,
Gustavo Pimentel, Bryan O'Donoghue, linux-pci, linux-arm-msm,
Linux ARM, linux-tegra, Stanimir Varbanov
Hi Bjorn,
[ Changed codeaurora.com addresses to their quicinc.com equivalents ]
On Wed, Jun 08 2022, Bjorn Helgaas wrote:
> [+cc Stanimir, beginning of thread at
> https://lore.kernel.org/r/cover.1644234441.git.baruch@tkos.co.il]
>
> On Tue, Jun 07, 2022 at 03:12:19PM +0200, Robert Marko wrote:
>> On Wed, May 11, 2022 at 4:03 PM Lorenzo Pieralisi
>> <lorenzo.pieralisi@arm.com> wrote:
>> >
>> > On Tue, Apr 12, 2022 at 05:12:59PM +0100, Lorenzo Pieralisi wrote:
>> > > On Mon, Feb 07, 2022 at 04:51:23PM +0200, Baruch Siach wrote:
>> > > > This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is
>> > > > ported from downstream Codeaurora v5.4 kernel. The main difference from
>> > > > downstream code is the split of PCIe registers configuration from .init to
>> > > > .post_init, since it requires phy_power_on().
>> > > >
>> > > > Tested on IPQ6010 based hardware.
>> > > >
>> > > > Changes in v6:
>> > > >
>> > > > * Drop DT patch applied to the qcom tree
>> > > >
>> > > > * Normalize driver changes subject line
>> > > >
>> > > > * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL,
>> > > > and define it using PCI_EXP_SLTCAP_* macros
>> > > >
>> > > > * Drop a vague comment about ASPM configuration
>> > > >
>> > > > * Add a comment about the source of delay periods
>> > > >
>> > > > Changes in v5:
>> > > >
>> > > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
>> > > >
>> > > > Changes in v4:
>> > > >
>> > > > * Drop applied DT bits
>> > > >
>> > > > * Add max-link-speed that was missing from the applied v2 patch
>> > > >
>> > > > * Rebase the driver on v5.16-rc3
>> > > >
>> > > > Changes in v3:
>> > > >
>> > > > * Drop applied patches
>> > > >
>> > > > * Rely on generic code for speed setup
>> > > >
>> > > > * Drop unused macros
>> > > >
>> > > > * Formatting fixes
>> > > >
>> > > > Changes in v2:
>> > > >
>> > > > * Add patch moving GEN3_RELATED macros to a common header
>> > > >
>> > > > * Drop ATU configuration from pcie-qcom
>> > > >
>> > > > * Remove local definition of common registers
>> > > >
>> > > > * Use bulk clk and reset APIs
>> > > >
>> > > > * Remove msi-parent from device-tree
>> > > >
>> > > > Baruch Siach (2):
>> > > > PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
>> > > > PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
>> > > >
>> > > > Selvam Sathappan Periakaruppan (1):
>> > > > PCI: qcom: Add IPQ60xx support
>> > > >
>> > > > drivers/pci/controller/dwc/pcie-designware.h | 7 +
>> > > > drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++-
>> > > > drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
>> > > > 3 files changed, 160 insertions(+), 8 deletions(-)
>> > >
>> > > Hi Bjorn, Andy,
>> > >
>> > > any feedback on this series please ?
>> >
>> > Any feedback on these patches please ?
>>
>> Finally dug the CP01, and for me, it works, so:
>> Tested-by: Robert Marko <robert.marko@sartura.hr>
>
> This mainly affects pcie-qcom.c, so it looks like Stanimir should have
> been copied on this, but wasn't. Please include him on the next
> iteration.
I somehow missed the pcie-qcom.c standalone entry in MAINTAINERS because
the same file also appears on the general qcom entry. I'll add him on
v7. Hopefully that will improve the fortune of this series.
> This will also need to be updated to apply on v5.19-rc1:
>
> 03:21:47 ~/linux (next)$ git checkout -b wip/baruch-ipq6018-v6 v5.19-rc1
> Switched to a new branch 'wip/baruch-ipq6018-v6'
> 03:21:55 ~/linux (wip/baruch-ipq6018-v6)$ git am m/v6_20220207_baruch_pci_ipq6018_platform_support.mbx
> Applying: PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
> Applying: PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
> Applying: PCI: qcom: Add IPQ60xx support
> error: patch failed: drivers/pci/controller/dwc/pcie-qcom.c:1531
> error: drivers/pci/controller/dwc/pcie-qcom.c: patch does not apply
> Patch failed at 0003 PCI: qcom: Add IPQ60xx support
I'll rebase on v5.19-rc1.
baruch
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 16+ messages in thread