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From: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCHv3 19/27] PCI: mobiveil: disabled IB and OB windows set by bootloader
Date: Fri, 8 Feb 2019 18:12:12 +0530	[thread overview]
Message-ID: <CAFZiPx1B7iTKgyr4uRJDescLx+NRLdOhjBdMyCoYA2Hja6Xy2g@mail.gmail.com> (raw)
In-Reply-To: <20190129080926.36773-20-Zhiqiang.Hou@nxp.com>

On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Disabled all inbound and outbound windows before set up the windows
> in kernel, in case transactions match the window set by bootloader.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> V3:
>  - No change
>
>  .../controller/mobiveil/pcie-mobiveil-host.c   |  7 +++++++
>  .../pci/controller/mobiveil/pcie-mobiveil.c    | 18 ++++++++++++++++++
>  .../pci/controller/mobiveil/pcie-mobiveil.h    |  2 ++
>  3 files changed, 27 insertions(+)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index d1765d572f44..d028cdf31d0e 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>  {
>         u32 value, pab_ctrl, type;
>         struct resource_entry *win;
> +       int i;
> +
> +       /* Disable all inbound/outbound windows */
> +       for (i = 0; i < pcie->apio_wins; i++)
> +               mobiveil_pcie_disable_ob_win(pcie, i);
> +       for (i = 0; i < pcie->ppio_wins; i++)
> +               mobiveil_pcie_disable_ib_win(pcie, i);
>
>         /* setup bus numbers */
>         value = csr_readl(pcie, PCI_PRIMARY_BUS);
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> index 370658d6546d..49d471b75925 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> @@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
>
>         return -ETIMEDOUT;
>  }
> +
> +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
> +{
> +       u32 val;
> +
> +       val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
> +       val &= ~(1 << AMAP_CTRL_EN_SHIFT);
> +       csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
> +}
> +
> +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
> +{
> +       u32 val;
> +
> +       val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
> +       val &= ~(1 << WIN_ENABLE_SHIFT);
> +       csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
> +}
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index eb4cb61291a8..81685840b378 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
>                         u64 pci_addr, u32 type, u64 size);
>  void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
>                         u64 pci_addr, u32 type, u64 size);
> +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
> +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
>  u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
>  void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
>
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

  reply	other threads:[~2019-02-08 12:39 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-29  8:08 [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-01-29  8:08 ` [PATCHv3 01/27] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-02-05  5:39   ` Subrahmanya Lingappa
2019-02-05 17:43     ` Lorenzo Pieralisi
2019-02-06 10:59       ` Subrahmanya Lingappa
2019-01-29  8:08 ` [PATCHv3 02/27] PCI: mobiveil: format the code without function change Z.q. Hou
2019-02-05  5:48   ` Subrahmanya Lingappa
2019-02-18  7:03     ` Z.q. Hou
2019-01-29  8:08 ` [PATCHv3 03/27] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-02-05  5:53   ` Subrahmanya Lingappa
2019-01-29  8:08 ` [PATCHv3 04/27] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-02-05  6:05   ` Subrahmanya Lingappa
2019-02-18  7:03     ` Z.q. Hou
2019-01-29  8:09 ` [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-02-05  6:06   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 06/27] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-02-05  6:07   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 07/27] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-02-05  6:08   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-02-05  6:08   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-02-05  6:10   ` Subrahmanya Lingappa
2019-02-18  7:07     ` Z.q. Hou
2019-01-29  8:09 ` [PATCHv3 10/27] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-02-05  6:11   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 11/27] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-02-05  6:11   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 12/27] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-02-05  6:12   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 13/27] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-02-08 12:30   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-02-08 12:31   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 15/27] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-02-08 12:32   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 16/27] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-02-08 12:37   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-02-08 12:41   ` Subrahmanya Lingappa
2019-02-08 14:13     ` Bjorn Helgaas
2019-02-18  7:15       ` Z.q. Hou
2019-02-18  7:04     ` Z.q. Hou
2019-01-29  8:10 ` [PATCHv3 18/27] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-02-08 12:41   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 19/27] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-02-08 12:42   ` Subrahmanya Lingappa [this message]
2019-01-29  8:10 ` [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-02-08 12:44   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 21/27] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-02-08 12:46   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 22/27] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-01-30 18:49   ` Rob Herring
2019-01-29  8:10 ` [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-02-08 12:49   ` Subrahmanya Lingappa
2019-02-18  7:05     ` Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 24/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-02-08 12:52   ` Subrahmanya Lingappa
2019-02-18  7:10     ` Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 25/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-02-08 12:53   ` Subrahmanya Lingappa
2019-02-18  7:14     ` Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 26/27] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 27/27] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-01-29 11:39 ` [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Lorenzo Pieralisi
     [not found]   ` <CAFZiPx002HED+YH2GysS7a7uoEDQuHGjxa_CQtwb9nSDH-XNuA@mail.gmail.com>
2019-02-04 16:13     ` Lorenzo Pieralisi
2019-02-04 16:51       ` Subrahmanya Lingappa
2019-01-30 15:34 ` Bjorn Helgaas

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