* [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port @ 2022-03-09 12:00 Bharat Kumar Gogada 2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada 2022-03-09 12:00 ` [PATCH v3 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada 0 siblings, 2 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-09 12:00 UTC (permalink / raw) To: linux-pci, linux-kernel, devicetree Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additonal register bit to enable and handle legacy interrupts. Changes in v3: - consistency in is_cpm5 flag check expression. Bharat Kumar Gogada (2): dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- 2 files changed, 72 insertions(+), 8 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-09 12:00 [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada @ 2022-03-09 12:00 ` Bharat Kumar Gogada 2022-03-10 13:24 ` Krzysztof Kozlowski ` (2 more replies) 2022-03-09 12:00 ` [PATCH v3 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada 1 sibling, 3 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-09 12:00 UTC (permalink / raw) To: linux-pci, linux-kernel, devicetree Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Add support for YAML schemas documentation for Versal CPM5 Root Port driver. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> --- .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 32f4641085bc..97c7229d7f91 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -14,17 +14,21 @@ allOf: properties: compatible: - const: xlnx,versal-cpm-host-1.00 + contains: + enum: + - xlnx,versal-cpm-host-1.00 + - xlnx,versal-cpm5-host-1.00 reg: - items: - - description: Configuration space region and bridge registers. - - description: CPM system level control and status registers. + description: | + Should contain cpm_slcr, cfg registers location and length. + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. + minItems: 2 + maxItems: 3 reg-names: - items: - - const: cfg - - const: cpm_slcr + minItems: 2 + maxItems: 3 interrupts: maxItems: 1 @@ -95,4 +99,33 @@ examples: interrupt-controller; }; }; + + cpm5_pcie: pcie@fcdd0000 { + compatible = "xlnx,versal-cpm5-host-1.00"; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <0 72 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_1 0>, + <0 0 0 2 &pcie_intc_1 1>, + <0 0 0 3 &pcie_intc_1 2>, + <0 0 0 4 &pcie_intc_1 3>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x00 0xfcdd0000 0x00 0x1000>, + <0x06 0x00000000 0x00 0x1000000>, + <0x00 0xfce20000 0x00 0x1000000>; + reg-names = "cpm_slcr", "cfg", "cpm_csr"; + + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada @ 2022-03-10 13:24 ` Krzysztof Kozlowski 2022-03-14 4:32 ` Bharat Kumar Gogada 2022-03-10 13:33 ` Krzysztof Kozlowski 2022-03-10 19:13 ` Rob Herring 2 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-03-10 13:24 UTC (permalink / raw) To: Bharat Kumar Gogada, linux-pci, linux-kernel, devicetree Cc: lorenzo.pieralisi, bhelgaas, michals, robh On 09/03/2022 13:00, Bharat Kumar Gogada wrote: > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Add support for YAML schemas documentation for Versal CPM5 Root Port driver. > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > --- > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > 1 file changed, 40 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index 32f4641085bc..97c7229d7f91 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -14,17 +14,21 @@ allOf: > > properties: > compatible: > - const: xlnx,versal-cpm-host-1.00 > + contains: > + enum: > + - xlnx,versal-cpm-host-1.00 > + - xlnx,versal-cpm5-host-1.00 > > reg: > - items: > - - description: Configuration space region and bridge registers. > - - description: CPM system level control and status registers. > + description: | > + Should contain cpm_slcr, cfg registers location and length. > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. > + minItems: 2 > + maxItems: 3 You removed here list of items, which should stay. See also https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/example-schema.yaml#L91 how to do it. > > reg-names: > - items: > - - const: cfg > - - const: cpm_slcr > + minItems: 2 > + maxItems: 3 The same. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-10 13:24 ` Krzysztof Kozlowski @ 2022-03-14 4:32 ` Bharat Kumar Gogada 0 siblings, 0 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-14 4:32 UTC (permalink / raw) To: Krzysztof Kozlowski, linux-pci, linux-kernel, devicetree Cc: lorenzo.pieralisi, bhelgaas, Michal Simek, robh > On 09/03/2022 13:00, Bharat Kumar Gogada wrote: > > Xilinx Versal Premium series has CPM5 block which supports Root Port > > functioning at Gen5 speed. > > > > Add support for YAML schemas documentation for Versal CPM5 Root Port > driver. > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > > --- > > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > > 1 file changed, 40 insertions(+), 7 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > index 32f4641085bc..97c7229d7f91 100644 > > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > @@ -14,17 +14,21 @@ allOf: > > > > properties: > > compatible: > > - const: xlnx,versal-cpm-host-1.00 > > + contains: > > + enum: > > + - xlnx,versal-cpm-host-1.00 > > + - xlnx,versal-cpm5-host-1.00 > > > > reg: > > - items: > > - - description: Configuration space region and bridge registers. > > - - description: CPM system level control and status registers. > > + description: | > > + Should contain cpm_slcr, cfg registers location and length. > > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. > > + minItems: 2 > > + maxItems: 3 > > You removed here list of items, which should stay. See also > https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bi > ndings/example-schema.yaml#L91 > how to do it. > > > > > reg-names: > > - items: > > - - const: cfg > > - - const: cpm_slcr > > + minItems: 2 > > + maxItems: 3 > > The same. > > Thanks Krzysztof, will fix this in next patch. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada 2022-03-10 13:24 ` Krzysztof Kozlowski @ 2022-03-10 13:33 ` Krzysztof Kozlowski 2022-03-10 19:13 ` Rob Herring 2 siblings, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-03-10 13:33 UTC (permalink / raw) To: Bharat Kumar Gogada, linux-pci, linux-kernel, devicetree Cc: lorenzo.pieralisi, bhelgaas, michals, robh On 09/03/2022 13:00, Bharat Kumar Gogada wrote: > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Add support for YAML schemas documentation for Versal CPM5 Root Port driver. > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > --- > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > 1 file changed, 40 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index 32f4641085bc..97c7229d7f91 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -14,17 +14,21 @@ allOf: > > properties: > compatible: > - const: xlnx,versal-cpm-host-1.00 > + contains: > + enum: > + - xlnx,versal-cpm-host-1.00 > + - xlnx,versal-cpm5-host-1.00 > > reg: > - items: > - - description: Configuration space region and bridge registers. > - - description: CPM system level control and status registers. > + description: | > + Should contain cpm_slcr, cfg registers location and length. > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. > + minItems: 2 > + maxItems: 3 > > reg-names: > - items: > - - const: cfg > - - const: cpm_slcr > + minItems: 2 > + maxItems: 3 > One more thought - it seems three items are required on cpm5, so you miss later proper allOf-if: which enforces this. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada 2022-03-10 13:24 ` Krzysztof Kozlowski 2022-03-10 13:33 ` Krzysztof Kozlowski @ 2022-03-10 19:13 ` Rob Herring 2022-03-14 4:33 ` Bharat Kumar Gogada 2 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2022-03-10 19:13 UTC (permalink / raw) To: Bharat Kumar Gogada Cc: PCI, linux-kernel, devicetree, Lorenzo Pieralisi, Bjorn Helgaas, Michal Simek On Wed, Mar 9, 2022 at 6:00 AM Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> wrote: > > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Add support for YAML schemas documentation for Versal CPM5 Root Port driver. > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > --- > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > 1 file changed, 40 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index 32f4641085bc..97c7229d7f91 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -14,17 +14,21 @@ allOf: > > properties: > compatible: > - const: xlnx,versal-cpm-host-1.00 > + contains: Nope. That means 'compatible = "foo", "xlnx,versal-cpm-host-1.00", "bar";' would be valid. > + enum: > + - xlnx,versal-cpm-host-1.00 > + - xlnx,versal-cpm5-host-1.00 Where does 1.00 come from? My guess is you or whoever did the original binding just made it up. Version numbers are only used when they correspond to something documented for the h/w. In the case of Xilinx, that should be soft IP (which I assume has versioned releases) and nothing else. If 'versal' is not specific enough to identify a specific SoC, then add to it. > reg: > - items: > - - description: Configuration space region and bridge registers. > - - description: CPM system level control and status registers. > + description: | > + Should contain cpm_slcr, cfg registers location and length. > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. Not an improvement in defining what each entry is. > + minItems: 2 > + maxItems: 3 ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-10 19:13 ` Rob Herring @ 2022-03-14 4:33 ` Bharat Kumar Gogada 0 siblings, 0 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-14 4:33 UTC (permalink / raw) To: Rob Herring Cc: PCI, linux-kernel, devicetree, Lorenzo Pieralisi, Bjorn Helgaas, Michal Simek > On Wed, Mar 9, 2022 at 6:00 AM Bharat Kumar Gogada > <bharat.kumar.gogada@xilinx.com> wrote: > > > > Xilinx Versal Premium series has CPM5 block which supports Root Port > > functioning at Gen5 speed. > > > > Add support for YAML schemas documentation for Versal CPM5 Root Port > driver. > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > > --- > > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > > 1 file changed, 40 insertions(+), 7 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > index 32f4641085bc..97c7229d7f91 100644 > > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > @@ -14,17 +14,21 @@ allOf: > > > > properties: > > compatible: > > - const: xlnx,versal-cpm-host-1.00 > > + contains: > > Nope. That means 'compatible = "foo", "xlnx,versal-cpm-host-1.00", "bar";' > would be valid. > > > + enum: > > + - xlnx,versal-cpm-host-1.00 > > + - xlnx,versal-cpm5-host-1.00 > > Where does 1.00 come from? My guess is you or whoever did the original > binding just made it up. Version numbers are only used when they > correspond to something documented for the h/w. In the case of Xilinx, that > should be soft IP (which I assume has versioned releases) and nothing else. If > 'versal' is not specific enough to identify a specific SoC, then add to it. > Agreed, will remove version numbers. > > > reg: > > - items: > > - - description: Configuration space region and bridge registers. > > - - description: CPM system level control and status registers. > > + description: | > > + Should contain cpm_slcr, cfg registers location and length. > > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. > > Not an improvement in defining what each entry is. Agreed, will fix this in next patch. regards, Bharat ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port 2022-03-09 12:00 [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada 2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada @ 2022-03-09 12:00 ` Bharat Kumar Gogada 1 sibling, 0 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-09 12:00 UTC (permalink / raw) To: linux-pci, linux-kernel, devicetree Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additional register bit to enable and handle legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> --- drivers/pci/controller/pcie-xilinx-cpm.c | 33 +++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index c7cd44ed4dfc..c8bf22718614 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -35,6 +35,10 @@ #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 +#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 +#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) + /* Interrupt registers definitions */ #define XILINX_CPM_PCIE_INTR_LINK_DOWN 0 #define XILINX_CPM_PCIE_INTR_HOT_RESET 3 @@ -109,6 +113,7 @@ * @intx_irq: legacy interrupt number * @irq: Error interrupt number * @lock: lock protecting shared register access + * @is_cpm5: value to check cpm version */ struct xilinx_cpm_pcie { struct device *dev; @@ -120,6 +125,7 @@ struct xilinx_cpm_pcie { int intx_irq; int irq; raw_spinlock_t lock; + bool is_cpm5; }; static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) @@ -285,6 +291,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) generic_handle_domain_irq(port->cpm_domain, i); pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); + if (port->is_cpm5) { + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); + if (val) + writel_relaxed(val, + port->cpm_base + + XILINX_CPM_PCIE_IR_STATUS); + } + /* * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to * CPM SLCR block. @@ -484,6 +498,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) */ writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); + + if (port->is_cpm5) { + writel(XILINX_CPM_PCIE_IR_LOCAL, + port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); + } + /* Enable the Bridge enable bit */ pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | XILINX_CPM_PCIE_REG_RPSC_BEN, @@ -504,6 +524,9 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, struct platform_device *pdev = to_platform_device(dev); struct resource *res; + port->is_cpm5 = of_device_is_compatible(dev->of_node, + "xlnx,versal-cpm5-host-1.00"); + port->cpm_base = devm_platform_ioremap_resource_byname(pdev, "cpm_slcr"); if (IS_ERR(port->cpm_base)) @@ -518,7 +541,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, if (IS_ERR(port->cfg)) return PTR_ERR(port->cfg); - port->reg_base = port->cfg->win; + if (port->is_cpm5) { + port->reg_base = devm_platform_ioremap_resource_byname(pdev, + "cpm_csr"); + if (IS_ERR(port->reg_base)) + return PTR_ERR(port->reg_base); + } else { + port->reg_base = port->cfg->win; + } return 0; } @@ -593,6 +623,7 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) static const struct of_device_id xilinx_cpm_pcie_of_match[] = { { .compatible = "xlnx,versal-cpm-host-1.00", }, + { .compatible = "xlnx,versal-cpm5-host-1.00", }, {} }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-03-14 4:33 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-09 12:00 [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada 2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada 2022-03-10 13:24 ` Krzysztof Kozlowski 2022-03-14 4:32 ` Bharat Kumar Gogada 2022-03-10 13:33 ` Krzysztof Kozlowski 2022-03-10 19:13 ` Rob Herring 2022-03-14 4:33 ` Bharat Kumar Gogada 2022-03-09 12:00 ` [PATCH v3 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
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