[PATCH v7 0/6] arm64: dts: qcom: sm6125: UFS and xiaomi-laurel-sprout support

[PATCH v7 0/6] arm64: dts: qcom: sm6125: UFS and xiaomi-laurel-sprout support

[Lux Aliaga]

Introduce Universal Flash Storage support on SM6125 and add support for the Xiaomi Mi A3 based on the former platform.

Changes since v6:
- Add struct for v3-660 UFS PHY offsets and replace the v5 offsets in sm6115 UFS PHY config to these
- Set ufs_mem_phy reg size to 0xdb8 in sm6125.dtsi
- Drop "#address-cells" and "#size-cells" properties on reserved-memory node in xiaomi-laurel-sprout dts
- Move "status" last on &pon_resin node in xiaomi-laurel-sprout dts
- Modify "&pm6125_gpio" pointer to "&pm6125_gpios" in xiaomi-laurel-sprout dts

v6: https://lore.kernel.org/linux-devicetree/20230108195336.388349-1-they@mint.lgbt/
v5: https://lore.kernel.org/linux-devicetree/20221231222420.75233-2-they@mint.lgbt/




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[PATCH v7 1/6] dt-bindings: ufs: qcom: Add SM6125 compatible string

[Lux Aliaga]

Document the compatible for UFS found on the SM6125.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index b517d76215e3..42422f3471b3 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -29,6 +29,7 @@ properties:
           - qcom,sc8280xp-ufshc
           - qcom,sdm845-ufshc
           - qcom,sm6115-ufshc
+          - qcom,sm6125-ufshc
           - qcom,sm6350-ufshc
           - qcom,sm8150-ufshc
           - qcom,sm8250-ufshc
@@ -185,6 +186,7 @@ allOf:
           contains:
             enum:
               - qcom,sm6115-ufshc
+              - qcom,sm6125-ufshc
     then:
       properties:
         clocks:
-- 
2.39.2


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Re: [PATCH v7 1/6] dt-bindings: ufs: qcom: Add SM6125 compatible string

[Krzysztof Kozlowski]

On 06/03/2023 18:08, Lux Aliaga wrote:
> Document the compatible for UFS found on the SM6125.
> 
> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> Reviewed-by: Martin Botka <martin.botka@somainline.org>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

I have trouble understanding why this patch was not applied... I don't
know, maybe it should not be send with other patches.

Or maybe Rob can pick it up?

Best regards,
Krzysztof


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[PATCH v7 2/6] dt-bindings: phy: Add QMP UFS PHY compatible for SM6125

[Lux Aliaga]

Document the QMP UFS PHY compatible for SM6125.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Acked-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index dde86a19f792..a7af57931f32 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,sc8280xp-qmp-ufs-phy
+      - qcom,sm6125-qmp-ufs-phy
 
   reg:
     maxItems: 1
-- 
2.39.2


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[PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Lux Aliaga]

The SM6125 UFS PHY is compatible with the one from SM6115. Add a
compatible for it and modify the config from SM6115 to make them
compatible with the SC8280XP binding

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 318eea35b972..44c29fdfc551 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
 	"vdda-phy", "vdda-pll",
 };
 
+static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
+	.serdes		= 0,
+	.pcs		= 0xc00,
+	.tx		= 0x400,
+	.rx		= 0x600,
+};
+
 static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
 	.serdes		= 0,
 	.pcs		= 0xc00,
@@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
 	.lanes			= 1,
 
+	.offsets		= &qmp_ufs_offsets_v3_660,
+
 	.serdes_tbl		= sm6115_ufsphy_serdes_tbl,
 	.serdes_tbl_num		= ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
 	.tx_tbl			= sm6115_ufsphy_tx_tbl,
@@ -1172,6 +1181,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
 	}, {
 		.compatible = "qcom,sm6115-qmp-ufs-phy",
 		.data = &sm6115_ufsphy_cfg,
+	}, {
+		.compatible = "qcom,sm6125-qmp-ufs-phy",
+		.data = &sm6115_ufsphy_cfg,
 	}, {
 		.compatible = "qcom,sm6350-qmp-ufs-phy",
 		.data = &sdm845_ufsphy_cfg,
-- 
2.39.2


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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Konrad Dybcio]

On 6.03.2023 18:08, Lux Aliaga wrote:
> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
> compatible for it and modify the config from SM6115 to make them
> compatible with the SC8280XP binding
> 
> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> Reviewed-by: Martin Botka <martin.botka@somainline.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 318eea35b972..44c29fdfc551 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>  	"vdda-phy", "vdda-pll",
>  };
>  
> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
> +	.serdes		= 0,
> +	.pcs		= 0xc00,
> +	.tx		= 0x400,
> +	.rx		= 0x600,
> +};
> +
>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>  	.serdes		= 0,
>  	.pcs		= 0xc00,
> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>  	.lanes			= 1,
>  
> +	.offsets		= &qmp_ufs_offsets_v3_660,
Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
which specify the regions separately (old binding style)?

Konrad
> +
>  	.serdes_tbl		= sm6115_ufsphy_serdes_tbl,
>  	.serdes_tbl_num		= ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
>  	.tx_tbl			= sm6115_ufsphy_tx_tbl,
> @@ -1172,6 +1181,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
>  	}, {
>  		.compatible = "qcom,sm6115-qmp-ufs-phy",
>  		.data = &sm6115_ufsphy_cfg,
> +	}, {
> +		.compatible = "qcom,sm6125-qmp-ufs-phy",
> +		.data = &sm6115_ufsphy_cfg,
>  	}, {
>  		.compatible = "qcom,sm6350-qmp-ufs-phy",
>  		.data = &sdm845_ufsphy_cfg,

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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Johan Hovold]

On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
> 
> 
> On 6.03.2023 18:08, Lux Aliaga wrote:
> > The SM6125 UFS PHY is compatible with the one from SM6115. Add a
> > compatible for it and modify the config from SM6115 to make them
> > compatible with the SC8280XP binding
> > 
> > Signed-off-by: Lux Aliaga <they@mint.lgbt>
> > Reviewed-by: Martin Botka <martin.botka@somainline.org>
> > ---
> >  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > index 318eea35b972..44c29fdfc551 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
> >  	"vdda-phy", "vdda-pll",
> >  };
> >  
> > +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
> > +	.serdes		= 0,
> > +	.pcs		= 0xc00,
> > +	.tx		= 0x400,
> > +	.rx		= 0x600,
> > +};
> > +
> >  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
> >  	.serdes		= 0,
> >  	.pcs		= 0xc00,
> > @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> >  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> >  	.lanes			= 1,
> >  
> > +	.offsets		= &qmp_ufs_offsets_v3_660,
> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
> which specify the regions separately (old binding style)?

No, that should work fine.

But looks like this series needs to be rebased on 6.3-rc1 as these
offsets are now already set in mainline.

Johan

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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Konrad Dybcio]

On 8.03.2023 12:02, Johan Hovold wrote:
> On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
>>
>>
>> On 6.03.2023 18:08, Lux Aliaga wrote:
>>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
>>> compatible for it and modify the config from SM6115 to make them
>>> compatible with the SC8280XP binding
>>>
>>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>>> ---
>>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>>>  1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> index 318eea35b972..44c29fdfc551 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>>>  	"vdda-phy", "vdda-pll",
>>>  };
>>>  
>>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
>>> +	.serdes		= 0,
>>> +	.pcs		= 0xc00,
>>> +	.tx		= 0x400,
>>> +	.rx		= 0x600,
>>> +};
>>> +
>>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>>>  	.serdes		= 0,
>>>  	.pcs		= 0xc00,
>>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>>>  	.lanes			= 1,
>>>  
>>> +	.offsets		= &qmp_ufs_offsets_v3_660,
>> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
>> which specify the regions separately (old binding style)?
> 
> No, that should work fine.
So do you think the SM6115 binding could be updated too? Or should
we keep it as-is for ABI purposes?..

> 
> But looks like this series needs to be rebased on 6.3-rc1 as these
> offsets are now already set in mainline.
..Or did you do that already and I can't find it?

Konrad
> 
> Johan

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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Johan Hovold]

On Wed, Mar 08, 2023 at 12:15:39PM +0100, Konrad Dybcio wrote:
> 
> 
> On 8.03.2023 12:02, Johan Hovold wrote:
> > On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
> >>
> >>
> >> On 6.03.2023 18:08, Lux Aliaga wrote:
> >>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
> >>> compatible for it and modify the config from SM6115 to make them
> >>> compatible with the SC8280XP binding
> >>>
> >>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> >>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
> >>> ---
> >>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
> >>>  1 file changed, 12 insertions(+)
> >>>
> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>> index 318eea35b972..44c29fdfc551 100644
> >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
> >>>  	"vdda-phy", "vdda-pll",
> >>>  };
> >>>  
> >>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
> >>> +	.serdes		= 0,
> >>> +	.pcs		= 0xc00,
> >>> +	.tx		= 0x400,
> >>> +	.rx		= 0x600,
> >>> +};
> >>> +
> >>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
> >>>  	.serdes		= 0,
> >>>  	.pcs		= 0xc00,
> >>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> >>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> >>>  	.lanes			= 1,
> >>>  
> >>> +	.offsets		= &qmp_ufs_offsets_v3_660,
> >> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
> >> which specify the regions separately (old binding style)?
> > 
> > No, that should work fine.
> So do you think the SM6115 binding could be updated too? Or should
> we keep it as-is for ABI purposes?..

They could be and the possibility has been raised. I think it may be
more important to convert the old combo-phy binding (it's on my list,
but I keep getting preempted), but at some point we can get rid of the
legacy UFS binding as well.

> > But looks like this series needs to be rebased on 6.3-rc1 as these
> > offsets are now already set in mainline.
> ..Or did you do that already and I can't find it?

It seems a previous version of this patch was merged almost two months
ago.

	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")

Not sure what failed here.

Johan

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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Konrad Dybcio]

On 8.03.2023 12:23, Johan Hovold wrote:
> On Wed, Mar 08, 2023 at 12:15:39PM +0100, Konrad Dybcio wrote:
>>
>>
>> On 8.03.2023 12:02, Johan Hovold wrote:
>>> On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
>>>>
>>>>
>>>> On 6.03.2023 18:08, Lux Aliaga wrote:
>>>>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
>>>>> compatible for it and modify the config from SM6115 to make them
>>>>> compatible with the SC8280XP binding
>>>>>
>>>>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>>>>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>>>>> ---
>>>>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>>>>>  1 file changed, 12 insertions(+)
>>>>>
>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>> index 318eea35b972..44c29fdfc551 100644
>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>>>>>  	"vdda-phy", "vdda-pll",
>>>>>  };
>>>>>  
>>>>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
>>>>> +	.serdes		= 0,
>>>>> +	.pcs		= 0xc00,
>>>>> +	.tx		= 0x400,
>>>>> +	.rx		= 0x600,
>>>>> +};
>>>>> +
>>>>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>>>>>  	.serdes		= 0,
>>>>>  	.pcs		= 0xc00,
>>>>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>>>>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>>>>>  	.lanes			= 1,
>>>>>  
>>>>> +	.offsets		= &qmp_ufs_offsets_v3_660,
>>>> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
>>>> which specify the regions separately (old binding style)?
>>>
>>> No, that should work fine.
>> So do you think the SM6115 binding could be updated too? Or should
>> we keep it as-is for ABI purposes?..
> 
> They could be and the possibility has been raised. I think it may be
> more important to convert the old combo-phy binding (it's on my list,
> but I keep getting preempted), but at some point we can get rid of the
> legacy UFS binding as well.
Okay sounds good!

> 
>>> But looks like this series needs to be rebased on 6.3-rc1 as these
>>> offsets are now already set in mainline.
>> ..Or did you do that already and I can't find it?
> 
> It seems a previous version of this patch was merged almost two months
> ago.
> 
> 	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")
> 
> Not sure what failed here.
My eyes :)

Konrad
> 
> Johan

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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Lux Aliaga]

On 8 March 2023 08:23:57 GMT-03:00, Johan Hovold <johan@kernel.org> wrote:
>On Wed, Mar 08, 2023 at 12:15:39PM +0100, Konrad Dybcio wrote:
>> 
>> 
>> On 8.03.2023 12:02, Johan Hovold wrote:
>> > On Wed, Mar 08, 2023 at 11:09:48AM +0100, Konrad Dybcio wrote:
>> >>
>> >>
>> >> On 6.03.2023 18:08, Lux Aliaga wrote:
>> >>> The SM6125 UFS PHY is compatible with the one from SM6115. Add a
>> >>> compatible for it and modify the config from SM6115 to make them
>> >>> compatible with the SC8280XP binding
>> >>>
>> >>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>> >>> Reviewed-by: Martin Botka <martin.botka@somainline.org>
>> >>> ---
>> >>>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 12 ++++++++++++
>> >>>  1 file changed, 12 insertions(+)
>> >>>
>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> >>> index 318eea35b972..44c29fdfc551 100644
>> >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> >>> @@ -620,6 +620,13 @@ static const char * const qmp_phy_vreg_l[] = {
>> >>>  	"vdda-phy", "vdda-pll",
>> >>>  };
>> >>>  
>> >>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v3_660 = {
>> >>> +	.serdes		= 0,
>> >>> +	.pcs		= 0xc00,
>> >>> +	.tx		= 0x400,
>> >>> +	.rx		= 0x600,
>> >>> +};
>> >>> +
>> >>>  static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
>> >>>  	.serdes		= 0,
>> >>>  	.pcs		= 0xc00,
>> >>> @@ -693,6 +700,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>> >>>  static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
>> >>>  	.lanes			= 1,
>> >>>  
>> >>> +	.offsets		= &qmp_ufs_offsets_v3_660,
>> >> Will this not trigger OOB r/w for the users of qcom,sm6115-smp-ufs-phy
>> >> which specify the regions separately (old binding style)?
>> > 
>> > No, that should work fine.
>> So do you think the SM6115 binding could be updated too? Or should
>> we keep it as-is for ABI purposes?..
>
>They could be and the possibility has been raised. I think it may be
>more important to convert the old combo-phy binding (it's on my list,
>but I keep getting preempted), but at some point we can get rid of the
>legacy UFS binding as well.
>
>> > But looks like this series needs to be rebased on 6.3-rc1 as these
>> > offsets are now already set in mainline.
>> ..Or did you do that already and I can't find it?
>
>It seems a previous version of this patch was merged almost two months
>ago.
>
>	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")
>
>Not sure what failed here.
>
>Johan
Yes, but it received some comments regarding using v5 offsets instead of v3-660. I could spin off this change into a new patch if necessary.

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Re: [PATCH v7 3/6] phy: qcom-qmp: Add SM6125 UFS PHY support

[Johan Hovold]

On Wed, Mar 08, 2023 at 08:37:48AM -0300, Lux Aliaga wrote:
> On 8 March 2023 08:23:57 GMT-03:00, Johan Hovold <johan@kernel.org> wrote:

> >It seems a previous version of this patch was merged almost two months
> >ago.
> >
> >	9b9e29af984c ("phy: qcom-qmp: Add SM6125 UFS PHY support")
> >
> >Not sure what failed here.

> Yes, but it received some comments regarding using v5 offsets instead
> of v3-660. I could spin off this change into a new patch if necessary.

Once a patch has been applied, you generally need to do any further
changes incrementally on top.

It seems Dmitry renamed the struct himself after the patch was applied
in this case.

Johan

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[PATCH v7 4/6] arm64: dts: qcom: sm6125: Add UFS nodes

[Lux Aliaga]

Adds a UFS host controller node and its corresponding PHY to
the sm6125 platform.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 62 ++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index df5453fcf2b9..7384d88f44cc 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -511,6 +511,68 @@ sdhc_2: mmc@4784000 {
 			status = "disabled";
 		};
 
+		ufs_mem_hc: ufs@4804000 {
+			compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
+			reg-names = "std", "ice";
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "ice_core_clk";
+			freq-table-hz = <50000000 240000000>,
+					<0 0>,
+					<0 0>,
+					<37500000 150000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>,
+					<75000000 300000000>;
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+			#reset-cells = <1>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			lanes-per-direction = <1>;
+
+			iommus = <&apps_smmu 0x200 0x0>;
+
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@4807000 {
+			compatible = "qcom,sm6125-qmp-ufs-phy";
+			reg = <0x04807000 0xdb8>;
+
+			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+			clock-names = "ref", "ref_aux";
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		gpi_dma0: dma-controller@4a00000 {
 			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
 			reg = <0x04a00000 0x60000>;
-- 
2.39.2


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Re: [PATCH v7 4/6] arm64: dts: qcom: sm6125: Add UFS nodes

[Konrad Dybcio]

On 6.03.2023 18:08, Lux Aliaga wrote:
> Adds a UFS host controller node and its corresponding PHY to
> the sm6125 platform.
> 
> Signed-off-by: Lux Aliaga <they@mint.lgbt>
> ---
[...]

> +		ufs_mem_phy: phy@4807000 {
> +			compatible = "qcom,sm6125-qmp-ufs-phy";
> +			reg = <0x04807000 0xdb8>;
> +
> +			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +			clock-names = "ref", "ref_aux";
Please wrap it into

clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
	 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref",
	      "ref_aux";


and resolve the binding/offset situation. Otherwise, LGTM!

Konrad
> +
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
> +
> +			power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
> +		};
> +
>  		gpi_dma0: dma-controller@4a00000 {
>  			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
>  			reg = <0x04a00000 0x60000>;

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[PATCH v7 5/6] dt-bindings: arm: qcom: Document xiaomi,laurel-sprout board

[Lux Aliaga]

Document the Xiaomi Mi A3 (xiaomi-laurel-sprout) smartphone which is
based on the Snapdragon 665 SoC.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 27063a045bd0..4923dafb5d7a 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -793,6 +793,7 @@ properties:
       - items:
           - enum:
               - sony,pdx201
+              - xiaomi,laurel-sprout
           - const: qcom,sm6125
 
       - items:
-- 
2.39.2


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[PATCH v7 6/6] arm64: dts: qcom: sm6125: Initial support for xiaomi-laurel-sprout

[Lux Aliaga]

Add support for the Xiaomi Mi A3 (xiaomi-laurel-sprout). Here's a
summary on what's defined.

- dmesg output to bootloader preconfigured display
- USB
- UFS
- SD card
- SMD RPM regulators
- Volume Up, Down and Power buttons
- Thermistors

Signed-off-by: Lux Aliaga <they@mint.lgbt>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../dts/qcom/sm6125-xiaomi-laurel-sprout.dts  | 421 ++++++++++++++++++
 2 files changed, 422 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 3e79496292e7..2b2a0170db14 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -157,6 +157,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-lenovo-yoga-c630.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-samsung-w737.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm4250-oneplus-billie2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6125-sony-xperia-seine-pdx201.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sm6125-xiaomi-laurel-sprout.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6350-sony-xperia-lena-pdx213.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6375-sony-xperia-murray-pdx225.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm7225-fairphone-fp4.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts
new file mode 100644
index 000000000000..b1038eb8cebc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Lux Aliaga <they@mint.lgbt>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "sm6125.dtsi"
+#include "pm6125.dtsi"
+
+/ {
+	model = "Xiaomi Mi A3";
+	compatible = "xiaomi,laurel-sprout", "qcom,sm6125";
+	chassis-type = "handset";
+
+	/* required for bootloader to select correct board */
+	qcom,msm-id = <394 0>; /* sm6125 v1 */
+	qcom,board-id = <11 0>;
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@5c000000 {
+			compatible = "simple-framebuffer";
+			reg = <0 0x5c000000 0 (1560 * 720 * 4)>;
+			width = <720>;
+			height = <1560>;
+			stride = <(720 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	reserved-memory {
+		debug_mem: debug@ffb00000 {
+			reg = <0x0 0xffb00000 0x0 0xc0000>;
+			no-map;
+		};
+
+		last_log_mem: lastlog@ffbc0000 {
+			reg = <0x0 0xffbc0000 0x0 0x80000>;
+			no-map;
+		};
+
+		pstore_mem: ramoops@ffc00000 {
+			compatible = "ramoops";
+			reg = <0x0 0xffc40000 0x0 0xc0000>;
+			record-size = <0x1000>;
+			console-size = <0x40000>;
+			msg-size = <0x20000 0x20000>;
+		};
+
+		cmdline_mem: memory@ffd00000 {
+			reg = <0x0 0xffd40000 0x0 0x1000>;
+			no-map;
+		};
+	};
+
+	extcon_usb: usb-id {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&vol_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	thermal-zones {
+		rf-pa0-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&pm6125_adc_tm 0>;
+
+			trips {
+				active-config0 {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		quiet-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <5000>;
+			thermal-sensors = <&pm6125_adc_tm 1>;
+
+			trips {
+				active-config0 {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		xo-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&pm6125_adc_tm 2>;
+
+			trips {
+				active-config0 {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&hsusb_phy1 {
+	vdd-supply = <&vreg_l7a>;
+	vdda-pll-supply = <&vreg_l10a>;
+	vdda-phy-dpdm-supply = <&vreg_l15a>;
+	status = "okay";
+};
+
+&pm6125_adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>;
+
+	adc-chan@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "rf_pa0_therm";
+	};
+
+	adc-chan@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "quiet_therm";
+	};
+
+	adc-chan@52 {
+		reg = <ADC5_GPIO1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "camera_flash_therm";
+	};
+
+	adc-chan@54 {
+		reg = <ADC5_GPIO3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "emmc_ufs_therm";
+	};
+};
+
+&pm6125_adc_tm {
+	status = "okay";
+
+	rf-pa0-therm@0 {
+		reg = <0>;
+		io-channels = <&pm6125_adc ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	quiet-therm@1 {
+		reg = <1>;
+		io-channels = <&pm6125_adc ADC5_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	xo-therm@2 {
+		reg = <2>;
+		io-channels = <&pm6125_adc ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+};
+
+&pm6125_gpios {
+	camera_flash_therm: camera-flash-therm-state {
+		pins = "gpio3";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		bias-high-impedance;
+	};
+
+	emmc_ufs_therm: emmc-ufs-therm-state {
+		pins = "gpio6";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		bias-high-impedance;
+	};
+
+	vol_up_n: vol-up-n-state {
+		pins = "gpio5";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		input-enable;
+		bias-pull-up;
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+	status = "okay";
+};
+
+&rpm_requests {
+	regulators-0 {
+		compatible = "qcom,rpm-pm6125-regulators";
+
+		vreg_s6a: s6 {
+			regulator-min-microvolt = <936000>;
+			regulator-max-microvolt = <1422000>;
+		};
+
+		vreg_l1a: l1 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1256000>;
+		};
+
+		vreg_l2a: l2 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1056000>;
+		};
+
+		vreg_l3a: l3 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1064000>;
+		};
+
+		vreg_l4a: l4 {
+			regulator-min-microvolt = <872000>;
+			regulator-max-microvolt = <976000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l5a: l5 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l6a: l6 {
+			regulator-min-microvolt = <576000>;
+			regulator-max-microvolt = <656000>;
+		};
+
+		vreg_l7a: l7 {
+			regulator-min-microvolt = <872000>;
+			regulator-max-microvolt = <976000>;
+		};
+
+		vreg_l8a: l8 {
+			regulator-min-microvolt = <400000>;
+			regulator-max-microvolt = <728000>;
+		};
+
+		vreg_l9a: l9 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1896000>;
+		};
+
+		vreg_l10a: l10 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1896000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l11a: l11 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1952000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l12a: l12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1996000>;
+		};
+
+		vreg_l13a: l13 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1832000>;
+		};
+
+		vreg_l14a: l14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+		};
+
+		vreg_l15a: l15 {
+			regulator-min-microvolt = <3104000>;
+			regulator-max-microvolt = <3232000>;
+		};
+
+		vreg_l16a: l16 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+		};
+
+		vreg_l17a: l17 {
+			regulator-min-microvolt = <1248000>;
+			regulator-max-microvolt = <1304000>;
+		};
+
+		vreg_l18a: l18 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1264000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l19a: l19 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <2952000>;
+		};
+
+		vreg_l20a: l20 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <2952000>;
+		};
+
+		vreg_l21a: l21 {
+			regulator-min-microvolt = <2600000>;
+			regulator-max-microvolt = <2856000>;
+		};
+
+		vreg_l22a: l22 {
+			regulator-min-microvolt = <2944000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l23a: l23 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+		};
+
+		vreg_l24a: l24 {
+			regulator-min-microvolt = <2944000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+		};
+	};
+};
+
+&sdc2_off_state {
+	sd-cd-pins {
+		pins = "gpio98";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&sdc2_on_state {
+	sd-cd-pins {
+		pins = "gpio98";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&vreg_l22a>;
+	vqmmc-supply = <&vreg_l5a>;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&tlmm {
+	gpio-reserved-ranges = <22 2>, <28 6>;
+};
+
+&ufs_mem_hc {
+	vcc-supply = <&vreg_l24a>;
+	vccq2-supply = <&vreg_l11a>;
+	vcc-max-microamp = <600000>;
+	vccq2-max-microamp = <600000>;
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l4a>;
+	vdda-pll-supply = <&vreg_l10a>;
+	vdda-phy-max-microamp = <51400>;
+	vdda-pll-max-microamp = <14200>;
+	vddp-ref-clk-supply = <&vreg_l18a>;
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc3 {
+	extcon = <&extcon_usb>;
+};
-- 
2.39.2


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Re: (subset) [PATCH v7 0/6] arm64: dts: qcom: sm6125: UFS and xiaomi-laurel-sprout support

[Bjorn Andersson]

On Mon, 6 Mar 2023 14:08:10 -0300, Lux Aliaga wrote:
> Introduce Universal Flash Storage support on SM6125 and add support for the Xiaomi Mi A3 based on the former platform.
> 
> Changes since v6:
> - Add struct for v3-660 UFS PHY offsets and replace the v5 offsets in sm6115 UFS PHY config to these
> - Set ufs_mem_phy reg size to 0xdb8 in sm6125.dtsi
> - Drop "#address-cells" and "#size-cells" properties on reserved-memory node in xiaomi-laurel-sprout dts
> - Move "status" last on &pon_resin node in xiaomi-laurel-sprout dts
> - Modify "&pm6125_gpio" pointer to "&pm6125_gpios" in xiaomi-laurel-sprout dts
> 
> [...]

Applied, thanks!

[4/6] arm64: dts: qcom: sm6125: Add UFS nodes
      commit: f8399e8a2f80adfac2e7f5dbe223eb428fdb6fe9
[6/6] arm64: dts: qcom: sm6125: Initial support for xiaomi-laurel-sprout
      commit: b76c8ceabe871470cee17990289e8dd39b96054e

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

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(no subject)

[Lux Aliaga]

Introduce Universal Flash Storage support on SM6125 and add support for the Xiaomi Mi A3 based on the former platform.

Changes since v6:
- Add struct for v3-660 UFS PHY offsets and modify sm6115 UFS PHY to use it
- Set ufs_mem_phy reg size to 0xdb8 in sm6125.dtsi
- Drop "#address-cells" and "#size-cells" properties on reserved-memory node in xiaomi-laurel-sprout dts
- Move "status" last on &pon_resin node in xiaomi-laurel-sprout dts
- Modify "&pm6125_gpio" pointer to "&pm6125_gpios" in xiaomi-laurel-sprout dts

v6: https://lore.kernel.org/linux-devicetree/20230108195336.388349-1-they@mint.lgbt/
v5: https://lore.kernel.org/linux-devicetree/20221231222420.75233-2-they@mint.lgbt/




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[PATCH v7 4/6] arm64: dts: qcom: sm6125: Add UFS nodes

[Lux Aliaga]

Adds a UFS host controller node and its corresponding PHY to
the sm6125 platform.

Signed-off-by: Lux Aliaga <they@mint.lgbt>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 62 ++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index df5453fcf2b9..7384d88f44cc 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -511,6 +511,68 @@ sdhc_2: mmc@4784000 {
 			status = "disabled";
 		};
 
+		ufs_mem_hc: ufs@4804000 {
+			compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
+			reg-names = "std", "ice";
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "ice_core_clk";
+			freq-table-hz = <50000000 240000000>,
+					<0 0>,
+					<0 0>,
+					<37500000 150000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>,
+					<75000000 300000000>;
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+			#reset-cells = <1>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			lanes-per-direction = <1>;
+
+			iommus = <&apps_smmu 0x200 0x0>;
+
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@4807000 {
+			compatible = "qcom,sm6125-qmp-ufs-phy";
+			reg = <0x04807000 0xdb8>;
+
+			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+			clock-names = "ref", "ref_aux";
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		gpi_dma0: dma-controller@4a00000 {
 			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
 			reg = <0x04a00000 0x60000>;
-- 
2.39.2


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