From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v4 03/10] drivers: clk: renesas: r9a07g044-cpg: Fix P1 Clock
Date: Sat, 26 Jun 2021 09:13:37 +0100 [thread overview]
Message-ID: <20210626081344.5783-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210626081344.5783-1-biju.das.jz@bp.renesas.com>
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions for P1.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3->v4
* No change.
v2->v3
* Added Geert's Rb tag
* changed divider table to dtable_1_32
v2:
* New patch
---
drivers/clk/renesas/r9a07g044-cpg.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index d5803fb1242e..d895c1cef1fa 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -30,8 +30,8 @@ enum clk_ids {
CLK_PLL2_DIV20,
CLK_PLL3,
CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_4,
CLK_PLL3_DIV4,
- CLK_PLL3_DIV8,
CLK_PLL4,
CLK_PLL5,
CLK_PLL5_DIV2,
@@ -67,15 +67,15 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
- DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
/* Core output clk */
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
- DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
+ DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
};
--
2.17.1
next prev parent reply other threads:[~2021-06-26 8:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-26 8:13 [PATCH v4 00/10] Update clock definitions Biju Das
2021-06-26 8:13 ` [PATCH v4 01/10] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-26 8:13 ` [PATCH v4 02/10] drivers: clk: renesas: r9a07g044-cpg: Rename divider table Biju Das
2021-06-26 8:13 ` Biju Das [this message]
2021-06-26 8:13 ` [PATCH v4 04/10] drivers: clk: renesas: r9a07g044-cpg: Add P2 Clock support Biju Das
2021-06-26 8:13 ` [PATCH v4 05/10] dt-bindings: clk: r9a07g044-cpg: Update clock/reset definitions Biju Das
2021-07-14 2:42 ` Rob Herring
2021-07-14 8:11 ` Geert Uytterhoeven
2021-06-26 8:13 ` [PATCH v4 06/10] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries Biju Das
2021-06-28 12:00 ` Geert Uytterhoeven
2021-06-26 8:13 ` [PATCH v4 07/10] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset Biju Das
2021-06-26 8:13 ` [PATCH v4 08/10] drivers: clk: renesas: r9a07g044-cpg: Add I2C clocks/resets Biju Das
2021-06-26 8:13 ` [PATCH v4 09/10] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks/resets Biju Das
2021-06-26 8:13 ` [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add I2C nodes Biju Das
2021-06-28 12:18 ` [PATCH v4 00/10] Update clock definitions Geert Uytterhoeven
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210626081344.5783-4-biju.das.jz@bp.renesas.com \
--to=biju.das.jz@bp.renesas.com \
--cc=Chris.Paterson2@renesas.com \
--cc=biju.das@bp.renesas.com \
--cc=geert+renesas@glider.be \
--cc=linux-clk@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).