From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
devicetree@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: [PATCH v4 07/10] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset
Date: Sat, 26 Jun 2021 09:13:41 +0100 [thread overview]
Message-ID: <20210626081344.5783-8-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210626081344.5783-1-biju.das.jz@bp.renesas.com>
Update SCIF0 clock and reset index in SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3->v4:
* No change.
v2->v3:
* Added Geert's Rb tag.
v1->v2:
* Updated reset entries
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 734c8adeceba..01482d227506 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -82,10 +82,10 @@
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
- resets = <&cpg R9A07G044_CLK_SCIF0>;
+ resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
--
2.17.1
next prev parent reply other threads:[~2021-06-26 8:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-26 8:13 [PATCH v4 00/10] Update clock definitions Biju Das
2021-06-26 8:13 ` [PATCH v4 01/10] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-26 8:13 ` [PATCH v4 02/10] drivers: clk: renesas: r9a07g044-cpg: Rename divider table Biju Das
2021-06-26 8:13 ` [PATCH v4 03/10] drivers: clk: renesas: r9a07g044-cpg: Fix P1 Clock Biju Das
2021-06-26 8:13 ` [PATCH v4 04/10] drivers: clk: renesas: r9a07g044-cpg: Add P2 Clock support Biju Das
2021-06-26 8:13 ` [PATCH v4 05/10] dt-bindings: clk: r9a07g044-cpg: Update clock/reset definitions Biju Das
2021-07-14 2:42 ` Rob Herring
2021-07-14 8:11 ` Geert Uytterhoeven
2021-06-26 8:13 ` [PATCH v4 06/10] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries Biju Das
2021-06-28 12:00 ` Geert Uytterhoeven
2021-06-26 8:13 ` Biju Das [this message]
2021-06-26 8:13 ` [PATCH v4 08/10] drivers: clk: renesas: r9a07g044-cpg: Add I2C clocks/resets Biju Das
2021-06-26 8:13 ` [PATCH v4 09/10] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks/resets Biju Das
2021-06-26 8:13 ` [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add I2C nodes Biju Das
2021-06-28 12:18 ` [PATCH v4 00/10] Update clock definitions Geert Uytterhoeven
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