From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v4 04/10] drivers: clk: renesas: r9a07g044-cpg: Add P2 Clock support
Date: Sat, 26 Jun 2021 09:13:38 +0100 [thread overview]
Message-ID: <20210626081344.5783-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210626081344.5783-1-biju.das.jz@bp.renesas.com>
Add support for P2 clock which is sourced from pll3_div2_4_2.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3->v4
* No change
v2->v3
* Added Geert's Rb tag
* Changed dtable name to dtable_1_32
v1->v2:
* Changed the divider name.
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++++
drivers/clk/renesas/renesas-rzg2l-cpg.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index d895c1cef1fa..70df4feda417 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -31,6 +31,7 @@ enum clk_ids {
CLK_PLL3,
CLK_PLL3_DIV2,
CLK_PLL3_DIV2_4,
+ CLK_PLL3_DIV2_4_2,
CLK_PLL3_DIV4,
CLK_PLL4,
CLK_PLL5,
@@ -68,6 +69,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
+ DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
/* Core output clk */
@@ -77,6 +79,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
+ DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/renesas-rzg2l-cpg.h
index 3948bdd8afc9..a6a3bade1985 100644
--- a/drivers/clk/renesas/renesas-rzg2l-cpg.h
+++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h
@@ -21,6 +21,7 @@
#define DDIV_PACK(offset, bitpos, size) \
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
+#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
/**
--
2.17.1
next prev parent reply other threads:[~2021-06-26 8:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-26 8:13 [PATCH v4 00/10] Update clock definitions Biju Das
2021-06-26 8:13 ` [PATCH v4 01/10] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-26 8:13 ` [PATCH v4 02/10] drivers: clk: renesas: r9a07g044-cpg: Rename divider table Biju Das
2021-06-26 8:13 ` [PATCH v4 03/10] drivers: clk: renesas: r9a07g044-cpg: Fix P1 Clock Biju Das
2021-06-26 8:13 ` Biju Das [this message]
2021-06-26 8:13 ` [PATCH v4 05/10] dt-bindings: clk: r9a07g044-cpg: Update clock/reset definitions Biju Das
2021-07-14 2:42 ` Rob Herring
2021-07-14 8:11 ` Geert Uytterhoeven
2021-06-26 8:13 ` [PATCH v4 06/10] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries Biju Das
2021-06-28 12:00 ` Geert Uytterhoeven
2021-06-26 8:13 ` [PATCH v4 07/10] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset Biju Das
2021-06-26 8:13 ` [PATCH v4 08/10] drivers: clk: renesas: r9a07g044-cpg: Add I2C clocks/resets Biju Das
2021-06-26 8:13 ` [PATCH v4 09/10] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks/resets Biju Das
2021-06-26 8:13 ` [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add I2C nodes Biju Das
2021-06-28 12:18 ` [PATCH v4 00/10] Update clock definitions Geert Uytterhoeven
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