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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v2 02/11] drivers: clk: renesas: r9a07g044-cpg: Rename divider table
Date: Fri, 25 Jun 2021 16:27:56 +0200	[thread overview]
Message-ID: <CAMuHMdVhyBVzF864m6n78U2nr+ZREj36B=T3wdtXDmTHRXcDjw@mail.gmail.com> (raw)
In-Reply-To: <20210624130240.17468-3-biju.das.jz@bp.renesas.com>

Hi Biju,

Thanks for your patch!

On Thu, Jun 24, 2021 at 3:02 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
> and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
> clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it

This does not match the actual variable name.
I do like the shorter name, though ;-)

> can be reused.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Apart from that:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -42,12 +42,13 @@ enum clk_ids {
>  };
>
>  /* Divider tables */
> -static const struct clk_div_table dtable_3b[] = {
> +static const struct clk_div_table dtable_common_1_32[] = {
>         {0, 1},
>         {1, 2},
>         {2, 4},
>         {3, 8},
>         {4, 32},
> +       {0, 0},
>  };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2021-06-25 14:28 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24 13:02 [PATCH v2 00/11] Update clock definitions Biju Das
2021-06-24 13:02 ` [PATCH v2 01/11] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Biju Das
2021-06-24 13:02 ` [PATCH v2 02/11] drivers: clk: renesas: r9a07g044-cpg: Rename divider table Biju Das
2021-06-25 14:27   ` Geert Uytterhoeven [this message]
2021-06-25 14:52     ` Biju Das
2021-06-24 13:02 ` [PATCH v2 03/11] drivers: clk: renesas: r9a07g044-cpg: Fix P1 Clock Biju Das
2021-06-25 14:32   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 04/11] drivers: clk: renesas: r9a07g044-cpg: Add P2 Clock support Biju Das
2021-06-25 14:33   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 05/11] dt-bindings: clk: r9a07g044-cpg: Update clock/reset definitions Biju Das
2021-06-25 14:33   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 06/11] drivers: clk: renesas: renesas-rzg2l-cpg: Separate reset from module clocks Biju Das
2021-06-25 14:42   ` Geert Uytterhoeven
2021-06-25 14:50     ` Biju Das
2021-06-24 13:02 ` [PATCH v2 07/11] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock/reset entries Biju Das
2021-06-25 15:05   ` Geert Uytterhoeven
2021-06-25 16:08     ` Biju Das
2021-06-25 17:42       ` Geert Uytterhoeven
2021-06-25 18:32         ` Biju Das
2021-06-24 13:02 ` [PATCH v2 08/11] arm64: dts: renesas: r9a07g044: Update SCIF0 clock/reset Biju Das
2021-06-25 15:05   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 09/11] drivers: clk: renesas: r9a07g044-cpg: Add I2C clocks/resets Biju Das
2021-06-25 15:06   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 10/11] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks/resets Biju Das
2021-06-25 15:12   ` Geert Uytterhoeven
2021-06-24 13:02 ` [PATCH v2 11/11] arm64: dts: renesas: r9a07g044: Add I2C nodes Biju Das
2021-06-25 15:16   ` Geert Uytterhoeven
2021-06-25 17:01     ` Biju Das

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