From: mhiramat@kernel.org (Masami Hiramatsu) To: linux-riscv@lists.infradead.org Subject: [RFC/RFT 2/2] RISC-V: kprobes/kretprobe support Date: Wed, 14 Nov 2018 23:50:04 -0800 [thread overview] Message-ID: <20181114235004.1d57d911e15efaa8f18fa75e@kernel.org> (raw) In-Reply-To: <05082ba4-33d6-a95c-e049-78791dafc009@packi.ch> On Wed, 14 Nov 2018 22:10:52 +0100 Patrick Staehlin <me@packi.ch> wrote: > On 14.11.18 16:49, Masami Hiramatsu wrote: > > On Wed, 14 Nov 2018 00:37:30 -0800 > > Masami Hiramatsu <mhiramat@kernel.org> wrote: > > > >>> + > >>> +static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode) > >>> +{ > >>> + if (is_compressed_insn(opcode)) > >>> + *(u16 *)addr = cpu_to_le16(opcode); > >>> + else > >>> + *addr = cpu_to_le32(opcode); > >>> + > > > > BTW, don't RISC-V need any i-cache flush and per-core serialization > > for patching the text area? (and no text_mutex protection?) > > Yes, we should probably call flush_icache_all. This code works on > QEMU/virt but I guess on real hardware you may run into problems, > especially when disarming the kprobe. I'll have a look at the arm64 code > again to see what's missing. Note that self code-modifying is a special case for any processors, especially if that is multi-processor. In general, this may depend on the circuit desgin, not ISA. Some processor implementation will do in-order and no i-cache, no SMP, that will be simple, but if it is out-of-order, deep pipeline, huge i-cache, and many-core, you might have to care many things. We have to talk with someone who is designing real hardware, and maybe better to make the patch_text pluggable for variants. (or choose the safest way) > >>> diff --git a/arch/riscv/kernel/probes/kprobes_trampoline.S b/arch/riscv/kernel/probes/kprobes_trampoline.S > >>> new file mode 100644 > >>> index 000000000000..c7ceda9556a3 > >>> --- /dev/null > >>> +++ b/arch/riscv/kernel/probes/kprobes_trampoline.S > >>> @@ -0,0 +1,91 @@ > >>> +/* SPDX-License-Identifier: GPL-2.0+ */ > >>> + > >>> +#include <linux/linkage.h> > >>> + > >>> +#include <asm/asm.h> > >>> +#include <asm/asm-offsets.h> > >>> + > >>> + .text > >>> + .altmacro > >>> + > >>> + .macro save_all_base_regs > >>> + REG_S x1, PT_RA(sp) > >>> + REG_S x3, PT_GP(sp) > >>> + REG_S x4, PT_TP(sp) > >>> + REG_S x5, PT_T0(sp) > >>> + REG_S x6, PT_T1(sp) > >>> + REG_S x7, PT_T2(sp) > >>> + REG_S x8, PT_S0(sp) > >>> + REG_S x9, PT_S1(sp) > >>> + REG_S x10, PT_A0(sp) > >>> + REG_S x11, PT_A1(sp) > >>> + REG_S x12, PT_A2(sp) > >>> + REG_S x13, PT_A3(sp) > >>> + REG_S x14, PT_A4(sp) > >>> + REG_S x15, PT_A5(sp) > >>> + REG_S x16, PT_A6(sp) > >>> + REG_S x17, PT_A7(sp) > >>> + REG_S x18, PT_S2(sp) > >>> + REG_S x19, PT_S3(sp) > >>> + REG_S x20, PT_S4(sp) > >>> + REG_S x21, PT_S5(sp) > >>> + REG_S x22, PT_S6(sp) > >>> + REG_S x23, PT_S7(sp) > >>> + REG_S x24, PT_S8(sp) > >>> + REG_S x25, PT_S9(sp) > >>> + REG_S x26, PT_S10(sp) > >>> + REG_S x27, PT_S11(sp) > >>> + REG_S x28, PT_T3(sp) > >>> + REG_S x29, PT_T4(sp) > >>> + REG_S x30, PT_T5(sp) > >>> + REG_S x31, PT_T6(sp) > >>> + .endm > >>> + > >>> + .macro restore_all_base_regs > >>> + REG_L x3, PT_GP(sp) > >>> + REG_L x4, PT_TP(sp) > >>> + REG_L x5, PT_T0(sp) > >>> + REG_L x6, PT_T1(sp) > >>> + REG_L x7, PT_T2(sp) > >>> + REG_L x8, PT_S0(sp) > >>> + REG_L x9, PT_S1(sp) > >>> + REG_L x10, PT_A0(sp) > >>> + REG_L x11, PT_A1(sp) > >>> + REG_L x12, PT_A2(sp) > >>> + REG_L x13, PT_A3(sp) > >>> + REG_L x14, PT_A4(sp) > >>> + REG_L x15, PT_A5(sp) > >>> + REG_L x16, PT_A6(sp) > >>> + REG_L x17, PT_A7(sp) > >>> + REG_L x18, PT_S2(sp) > >>> + REG_L x19, PT_S3(sp) > >>> + REG_L x20, PT_S4(sp) > >>> + REG_L x21, PT_S5(sp) > >>> + REG_L x22, PT_S6(sp) > >>> + REG_L x23, PT_S7(sp) > >>> + REG_L x24, PT_S8(sp) > >>> + REG_L x25, PT_S9(sp) > >>> + REG_L x26, PT_S10(sp) > >>> + REG_L x27, PT_S11(sp) > >>> + REG_L x28, PT_T3(sp) > >>> + REG_L x29, PT_T4(sp) > >>> + REG_L x30, PT_T5(sp) > >>> + REG_L x31, PT_T6(sp) > >>> + .endm > > > > > > It seems thses macros can be (partially?) shared with entry.S > > Yes, I wanted to avoid somebody changing the shared code and breaking > random things. But that's what reviews are for. I'll think of something > for v2. Ah, OK. So for the first version, we introduce this separated code until someone complains it. Thank you, -- Masami Hiramatsu <mhiramat@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Masami Hiramatsu <mhiramat@kernel.org> To: Patrick Staehlin <me@packi.ch> Cc: Albert Ou <aou@eecs.berkeley.edu>, Anders Roxell <anders.roxell@linaro.org>, Andrew Morton <akpm@linux-foundation.org>, Alan Kao <alankao@andestech.com>, Catalin Marinas <catalin.marinas@arm.com>, Palmer Dabbelt <palmer@sifive.com>, Will Deacon <will.deacon@arm.com>, linux-kernel@vger.kernel.org, Al Viro <viro@zeniv.linux.org.uk>, Souptick Joarder <jrdr.linux@gmail.com>, Zong Li <zong@andestech.com>, Thomas Gleixner <tglx@linutronix.de>, "Eric W. Biederman" <ebiederm@xmission.com>, linux-riscv@lists.infradead.org, zhong jiang <zhongjiang@huawei.com>, Ingo Molnar <mingo@kernel.org>, Luc Van Oostenryck <luc.vanoostenryck@gmail.com>, Jim Wilson <jimw@sifive.com> Subject: Re: [RFC/RFT 2/2] RISC-V: kprobes/kretprobe support Date: Wed, 14 Nov 2018 23:50:04 -0800 [thread overview] Message-ID: <20181114235004.1d57d911e15efaa8f18fa75e@kernel.org> (raw) Message-ID: <20181115075004.H4nqx6ml9mPkFSCqKy4YaTlgz2gz-21xusQ1VcZfNCk@z> (raw) In-Reply-To: <05082ba4-33d6-a95c-e049-78791dafc009@packi.ch> On Wed, 14 Nov 2018 22:10:52 +0100 Patrick Staehlin <me@packi.ch> wrote: > On 14.11.18 16:49, Masami Hiramatsu wrote: > > On Wed, 14 Nov 2018 00:37:30 -0800 > > Masami Hiramatsu <mhiramat@kernel.org> wrote: > > > >>> + > >>> +static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode) > >>> +{ > >>> + if (is_compressed_insn(opcode)) > >>> + *(u16 *)addr = cpu_to_le16(opcode); > >>> + else > >>> + *addr = cpu_to_le32(opcode); > >>> + > > > > BTW, don't RISC-V need any i-cache flush and per-core serialization > > for patching the text area? (and no text_mutex protection?) > > Yes, we should probably call flush_icache_all. This code works on > QEMU/virt but I guess on real hardware you may run into problems, > especially when disarming the kprobe. I'll have a look at the arm64 code > again to see what's missing. Note that self code-modifying is a special case for any processors, especially if that is multi-processor. In general, this may depend on the circuit desgin, not ISA. Some processor implementation will do in-order and no i-cache, no SMP, that will be simple, but if it is out-of-order, deep pipeline, huge i-cache, and many-core, you might have to care many things. We have to talk with someone who is designing real hardware, and maybe better to make the patch_text pluggable for variants. (or choose the safest way) > >>> diff --git a/arch/riscv/kernel/probes/kprobes_trampoline.S b/arch/riscv/kernel/probes/kprobes_trampoline.S > >>> new file mode 100644 > >>> index 000000000000..c7ceda9556a3 > >>> --- /dev/null > >>> +++ b/arch/riscv/kernel/probes/kprobes_trampoline.S > >>> @@ -0,0 +1,91 @@ > >>> +/* SPDX-License-Identifier: GPL-2.0+ */ > >>> + > >>> +#include <linux/linkage.h> > >>> + > >>> +#include <asm/asm.h> > >>> +#include <asm/asm-offsets.h> > >>> + > >>> + .text > >>> + .altmacro > >>> + > >>> + .macro save_all_base_regs > >>> + REG_S x1, PT_RA(sp) > >>> + REG_S x3, PT_GP(sp) > >>> + REG_S x4, PT_TP(sp) > >>> + REG_S x5, PT_T0(sp) > >>> + REG_S x6, PT_T1(sp) > >>> + REG_S x7, PT_T2(sp) > >>> + REG_S x8, PT_S0(sp) > >>> + REG_S x9, PT_S1(sp) > >>> + REG_S x10, PT_A0(sp) > >>> + REG_S x11, PT_A1(sp) > >>> + REG_S x12, PT_A2(sp) > >>> + REG_S x13, PT_A3(sp) > >>> + REG_S x14, PT_A4(sp) > >>> + REG_S x15, PT_A5(sp) > >>> + REG_S x16, PT_A6(sp) > >>> + REG_S x17, PT_A7(sp) > >>> + REG_S x18, PT_S2(sp) > >>> + REG_S x19, PT_S3(sp) > >>> + REG_S x20, PT_S4(sp) > >>> + REG_S x21, PT_S5(sp) > >>> + REG_S x22, PT_S6(sp) > >>> + REG_S x23, PT_S7(sp) > >>> + REG_S x24, PT_S8(sp) > >>> + REG_S x25, PT_S9(sp) > >>> + REG_S x26, PT_S10(sp) > >>> + REG_S x27, PT_S11(sp) > >>> + REG_S x28, PT_T3(sp) > >>> + REG_S x29, PT_T4(sp) > >>> + REG_S x30, PT_T5(sp) > >>> + REG_S x31, PT_T6(sp) > >>> + .endm > >>> + > >>> + .macro restore_all_base_regs > >>> + REG_L x3, PT_GP(sp) > >>> + REG_L x4, PT_TP(sp) > >>> + REG_L x5, PT_T0(sp) > >>> + REG_L x6, PT_T1(sp) > >>> + REG_L x7, PT_T2(sp) > >>> + REG_L x8, PT_S0(sp) > >>> + REG_L x9, PT_S1(sp) > >>> + REG_L x10, PT_A0(sp) > >>> + REG_L x11, PT_A1(sp) > >>> + REG_L x12, PT_A2(sp) > >>> + REG_L x13, PT_A3(sp) > >>> + REG_L x14, PT_A4(sp) > >>> + REG_L x15, PT_A5(sp) > >>> + REG_L x16, PT_A6(sp) > >>> + REG_L x17, PT_A7(sp) > >>> + REG_L x18, PT_S2(sp) > >>> + REG_L x19, PT_S3(sp) > >>> + REG_L x20, PT_S4(sp) > >>> + REG_L x21, PT_S5(sp) > >>> + REG_L x22, PT_S6(sp) > >>> + REG_L x23, PT_S7(sp) > >>> + REG_L x24, PT_S8(sp) > >>> + REG_L x25, PT_S9(sp) > >>> + REG_L x26, PT_S10(sp) > >>> + REG_L x27, PT_S11(sp) > >>> + REG_L x28, PT_T3(sp) > >>> + REG_L x29, PT_T4(sp) > >>> + REG_L x30, PT_T5(sp) > >>> + REG_L x31, PT_T6(sp) > >>> + .endm > > > > > > It seems thses macros can be (partially?) shared with entry.S > > Yes, I wanted to avoid somebody changing the shared code and breaking > random things. But that's what reviews are for. I'll think of something > for v2. Ah, OK. So for the first version, we introduce this separated code until someone complains it. Thank you, -- Masami Hiramatsu <mhiramat@kernel.org> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2018-11-15 7:50 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-13 19:58 [RFC/RFT 0/2] RISC-V: kprobes/kretprobe support Patrick Stählin 2018-11-13 19:58 ` Patrick Stählin 2018-11-13 19:58 ` [RFC/RFT 1/2] RISC-V: Implement ptrace regs and stack API Patrick Stählin 2018-11-13 19:58 ` Patrick Stählin 2019-11-21 22:34 ` Paul Walmsley 2018-11-13 19:58 ` [RFC/RFT 2/2] RISC-V: kprobes/kretprobe support Patrick Stählin 2018-11-13 19:58 ` Patrick Stählin 2018-11-14 8:37 ` Masami Hiramatsu 2018-11-14 8:37 ` Masami Hiramatsu 2018-11-14 15:49 ` Masami Hiramatsu 2018-11-14 15:49 ` Masami Hiramatsu 2018-11-14 21:10 ` Patrick Staehlin 2018-11-14 21:10 ` Patrick Staehlin 2018-11-15 7:50 ` Masami Hiramatsu [this message] 2018-11-15 7:50 ` Masami Hiramatsu 2019-12-20 11:14 ` Paul Walmsley 2019-12-20 22:46 ` Paul Walmsley 2018-11-14 20:52 ` Patrick Staehlin 2018-11-14 20:52 ` Patrick Staehlin 2018-11-15 8:41 ` Masami Hiramatsu 2018-11-15 8:41 ` Masami Hiramatsu [not found] ` <CANXhq0qWwKRrz80Q3LSeQu-cH19otCF1my6dDGDxH0Q5j1RYYw@mail.gmail.com> [not found] ` <9cdd84b5-6c81-9bfa-5d35-6645f542f71e@packi.ch> 2019-12-19 9:28 ` Zong Li 2020-03-31 2:45 ` Zong Li 2020-06-12 5:57 ` David Abdurachmanov 2020-06-17 12:58 ` Guo Ren 2020-06-17 14:54 ` Masami Hiramatsu 2020-06-18 16:14 ` Guo Ren 2020-07-05 14:57 ` Guo Ren
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20181114235004.1d57d911e15efaa8f18fa75e@kernel.org \ --to=mhiramat@kernel.org \ --cc=linux-riscv@lists.infradead.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).