From: Conor Dooley <mail@conchuod.ie>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daire McNamara <daire.mcnamara@microchip.com>,
Conor Dooley <conor.dooley@microchip.com>,
Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Zong Li <zong.li@sifive.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Jonas Hahnfeld <hahnjo@hahnjo.de>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Brice Goglin <Brice.Goglin@inria.fr>
Subject: [PATCH 1/5] riscv: dts: starfive: Add JH7100 CPU topology
Date: Tue, 5 Jul 2022 20:04:32 +0100 [thread overview]
Message-ID: <20220705190435.1790466-2-mail@conchuod.ie> (raw)
In-Reply-To: <20220705190435.1790466-1-mail@conchuod.ie>
From: Jonas Hahnfeld <hahnjo@hahnjo.de>
Add cpu-map binding to inform the kernel about the hardware topology
of the CPU cores.
Before this change, lstopo would report 1 core with 2 threads:
Machine (7231MB total)
Package L#0
NUMANode L#0 (P#0 7231MB)
L2 L#0 (2048KB) + Core L#0
L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
After this change, it correctly identifies two cores:
Machine (7231MB total)
Package L#0
NUMANode L#0 (P#0 7231MB)
L2 L#0 (2048KB)
L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 69f22f9aad9d..c617a61e26e2 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -17,7 +17,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ U74_0: cpu@0 {
compatible = "sifive,u74-mc", "riscv";
reg = <0>;
d-cache-block-size = <64>;
@@ -42,7 +42,7 @@ cpu0_intc: interrupt-controller {
};
};
- cpu@1 {
+ U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
reg = <1>;
d-cache-block-size = <64>;
@@ -66,6 +66,18 @@ cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
};
};
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&U74_0>;
+ };
+
+ core1 {
+ cpu = <&U74_1>;
+ };
+ };
+ };
};
osc_sys: osc_sys {
--
2.37.0
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next prev parent reply other threads:[~2022-07-05 19:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-05 19:04 [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Conor Dooley
2022-07-05 19:04 ` Conor Dooley [this message]
2022-07-05 19:04 ` [PATCH 2/5] riscv: dts: sifive: Add fu540 topology information Conor Dooley
2022-07-05 19:04 ` [PATCH 3/5] riscv: dts: sifive: Add fu740 " Conor Dooley
2022-07-05 19:04 ` [PATCH 4/5] riscv: dts: microchip: Add mpfs' " Conor Dooley
2022-07-14 22:04 ` Palmer Dabbelt
2022-07-05 19:04 ` [PATCH 5/5] riscv: dts: canaan: Add k210 " Conor Dooley
2022-07-06 3:49 ` Damien Le Moal
2022-07-05 20:19 ` [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Sudeep Holla
2022-07-05 20:33 ` Conor.Dooley
2022-07-05 23:03 ` Conor.Dooley
2022-07-06 9:21 ` Sudeep Holla
2022-07-06 9:43 ` Conor.Dooley
2022-07-06 10:03 ` Sudeep Holla
2022-07-06 10:11 ` Conor.Dooley
2022-07-06 13:04 ` Conor.Dooley
2022-07-06 14:00 ` Sudeep Holla
2022-07-06 9:18 ` Sudeep Holla
2022-07-07 22:29 ` (subset) " Conor Dooley
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