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From: Sudeep Holla <sudeep.holla@arm.com>
To: Conor Dooley <mail@conchuod.ie>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Niklas Cassel <niklas.cassel@wdc.com>,
	Damien Le Moal <damien.lemoal@opensource.wdc.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Zong Li <zong.li@sifive.com>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Jonas Hahnfeld <hahnjo@hahnjo.de>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Brice Goglin <Brice.Goglin@inria.fr>
Subject: Re: [PATCH 0/5] RISC-V: Add cpu-map topology information nodes
Date: Tue, 5 Jul 2022 21:19:31 +0100	[thread overview]
Message-ID: <20220705201931.nfwi5rlku7ykmydr@bogus> (raw)
In-Reply-To: <20220705190435.1790466-1-mail@conchuod.ie>

On Tue, Jul 05, 2022 at 08:04:31PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> It was reported to me that the Hive Unmatched incorrectly reports
> its topology to hwloc, but the StarFive VisionFive did in [0] &
> a subsequent off-list email from Brice (the hwloc maintainer).
> This turned out not to be entirely true, the /downstream/ version
> of the VisionFive does work correctly but not upstream, as the
> downstream devicetree has a cpu-map node that was added recently.
> 
> This series adds a cpu-map node to all upstream devicetrees, which
> I have tested on mpfs & fu540. The first patch is lifted directly
> from the downstream StarFive devicetree.
> 

Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>

I would recommend to have sane defaults in core risc-v code in case of
absence of /cpu-map node as it is optional. The reason I mentioned is that
Conor mentioned how the default values in absence of the node looked quite
wrong. I don't know if it is possible on RISC-V but on ARM64 we do have
default values if arch_topology fails to set based on DT/ACPI.

-- 
Regards,
Sudeep

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  parent reply	other threads:[~2022-07-05 20:21 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-05 19:04 [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Conor Dooley
2022-07-05 19:04 ` [PATCH 1/5] riscv: dts: starfive: Add JH7100 CPU topology Conor Dooley
2022-07-05 19:04 ` [PATCH 2/5] riscv: dts: sifive: Add fu540 topology information Conor Dooley
2022-07-05 19:04 ` [PATCH 3/5] riscv: dts: sifive: Add fu740 " Conor Dooley
2022-07-05 19:04 ` [PATCH 4/5] riscv: dts: microchip: Add mpfs' " Conor Dooley
2022-07-14 22:04   ` Palmer Dabbelt
2022-07-05 19:04 ` [PATCH 5/5] riscv: dts: canaan: Add k210 " Conor Dooley
2022-07-06  3:49   ` Damien Le Moal
2022-07-05 20:19 ` Sudeep Holla [this message]
2022-07-05 20:33   ` [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Conor.Dooley
2022-07-05 23:03     ` Conor.Dooley
2022-07-06  9:21       ` Sudeep Holla
2022-07-06  9:43         ` Conor.Dooley
2022-07-06 10:03           ` Sudeep Holla
2022-07-06 10:11             ` Conor.Dooley
2022-07-06 13:04         ` Conor.Dooley
2022-07-06 14:00           ` Sudeep Holla
2022-07-06  9:18     ` Sudeep Holla
2022-07-07 22:29 ` (subset) " Conor Dooley

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