From: Conor Dooley <mail@conchuod.ie>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daire McNamara <daire.mcnamara@microchip.com>,
Conor Dooley <conor.dooley@microchip.com>,
Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Zong Li <zong.li@sifive.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Jonas Hahnfeld <hahnjo@hahnjo.de>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Brice Goglin <Brice.Goglin@inria.fr>
Subject: [PATCH 0/5] RISC-V: Add cpu-map topology information nodes
Date: Tue, 5 Jul 2022 20:04:31 +0100 [thread overview]
Message-ID: <20220705190435.1790466-1-mail@conchuod.ie> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
It was reported to me that the Hive Unmatched incorrectly reports
its topology to hwloc, but the StarFive VisionFive did in [0] &
a subsequent off-list email from Brice (the hwloc maintainer).
This turned out not to be entirely true, the /downstream/ version
of the VisionFive does work correctly but not upstream, as the
downstream devicetree has a cpu-map node that was added recently.
This series adds a cpu-map node to all upstream devicetrees, which
I have tested on mpfs & fu540. The first patch is lifted directly
from the downstream StarFive devicetree.
Thanks,
Conor.
0: https://github.com/open-mpi/hwloc/issues/536
Conor Dooley (4):
riscv: dts: sifive: Add fu540 topology information
riscv: dts: sifive: Add fu740 topology information
riscv: dts: microchip: Add mpfs' topology information
riscv: dts: canaan: Add k210 topology information
Jonas Hahnfeld (1):
riscv: dts: starfive: Add JH7100 CPU topology
arch/riscv/boot/dts/canaan/k210.dtsi | 12 +++++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 ++++++++++++++++++++++
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 24 ++++++++++++++++++++++
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 24 ++++++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 +++++++++++++--
5 files changed, 98 insertions(+), 2 deletions(-)
base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563
--
2.37.0
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next reply other threads:[~2022-07-05 19:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-05 19:04 Conor Dooley [this message]
2022-07-05 19:04 ` [PATCH 1/5] riscv: dts: starfive: Add JH7100 CPU topology Conor Dooley
2022-07-05 19:04 ` [PATCH 2/5] riscv: dts: sifive: Add fu540 topology information Conor Dooley
2022-07-05 19:04 ` [PATCH 3/5] riscv: dts: sifive: Add fu740 " Conor Dooley
2022-07-05 19:04 ` [PATCH 4/5] riscv: dts: microchip: Add mpfs' " Conor Dooley
2022-07-14 22:04 ` Palmer Dabbelt
2022-07-05 19:04 ` [PATCH 5/5] riscv: dts: canaan: Add k210 " Conor Dooley
2022-07-06 3:49 ` Damien Le Moal
2022-07-05 20:19 ` [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Sudeep Holla
2022-07-05 20:33 ` Conor.Dooley
2022-07-05 23:03 ` Conor.Dooley
2022-07-06 9:21 ` Sudeep Holla
2022-07-06 9:43 ` Conor.Dooley
2022-07-06 10:03 ` Sudeep Holla
2022-07-06 10:11 ` Conor.Dooley
2022-07-06 13:04 ` Conor.Dooley
2022-07-06 14:00 ` Sudeep Holla
2022-07-06 9:18 ` Sudeep Holla
2022-07-07 22:29 ` (subset) " Conor Dooley
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