From: Sudeep Holla <sudeep.holla@arm.com>
To: Conor.Dooley@microchip.com
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, Daire.McNamara@microchip.com,
niklas.cassel@wdc.com, damien.lemoal@opensource.wdc.com,
geert@linux-m68k.org, zong.li@sifive.com, kernel@esmil.dk,
hahnjo@hahnjo.de, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Brice.Goglin@inria.fr
Subject: Re: [PATCH 0/5] RISC-V: Add cpu-map topology information nodes
Date: Wed, 6 Jul 2022 10:18:50 +0100 [thread overview]
Message-ID: <20220706091850.deealvovinkzjrml@bogus> (raw)
In-Reply-To: <8f07796a-d9a2-3301-aafb-7fbec4d5b1a2@microchip.com>
On Tue, Jul 05, 2022 at 08:33:39PM +0000, Conor.Dooley@microchip.com wrote:
>
>
> On 05/07/2022 21:19, Sudeep Holla wrote:
> > On Tue, Jul 05, 2022 at 08:04:31PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> It was reported to me that the Hive Unmatched incorrectly reports
> >> its topology to hwloc, but the StarFive VisionFive did in [0] &
> >> a subsequent off-list email from Brice (the hwloc maintainer).
> >> This turned out not to be entirely true, the /downstream/ version
> >> of the VisionFive does work correctly but not upstream, as the
> >> downstream devicetree has a cpu-map node that was added recently.
> >>
> >> This series adds a cpu-map node to all upstream devicetrees, which
> >> I have tested on mpfs & fu540. The first patch is lifted directly
> >> from the downstream StarFive devicetree.
> >>
> >
> > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> >
> > I would recommend to have sane defaults in core risc-v code in case of
> > absence of /cpu-map node as it is optional. The reason I mentioned is that
> > Conor mentioned how the default values in absence of the node looked quite
> > wrong. I don't know if it is possible on RISC-V but on ARM64 we do have
> > default values if arch_topology fails to set based on DT/ACPI.
> >
>
> Yeah the defaults are all -1. I'll add some sane defaults for a v2.
Sorry I didn't mean it to be part of this series. This series of DT changes
are just fine on their own.
--
Regards,
Sudeep
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next prev parent reply other threads:[~2022-07-06 9:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-05 19:04 [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Conor Dooley
2022-07-05 19:04 ` [PATCH 1/5] riscv: dts: starfive: Add JH7100 CPU topology Conor Dooley
2022-07-05 19:04 ` [PATCH 2/5] riscv: dts: sifive: Add fu540 topology information Conor Dooley
2022-07-05 19:04 ` [PATCH 3/5] riscv: dts: sifive: Add fu740 " Conor Dooley
2022-07-05 19:04 ` [PATCH 4/5] riscv: dts: microchip: Add mpfs' " Conor Dooley
2022-07-14 22:04 ` Palmer Dabbelt
2022-07-05 19:04 ` [PATCH 5/5] riscv: dts: canaan: Add k210 " Conor Dooley
2022-07-06 3:49 ` Damien Le Moal
2022-07-05 20:19 ` [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Sudeep Holla
2022-07-05 20:33 ` Conor.Dooley
2022-07-05 23:03 ` Conor.Dooley
2022-07-06 9:21 ` Sudeep Holla
2022-07-06 9:43 ` Conor.Dooley
2022-07-06 10:03 ` Sudeep Holla
2022-07-06 10:11 ` Conor.Dooley
2022-07-06 13:04 ` Conor.Dooley
2022-07-06 14:00 ` Sudeep Holla
2022-07-06 9:18 ` Sudeep Holla [this message]
2022-07-07 22:29 ` (subset) " Conor Dooley
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