* [PATCH V8 01/10] asm-generic: ticket-lock: Remove unnecessary atomic_read
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 02/10] asm-generic: ticket-lock: Use the same struct definitions with qspinlock guoren
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Remove unnecessary atomic_read in arch_spin_value_unlocked(lock),
because the value has been in lock. This patch could prevent
arch_spin_value_unlocked contend spin_lock data again.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
include/asm-generic/spinlock.h | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h
index fdfebcb050f4..90803a826ba0 100644
--- a/include/asm-generic/spinlock.h
+++ b/include/asm-generic/spinlock.h
@@ -68,11 +68,18 @@ static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
smp_store_release(ptr, (u16)val + 1);
}
+static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
+{
+ u32 val = lock.counter;
+
+ return ((val >> 16) == (val & 0xffff));
+}
+
static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
- u32 val = atomic_read(lock);
+ arch_spinlock_t val = READ_ONCE(*lock);
- return ((val >> 16) != (val & 0xffff));
+ return !arch_spin_value_unlocked(val);
}
static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
@@ -82,11 +89,6 @@ static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
return (s16)((val >> 16) - (val & 0xffff)) > 1;
}
-static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
-{
- return !arch_spin_is_locked(&lock);
-}
-
#include <asm/qrwlock.h>
#endif /* __ASM_GENERIC_SPINLOCK_H */
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 02/10] asm-generic: ticket-lock: Use the same struct definitions with qspinlock
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
2022-07-24 12:25 ` [PATCH V8 01/10] asm-generic: ticket-lock: Remove unnecessary atomic_read guoren
@ 2022-07-24 12:25 ` guoren
2022-07-27 19:20 ` kernel test robot
2022-07-24 12:25 ` [PATCH V8 03/10] asm-generic: ticket-lock: Move into ticket_spinlock.h guoren
` (7 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Let ticket_lock use the same struct definitions with qspinlock, and then
we could move to combo spinlock (combine ticket & queue).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
include/asm-generic/spinlock.h | 14 +++++++-------
include/asm-generic/spinlock_types.h | 12 ++----------
2 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h
index 90803a826ba0..4773334ee638 100644
--- a/include/asm-generic/spinlock.h
+++ b/include/asm-generic/spinlock.h
@@ -32,7 +32,7 @@
static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
{
- u32 val = atomic_fetch_add(1<<16, lock);
+ u32 val = atomic_fetch_add(1<<16, &lock->val);
u16 ticket = val >> 16;
if (ticket == (u16)val)
@@ -46,31 +46,31 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
* have no outstanding writes due to the atomic_fetch_add() the extra
* orderings are free.
*/
- atomic_cond_read_acquire(lock, ticket == (u16)VAL);
+ atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);
smp_mb();
}
static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
{
- u32 old = atomic_read(lock);
+ u32 old = atomic_read(&lock->val);
if ((old >> 16) != (old & 0xffff))
return false;
- return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
+ return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */
}
static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
{
u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
- u32 val = atomic_read(lock);
+ u32 val = atomic_read(&lock->val);
smp_store_release(ptr, (u16)val + 1);
}
static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
- u32 val = lock.counter;
+ u32 val = lock.val.counter;
return ((val >> 16) == (val & 0xffff));
}
@@ -84,7 +84,7 @@ static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
{
- u32 val = atomic_read(lock);
+ u32 val = atomic_read(&lock->val);
return (s16)((val >> 16) - (val & 0xffff)) > 1;
}
diff --git a/include/asm-generic/spinlock_types.h b/include/asm-generic/spinlock_types.h
index 8962bb730945..f534aa5de394 100644
--- a/include/asm-generic/spinlock_types.h
+++ b/include/asm-generic/spinlock_types.h
@@ -3,15 +3,7 @@
#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
#define __ASM_GENERIC_SPINLOCK_TYPES_H
-#include <linux/types.h>
-typedef atomic_t arch_spinlock_t;
-
-/*
- * qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
- * include.
- */
-#include <asm/qrwlock_types.h>
-
-#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */
--
2.36.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V8 02/10] asm-generic: ticket-lock: Use the same struct definitions with qspinlock
2022-07-24 12:25 ` [PATCH V8 02/10] asm-generic: ticket-lock: Use the same struct definitions with qspinlock guoren
@ 2022-07-27 19:20 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2022-07-27 19:20 UTC (permalink / raw)
To: guoren, palmer, heiko, hch, arnd, peterz, will, boqun.feng,
longman, mingo, philipp.tomsich, cmuellner, linux-kernel,
David.Laight
Cc: kbuild-all, linux-riscv, linux-csky, Guo Ren
Hi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on arnd-asm-generic/master]
[also build test WARNING on linus/master v5.19-rc8 next-20220727]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/guoren-kernel-org/arch-Add-qspinlock-support-with-combo-style/20220724-202743
base: https://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic.git master
config: riscv-randconfig-s032-20220726 (https://download.01.org/0day-ci/archive/20220728/202207280322.pBROaNWs-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 12.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
# https://github.com/intel-lab-lkp/linux/commit/e6277b2b8d76d6b4568e4e6f8270d10e8591c383
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review guoren-kernel-org/arch-Add-qspinlock-support-with-combo-style/20220724-202743
git checkout e6277b2b8d76d6b4568e4e6f8270d10e8591c383
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> kernel/seccomp.c:873:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:873:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:873:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:1371:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/seccomp.c:1371:31: sparse: expected struct spinlock [usertype] *lock
kernel/seccomp.c:1371:31: sparse: got struct spinlock [noderef] __rcu *
kernel/seccomp.c:1383:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/seccomp.c:1383:33: sparse: expected struct spinlock [usertype] *lock
kernel/seccomp.c:1383:33: sparse: got struct spinlock [noderef] __rcu *
kernel/seccomp.c:1812:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct lockdep_map const *lock @@ got struct lockdep_map [noderef] __rcu * @@
kernel/seccomp.c:1812:9: sparse: expected struct lockdep_map const *lock
kernel/seccomp.c:1812:9: sparse: got struct lockdep_map [noderef] __rcu *
kernel/seccomp.c:1898:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/seccomp.c:1898:31: sparse: expected struct spinlock [usertype] *lock
kernel/seccomp.c:1898:31: sparse: got struct spinlock [noderef] __rcu *
kernel/seccomp.c:1916:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/seccomp.c:1916:33: sparse: expected struct spinlock [usertype] *lock
kernel/seccomp.c:1916:33: sparse: got struct spinlock [noderef] __rcu *
kernel/seccomp.c:490:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:490:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:490:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:587:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:587:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:587:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:448:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:448:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:448:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:434:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:434:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:434:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:448:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:448:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:448:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:434:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:434:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:434:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/seccomp.c:448:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/seccomp.c:448:9: sparse: expected struct qspinlock [usertype] *lock
kernel/seccomp.c:448:9: sparse: got struct qspinlock [noderef] __rcu *
--
kernel/fork.c:1307:24: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct file [noderef] __rcu *_x_ @@ got struct file *new_exe_file @@
kernel/fork.c:1307:24: sparse: expected struct file [noderef] __rcu *_x_
kernel/fork.c:1307:24: sparse: got struct file *new_exe_file
kernel/fork.c:1307:22: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct file *[assigned] old_exe_file @@ got struct file [noderef] __rcu * @@
kernel/fork.c:1307:22: sparse: expected struct file *[assigned] old_exe_file
kernel/fork.c:1307:22: sparse: got struct file [noderef] __rcu *
kernel/fork.c:1638:38: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct refcount_struct [usertype] *r @@ got struct refcount_struct [noderef] __rcu * @@
kernel/fork.c:1638:38: sparse: expected struct refcount_struct [usertype] *r
kernel/fork.c:1638:38: sparse: got struct refcount_struct [noderef] __rcu *
kernel/fork.c:1647:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:1647:31: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:1647:31: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:1648:36: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void const * @@ got struct k_sigaction [noderef] __rcu * @@
kernel/fork.c:1648:36: sparse: expected void const *
kernel/fork.c:1648:36: sparse: got struct k_sigaction [noderef] __rcu *
kernel/fork.c:1649:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:1649:33: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:1649:33: sparse: got struct spinlock [noderef] __rcu *
>> kernel/fork.c:1742:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct qspinlock [usertype] *lock @@ got struct qspinlock [noderef] __rcu * @@
kernel/fork.c:1742:9: sparse: expected struct qspinlock [usertype] *lock
kernel/fork.c:1742:9: sparse: got struct qspinlock [noderef] __rcu *
kernel/fork.c:2061:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2061:31: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2061:31: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2065:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2065:33: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2065:33: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2385:32: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct task_struct [noderef] __rcu *real_parent @@ got struct task_struct * @@
kernel/fork.c:2385:32: sparse: expected struct task_struct [noderef] __rcu *real_parent
kernel/fork.c:2385:32: sparse: got struct task_struct *
kernel/fork.c:2394:27: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2394:27: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2394:27: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2439:54: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected struct list_head *head @@ got struct list_head [noderef] __rcu * @@
kernel/fork.c:2439:54: sparse: expected struct list_head *head
kernel/fork.c:2439:54: sparse: got struct list_head [noderef] __rcu *
kernel/fork.c:2460:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2460:29: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2460:29: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2481:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2481:29: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2481:29: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2508:28: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct sighand_struct *sighand @@ got struct sighand_struct [noderef] __rcu *sighand @@
kernel/fork.c:2508:28: sparse: expected struct sighand_struct *sighand
kernel/fork.c:2508:28: sparse: got struct sighand_struct [noderef] __rcu *sighand
kernel/fork.c:2537:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2537:31: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2537:31: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2539:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct spinlock [usertype] *lock @@ got struct spinlock [noderef] __rcu * @@
kernel/fork.c:2539:33: sparse: expected struct spinlock [usertype] *lock
kernel/fork.c:2539:33: sparse: got struct spinlock [noderef] __rcu *
kernel/fork.c:2975:24: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct task_struct *[assigned] parent @@ got struct task_struct [noderef] __rcu *real_parent @@
kernel/fork.c:2975:24: sparse: expected struct task_struct *[assigned] parent
kernel/fork.c:2975:24: sparse: got struct task_struct [noderef] __rcu *real_parent
kernel/fork.c:3056:43: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct refcount_struct const [usertype] *r @@ got struct refcount_struct [noderef] __rcu * @@
kernel/fork.c:3056:43: sparse: expected struct refcount_struct const [usertype] *r
kernel/fork.c:3056:43: sparse: got struct refcount_struct [noderef] __rcu *
kernel/fork.c:2106:22: sparse: sparse: dereference of noderef expression
kernel/fork.c: note: in included file (through include/linux/ftrace.h, include/linux/perf_event.h, include/linux/trace_events.h, ...):
include/linux/ptrace.h:210:45: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected struct task_struct *new_parent @@ got struct task_struct [noderef] __rcu *parent @@
include/linux/ptrace.h:210:45: sparse: expected struct task_struct *new_parent
include/linux/ptrace.h:210:45: sparse: got struct task_struct [noderef] __rcu *parent
include/linux/ptrace.h:210:62: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected struct cred const *ptracer_cred @@ got struct cred const [noderef] __rcu *ptracer_cred @@
include/linux/ptrace.h:210:62: sparse: expected struct cred const *ptracer_cred
include/linux/ptrace.h:210:62: sparse: got struct cred const [noderef] __rcu *ptracer_cred
kernel/fork.c:2437:59: sparse: sparse: dereference of noderef expression
kernel/fork.c:2438:59: sparse: sparse: dereference of noderef expression
vim +873 kernel/seccomp.c
8e01b51a31a1e08 YiFei Zhu 2020-10-11 854
c8bee430dc52cfc Kees Cook 2014-06-27 855 /**
c8bee430dc52cfc Kees Cook 2014-06-27 856 * seccomp_attach_filter: validate and attach filter
c8bee430dc52cfc Kees Cook 2014-06-27 857 * @flags: flags to change filter behavior
c8bee430dc52cfc Kees Cook 2014-06-27 858 * @filter: seccomp filter to add to the current process
c8bee430dc52cfc Kees Cook 2014-06-27 859 *
dbd952127d11bb4 Kees Cook 2014-06-27 860 * Caller must be holding current->sighand->siglock lock.
dbd952127d11bb4 Kees Cook 2014-06-27 861 *
7a0df7fbc14505e Tycho Andersen 2019-03-06 862 * Returns 0 on success, -ve on error, or
7a0df7fbc14505e Tycho Andersen 2019-03-06 863 * - in TSYNC mode: the pid of a thread which was either not in the correct
7a0df7fbc14505e Tycho Andersen 2019-03-06 864 * seccomp mode or did not have an ancestral seccomp filter
7a0df7fbc14505e Tycho Andersen 2019-03-06 865 * - in NEW_LISTENER mode: the fd of the new listener
c8bee430dc52cfc Kees Cook 2014-06-27 866 */
c8bee430dc52cfc Kees Cook 2014-06-27 867 static long seccomp_attach_filter(unsigned int flags,
c8bee430dc52cfc Kees Cook 2014-06-27 868 struct seccomp_filter *filter)
c8bee430dc52cfc Kees Cook 2014-06-27 869 {
c8bee430dc52cfc Kees Cook 2014-06-27 870 unsigned long total_insns;
c8bee430dc52cfc Kees Cook 2014-06-27 871 struct seccomp_filter *walker;
c8bee430dc52cfc Kees Cook 2014-06-27 872
69f6a34bdeea4fe Guenter Roeck 2014-08-10 @873 assert_spin_locked(¤t->sighand->siglock);
dbd952127d11bb4 Kees Cook 2014-06-27 874
c8bee430dc52cfc Kees Cook 2014-06-27 875 /* Validate resulting filter length. */
c8bee430dc52cfc Kees Cook 2014-06-27 876 total_insns = filter->prog->len;
c8bee430dc52cfc Kees Cook 2014-06-27 877 for (walker = current->seccomp.filter; walker; walker = walker->prev)
c8bee430dc52cfc Kees Cook 2014-06-27 878 total_insns += walker->prog->len + 4; /* 4 instr penalty */
c8bee430dc52cfc Kees Cook 2014-06-27 879 if (total_insns > MAX_INSNS_PER_PATH)
c8bee430dc52cfc Kees Cook 2014-06-27 880 return -ENOMEM;
c8bee430dc52cfc Kees Cook 2014-06-27 881
c2e1f2e30daa551 Kees Cook 2014-06-05 882 /* If thread sync has been requested, check that it is possible. */
c2e1f2e30daa551 Kees Cook 2014-06-05 883 if (flags & SECCOMP_FILTER_FLAG_TSYNC) {
c2e1f2e30daa551 Kees Cook 2014-06-05 884 int ret;
c2e1f2e30daa551 Kees Cook 2014-06-05 885
c2e1f2e30daa551 Kees Cook 2014-06-05 886 ret = seccomp_can_sync_threads();
51891498f2da78e Tycho Andersen 2020-03-04 887 if (ret) {
51891498f2da78e Tycho Andersen 2020-03-04 888 if (flags & SECCOMP_FILTER_FLAG_TSYNC_ESRCH)
51891498f2da78e Tycho Andersen 2020-03-04 889 return -ESRCH;
51891498f2da78e Tycho Andersen 2020-03-04 890 else
c2e1f2e30daa551 Kees Cook 2014-06-05 891 return ret;
c2e1f2e30daa551 Kees Cook 2014-06-05 892 }
51891498f2da78e Tycho Andersen 2020-03-04 893 }
c2e1f2e30daa551 Kees Cook 2014-06-05 894
e66a39977985b1e Tyler Hicks 2017-08-11 895 /* Set log flag, if present. */
e66a39977985b1e Tyler Hicks 2017-08-11 896 if (flags & SECCOMP_FILTER_FLAG_LOG)
e66a39977985b1e Tyler Hicks 2017-08-11 897 filter->log = true;
e66a39977985b1e Tyler Hicks 2017-08-11 898
c2aa2dfef243efe Sargun Dhillon 2022-05-03 899 /* Set wait killable flag, if present. */
c2aa2dfef243efe Sargun Dhillon 2022-05-03 900 if (flags & SECCOMP_FILTER_FLAG_WAIT_KILLABLE_RECV)
c2aa2dfef243efe Sargun Dhillon 2022-05-03 901 filter->wait_killable_recv = true;
c2aa2dfef243efe Sargun Dhillon 2022-05-03 902
c8bee430dc52cfc Kees Cook 2014-06-27 903 /*
c8bee430dc52cfc Kees Cook 2014-06-27 904 * If there is an existing filter, make it the prev and don't drop its
c8bee430dc52cfc Kees Cook 2014-06-27 905 * task reference.
c8bee430dc52cfc Kees Cook 2014-06-27 906 */
c8bee430dc52cfc Kees Cook 2014-06-27 907 filter->prev = current->seccomp.filter;
8e01b51a31a1e08 YiFei Zhu 2020-10-11 908 seccomp_cache_prepare(filter);
c8bee430dc52cfc Kees Cook 2014-06-27 909 current->seccomp.filter = filter;
c818c03b661cd76 Kees Cook 2020-05-13 910 atomic_inc(¤t->seccomp.filter_count);
c8bee430dc52cfc Kees Cook 2014-06-27 911
c2e1f2e30daa551 Kees Cook 2014-06-05 912 /* Now that the new filter is in place, synchronize to all threads. */
c2e1f2e30daa551 Kees Cook 2014-06-05 913 if (flags & SECCOMP_FILTER_FLAG_TSYNC)
00a02d0c502a06d Kees Cook 2018-05-03 914 seccomp_sync_threads(flags);
c2e1f2e30daa551 Kees Cook 2014-06-05 915
c8bee430dc52cfc Kees Cook 2014-06-27 916 return 0;
e2cfabdfd075648 Will Drewry 2012-04-12 917 }
e2cfabdfd075648 Will Drewry 2012-04-12 918
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH V8 03/10] asm-generic: ticket-lock: Move into ticket_spinlock.h
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
2022-07-24 12:25 ` [PATCH V8 01/10] asm-generic: ticket-lock: Remove unnecessary atomic_read guoren
2022-07-24 12:25 ` [PATCH V8 02/10] asm-generic: ticket-lock: Use the same struct definitions with qspinlock guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 04/10] asm-generic: spinlock: Add queued spinlock support in common header guoren
` (6 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Move ticket-lock definition into an independent file. It's a preparation
patch for the following combo spinlock.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
include/asm-generic/spinlock.h | 87 +---------------------
include/asm-generic/ticket_spinlock.h | 103 ++++++++++++++++++++++++++
2 files changed, 104 insertions(+), 86 deletions(-)
create mode 100644 include/asm-generic/ticket_spinlock.h
diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h
index 4773334ee638..970590baf61b 100644
--- a/include/asm-generic/spinlock.h
+++ b/include/asm-generic/spinlock.h
@@ -1,94 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * 'Generic' ticket-lock implementation.
- *
- * It relies on atomic_fetch_add() having well defined forward progress
- * guarantees under contention. If your architecture cannot provide this, stick
- * to a test-and-set lock.
- *
- * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
- * sub-word of the value. This is generally true for anything LL/SC although
- * you'd be hard pressed to find anything useful in architecture specifications
- * about this. If your architecture cannot do this you might be better off with
- * a test-and-set.
- *
- * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
- * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
- * a full fence after the spin to upgrade the otherwise-RCpc
- * atomic_cond_read_acquire().
- *
- * The implementation uses smp_cond_load_acquire() to spin, so if the
- * architecture has WFE like instructions to sleep instead of poll for word
- * modifications be sure to implement that (see ARM64 for example).
- *
- */
-
#ifndef __ASM_GENERIC_SPINLOCK_H
#define __ASM_GENERIC_SPINLOCK_H
-#include <linux/atomic.h>
-#include <asm-generic/spinlock_types.h>
-
-static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- u32 val = atomic_fetch_add(1<<16, &lock->val);
- u16 ticket = val >> 16;
-
- if (ticket == (u16)val)
- return;
-
- /*
- * atomic_cond_read_acquire() is RCpc, but rather than defining a
- * custom cond_read_rcsc() here we just emit a full fence. We only
- * need the prior reads before subsequent writes ordering from
- * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
- * have no outstanding writes due to the atomic_fetch_add() the extra
- * orderings are free.
- */
- atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);
- smp_mb();
-}
-
-static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
-{
- u32 old = atomic_read(&lock->val);
-
- if ((old >> 16) != (old & 0xffff))
- return false;
-
- return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */
-}
-
-static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
- u32 val = atomic_read(&lock->val);
-
- smp_store_release(ptr, (u16)val + 1);
-}
-
-static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
-{
- u32 val = lock.val.counter;
-
- return ((val >> 16) == (val & 0xffff));
-}
-
-static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- arch_spinlock_t val = READ_ONCE(*lock);
-
- return !arch_spin_value_unlocked(val);
-}
-
-static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
-{
- u32 val = atomic_read(&lock->val);
-
- return (s16)((val >> 16) - (val & 0xffff)) > 1;
-}
-
+#include <asm-generic/ticket_spinlock.h>
#include <asm/qrwlock.h>
#endif /* __ASM_GENERIC_SPINLOCK_H */
diff --git a/include/asm-generic/ticket_spinlock.h b/include/asm-generic/ticket_spinlock.h
new file mode 100644
index 000000000000..cfcff22b37b3
--- /dev/null
+++ b/include/asm-generic/ticket_spinlock.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * 'Generic' ticket-lock implementation.
+ *
+ * It relies on atomic_fetch_add() having well defined forward progress
+ * guarantees under contention. If your architecture cannot provide this, stick
+ * to a test-and-set lock.
+ *
+ * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
+ * sub-word of the value. This is generally true for anything LL/SC although
+ * you'd be hard pressed to find anything useful in architecture specifications
+ * about this. If your architecture cannot do this you might be better off with
+ * a test-and-set.
+ *
+ * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
+ * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
+ * a full fence after the spin to upgrade the otherwise-RCpc
+ * atomic_cond_read_acquire().
+ *
+ * The implementation uses smp_cond_load_acquire() to spin, so if the
+ * architecture has WFE like instructions to sleep instead of poll for word
+ * modifications be sure to implement that (see ARM64 for example).
+ *
+ */
+
+#ifndef __ASM_GENERIC_TICKET_SPINLOCK_H
+#define __ASM_GENERIC_TICKET_SPINLOCK_H
+
+#include <linux/atomic.h>
+#include <asm-generic/spinlock_types.h>
+
+static __always_inline void ticket_spin_lock(arch_spinlock_t *lock)
+{
+ u32 val = atomic_fetch_add(1<<16, &lock->val);
+ u16 ticket = val >> 16;
+
+ if (ticket == (u16)val)
+ return;
+
+ /*
+ * atomic_cond_read_acquire() is RCpc, but rather than defining a
+ * custom cond_read_rcsc() here we just emit a full fence. We only
+ * need the prior reads before subsequent writes ordering from
+ * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
+ * have no outstanding writes due to the atomic_fetch_add() the extra
+ * orderings are free.
+ */
+ atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);
+ smp_mb();
+}
+
+static __always_inline bool ticket_spin_trylock(arch_spinlock_t *lock)
+{
+ u32 old = atomic_read(&lock->val);
+
+ if ((old >> 16) != (old & 0xffff))
+ return false;
+
+ return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */
+}
+
+static __always_inline void ticket_spin_unlock(arch_spinlock_t *lock)
+{
+ u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
+ u32 val = atomic_read(&lock->val);
+
+ smp_store_release(ptr, (u16)val + 1);
+}
+
+static __always_inline int ticket_spin_value_unlocked(arch_spinlock_t lock)
+{
+ u32 val = lock.val.counter;
+
+ return ((val >> 16) == (val & 0xffff));
+}
+
+static __always_inline int ticket_spin_is_locked(arch_spinlock_t *lock)
+{
+ arch_spinlock_t val = READ_ONCE(*lock);
+
+ return !ticket_spin_value_unlocked(val);
+}
+
+static __always_inline int ticket_spin_is_contended(arch_spinlock_t *lock)
+{
+ u32 val = atomic_read(&lock->val);
+
+ return (s16)((val >> 16) - (val & 0xffff)) > 1;
+}
+
+/*
+ * Remapping spinlock architecture specific functions to the corresponding
+ * ticket spinlock functions.
+ */
+#define arch_spin_is_locked(l) ticket_spin_is_locked(l)
+#define arch_spin_is_contended(l) ticket_spin_is_contended(l)
+#define arch_spin_value_unlocked(l) ticket_spin_value_unlocked(l)
+#define arch_spin_lock(l) ticket_spin_lock(l)
+#define arch_spin_trylock(l) ticket_spin_trylock(l)
+#define arch_spin_unlock(l) ticket_spin_unlock(l)
+
+#endif /* __ASM_GENERIC_TICKET_SPINLOCK_H */
--
2.36.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 04/10] asm-generic: spinlock: Add queued spinlock support in common header
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (2 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 03/10] asm-generic: ticket-lock: Move into ticket_spinlock.h guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 05/10] riscv: Enable ARCH_INLINE_READ*/WRITE*/SPIN* guoren
` (5 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Select queued spinlock or ticket lock by CONFIG_QUEUED_SPINLOCKS in
the common header file.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
include/asm-generic/spinlock.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h
index 970590baf61b..f1c29db9c8b5 100644
--- a/include/asm-generic/spinlock.h
+++ b/include/asm-generic/spinlock.h
@@ -3,7 +3,11 @@
#ifndef __ASM_GENERIC_SPINLOCK_H
#define __ASM_GENERIC_SPINLOCK_H
+#ifdef CONFIG_QUEUED_SPINLOCKS
+#include <asm-generic/qspinlock.h>
+#else
#include <asm-generic/ticket_spinlock.h>
+#endif
#include <asm/qrwlock.h>
#endif /* __ASM_GENERIC_SPINLOCK_H */
--
2.36.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 05/10] riscv: Enable ARCH_INLINE_READ*/WRITE*/SPIN*
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (3 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 04/10] asm-generic: spinlock: Add queued spinlock support in common header guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 06/10] riscv: atomic: Clean up unnecessary acquire and release definitions guoren
` (4 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Enable ARCH_INLINE_READ*/WRITE*/SPIN* when !PREEMPTION, it is copied
from arch/arm64. It could reduce procedure calls and improves
performance.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/Kconfig | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fcbb81feb7ad..bff04916a6c5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -32,6 +32,32 @@ config RISCV
select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UBSAN_SANITIZE_ALL
+ select ARCH_INLINE_READ_LOCK if !PREEMPTION
+ select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
+ select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
+ select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
+ select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_STACKWALK
--
2.36.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 06/10] riscv: atomic: Clean up unnecessary acquire and release definitions
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (4 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 05/10] riscv: Enable ARCH_INLINE_READ*/WRITE*/SPIN* guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 07/10] riscv: Add qspinlock support guoren
` (3 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Clean up unnecessary xchg_acquire, xchg_release, and cmpxchg_release
custom definitions, because the generic implementation is the same as
the riscv custom implementation.
Before the patch:
000000000000024e <.LBB238>:
ops = xchg_acquire(pending_ipis, 0);
24e: 089937af amoswap.d a5,s1,(s2)
252: 0230000f fence r,rw
0000000000000256 <.LBB243>:
ops = xchg_release(pending_ipis, 0);
256: 0310000f fence rw,w
25a: 089934af amoswap.d s1,s1,(s2)
After the patch:
000000000000026e <.LBB245>:
ops = xchg_acquire(pending_ipis, 0);
26e: 089937af amoswap.d a5,s1,(s2)
0000000000000272 <.LBE247>:
272: 0230000f fence r,rw
0000000000000276 <.LBB249>:
ops = xchg_release(pending_ipis, 0);
276: 0310000f fence rw,w
000000000000027a <.LBB251>:
27a: 089934af amoswap.d s1,s1,(s2)
Only cmpxchg_acquire is necessary (It prevents unnecessary acquire
ordering when the value from lr is different from old).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/atomic.h | 19 -----
arch/riscv/include/asm/cmpxchg.h | 116 -------------------------------
2 files changed, 135 deletions(-)
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
index 0dfe9d857a76..83636320ba95 100644
--- a/arch/riscv/include/asm/atomic.h
+++ b/arch/riscv/include/asm/atomic.h
@@ -249,16 +249,6 @@ c_t arch_atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \
return __xchg_relaxed(&(v->counter), n, size); \
} \
static __always_inline \
-c_t arch_atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \
-{ \
- return __xchg_acquire(&(v->counter), n, size); \
-} \
-static __always_inline \
-c_t arch_atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \
-{ \
- return __xchg_release(&(v->counter), n, size); \
-} \
-static __always_inline \
c_t arch_atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \
{ \
return __xchg(&(v->counter), n, size); \
@@ -276,12 +266,6 @@ c_t arch_atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \
return __cmpxchg_acquire(&(v->counter), o, n, size); \
} \
static __always_inline \
-c_t arch_atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \
- c_t o, c_t n) \
-{ \
- return __cmpxchg_release(&(v->counter), o, n, size); \
-} \
-static __always_inline \
c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
{ \
return __cmpxchg(&(v->counter), o, n, size); \
@@ -299,12 +283,9 @@ c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
ATOMIC_OPS()
#define arch_atomic_xchg_relaxed arch_atomic_xchg_relaxed
-#define arch_atomic_xchg_acquire arch_atomic_xchg_acquire
-#define arch_atomic_xchg_release arch_atomic_xchg_release
#define arch_atomic_xchg arch_atomic_xchg
#define arch_atomic_cmpxchg_relaxed arch_atomic_cmpxchg_relaxed
#define arch_atomic_cmpxchg_acquire arch_atomic_cmpxchg_acquire
-#define arch_atomic_cmpxchg_release arch_atomic_cmpxchg_release
#define arch_atomic_cmpxchg arch_atomic_cmpxchg
#undef ATOMIC_OPS
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 12debce235e5..67ab6375b650 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -44,76 +44,6 @@
_x_, sizeof(*(ptr))); \
})
-#define __xchg_acquire(ptr, new, size) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(new) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- " amoswap.w %0, %2, %1\n" \
- RISCV_ACQUIRE_BARRIER \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- " amoswap.d %0, %2, %1\n" \
- RISCV_ACQUIRE_BARRIER \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
-})
-
-#define arch_xchg_acquire(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_acquire((ptr), \
- _x_, sizeof(*(ptr))); \
-})
-
-#define __xchg_release(ptr, new, size) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(new) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- " amoswap.w %0, %2, %1\n" \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- " amoswap.d %0, %2, %1\n" \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
-})
-
-#define arch_xchg_release(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_release((ptr), \
- _x_, sizeof(*(ptr))); \
-})
-
#define __xchg(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -253,52 +183,6 @@
_o_, _n_, sizeof(*(ptr))); \
})
-#define __cmpxchg_release(ptr, old, new, size) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(*(ptr)) __old = (old); \
- __typeof__(*(ptr)) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- register unsigned int __rc; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- "0: lr.w %0, %2\n" \
- " bne %0, %z3, 1f\n" \
- " sc.w %1, %z4, %2\n" \
- " bnez %1, 0b\n" \
- "1:\n" \
- : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
- : "rJ" ((long)__old), "rJ" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- "0: lr.d %0, %2\n" \
- " bne %0, %z3, 1f\n" \
- " sc.d %1, %z4, %2\n" \
- " bnez %1, 0b\n" \
- "1:\n" \
- : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
- : "rJ" (__old), "rJ" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
-})
-
-#define arch_cmpxchg_release(ptr, o, n) \
-({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg_release((ptr), \
- _o_, _n_, sizeof(*(ptr))); \
-})
-
#define __cmpxchg(ptr, old, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
--
2.36.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 07/10] riscv: Add qspinlock support
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (5 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 06/10] riscv: atomic: Clean up unnecessary acquire and release definitions guoren
@ 2022-07-24 12:25 ` guoren
2022-07-28 0:04 ` kernel test robot
2022-07-24 12:25 ` [PATCH V8 08/10] riscv: Add combo spinlock support guoren
` (2 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Enable qspinlock by the requirements mentioned in a8ad07e5240c9
("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
- RISC-V atomic_*_release()/atomic_*_acquire() are implemented with
own relaxed version plus acquire/release_fence for RCsc
synchronization.
- RISC-V LR/SC pairs could provide a strong/weak forward guarantee
that depends on micro-architecture. And RISC-V ISA spec has given
out several limitations to let hardware support strict forward
guarantee (RISC-V User ISA - 8.3 Eventual Success of
Store-Conditional Instructions). Some riscv cores such as BOOMv3
& XiangShan could provide strict & strong forward guarantee (The
cache line would be kept in an exclusive state for Backoff cycles,
and only this core's interrupt could break the LR/SC pair).
- RISC-V provides cheap atomic_fetch_or_acquire() with RCsc.
- RISC-V only provides relaxed xchg16 to support qspinlock.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/Kconfig | 16 ++++++++++++++++
arch/riscv/include/asm/Kbuild | 2 ++
arch/riscv/include/asm/cmpxchg.h | 17 +++++++++++++++++
3 files changed, 35 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index bff04916a6c5..721f098228a8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -359,6 +359,22 @@ config NODES_SHIFT
Specify the maximum number of NUMA Nodes available on the target
system. Increases memory reserved to accommodate various tables.
+choice
+ prompt "RISC-V spinlock type"
+ default RISCV_TICKET_SPINLOCKS
+
+config RISCV_TICKET_SPINLOCKS
+ bool "Using ticket spinlock"
+
+config RISCV_QUEUED_SPINLOCKS
+ bool "Using queued spinlock"
+ depends on SMP && MMU
+ select ARCH_USE_QUEUED_SPINLOCKS
+ help
+ Make sure your micro arch LL/SC has a strong forward progress guarantee.
+ Otherwise, stay at ticket-lock/combo-lock.
+endchoice
+
config RISCV_ALTERNATIVE
bool
depends on !XIP_KERNEL
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 504f8b7e72d4..2cce98c7b653 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -2,7 +2,9 @@
generic-y += early_ioremap.h
generic-y += flat.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
generic-y += parport.h
+generic-y += qspinlock.h
generic-y += spinlock.h
generic-y += spinlock_types.h
generic-y += qrwlock.h
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 67ab6375b650..6bf2726d4500 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -17,6 +17,23 @@
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
switch (size) { \
+ case 2: { \
+ u32 tmp, ret; \
+ u32 shif = ((ulong)__ptr & 2) ? 16 : 0; \
+ u32 mask = 0xffff << shif; \
+ __ptr = (__typeof__(ptr))((ulong)__ptr & ~2); \
+ __asm__ __volatile__ ( \
+ "0: lr.w %0, %2\n" \
+ " and %1, %0, %z3\n" \
+ " or %1, %1, %z4\n" \
+ " sc.w %1, %1, %2\n" \
+ " bnez %1, 0b\n" \
+ : "=&r" (ret), "=&r" (tmp), "+A" (*__ptr) \
+ : "rJ" (~mask), "rJ" ((u32)__new << shif) \
+ : "memory"); \
+ __ret = (__typeof__(*(ptr)))((ret & mask) >> shif); \
+ break; \
+ } \
case 4: \
__asm__ __volatile__ ( \
" amoswap.w %0, %2, %1\n" \
--
2.36.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V8 07/10] riscv: Add qspinlock support
2022-07-24 12:25 ` [PATCH V8 07/10] riscv: Add qspinlock support guoren
@ 2022-07-28 0:04 ` kernel test robot
2022-07-28 3:35 ` Guo Ren
0 siblings, 1 reply; 18+ messages in thread
From: kernel test robot @ 2022-07-28 0:04 UTC (permalink / raw)
To: guoren, palmer, heiko, hch, arnd, peterz, will, boqun.feng,
longman, mingo, philipp.tomsich, cmuellner, linux-kernel,
David.Laight
Cc: llvm, kbuild-all, linux-riscv, linux-csky, Guo Ren
Hi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on arnd-asm-generic/master]
[also build test WARNING on linus/master v5.19-rc8 next-20220727]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/guoren-kernel-org/arch-Add-qspinlock-support-with-combo-style/20220724-202743
base: https://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic.git master
config: riscv-randconfig-r026-20220727 (https://download.01.org/0day-ci/archive/20220728/202207280822.VHS6qieH-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 8dfaecc4c24494337933aff9d9166486ca0949f1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/980c0acb7f432777e3473ab9a5696044e03b3f3d
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review guoren-kernel-org/arch-Add-qspinlock-support-with-combo-style/20220724-202743
git checkout 980c0acb7f432777e3473ab9a5696044e03b3f3d
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/net/wireguard/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from drivers/net/wireguard/queueing.c:6:
In file included from drivers/net/wireguard/queueing.h:9:
In file included from drivers/net/wireguard/peer.h:9:
In file included from drivers/net/wireguard/device.h:9:
In file included from drivers/net/wireguard/noise.h:8:
In file included from drivers/net/wireguard/messages.h:10:
In file included from include/crypto/chacha20poly1305.h:10:
In file included from include/linux/scatterlist.h:9:
In file included from arch/riscv/include/asm/io.h:136:
include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __raw_readb(PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
^
In file included from drivers/net/wireguard/queueing.c:6:
In file included from drivers/net/wireguard/queueing.h:9:
In file included from drivers/net/wireguard/peer.h:9:
In file included from drivers/net/wireguard/device.h:9:
In file included from drivers/net/wireguard/noise.h:8:
In file included from drivers/net/wireguard/messages.h:10:
In file included from include/crypto/chacha20poly1305.h:10:
In file included from include/linux/scatterlist.h:9:
In file included from arch/riscv/include/asm/io.h:136:
include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
^
In file included from drivers/net/wireguard/queueing.c:6:
In file included from drivers/net/wireguard/queueing.h:9:
In file included from drivers/net/wireguard/peer.h:9:
In file included from drivers/net/wireguard/device.h:9:
In file included from drivers/net/wireguard/noise.h:8:
In file included from drivers/net/wireguard/messages.h:10:
In file included from include/crypto/chacha20poly1305.h:10:
In file included from include/linux/scatterlist.h:9:
In file included from arch/riscv/include/asm/io.h:136:
include/asm-generic/io.h:584:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writeb(value, PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:594:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:604:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:1107:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
~~~~~~~~~~ ^
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
^~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
^~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
^~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
^~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 6 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
^~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 6 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
#define NEXT(skb) ((skb)->prev)
^~~
include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
__WRITE_ONCE(x, val); \
^
include/asm-generic/rwonce.h:55:20: note: expanded from macro '__WRITE_ONCE'
*(volatile typeof(x) *)&(x) = (val); \
^
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
#define NEXT(skb) ((skb)->prev)
^
include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
__WRITE_ONCE(x, val); \
~~~~~~~~~~~~~^~~~~~~
include/asm-generic/rwonce.h:55:20: note: expanded from macro '__WRITE_ONCE'
*(volatile typeof(x) *)&(x) = (val); \
^
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^~~~~~~~~~~~~~~~~~
note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
#define NEXT(skb) ((skb)->prev)
^~~
include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
__WRITE_ONCE(x, val); \
^
include/asm-generic/rwonce.h:55:27: note: expanded from macro '__WRITE_ONCE'
*(volatile typeof(x) *)&(x) = (val); \
^
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
arch_xchg_release(__ai_ptr, __VA_ARGS__); \
^
include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
__atomic_op_release(arch_xchg, __VA_ARGS__)
^
include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
op##_relaxed(args); \
^
note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
#define NEXT(skb) ((skb)->prev)
^
include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
__WRITE_ONCE(x, val); \
~~~~~~~~~~~~~^~~~~~~
include/asm-generic/rwonce.h:55:27: note: expanded from macro '__WRITE_ONCE'
*(volatile typeof(x) *)&(x) = (val); \
^
21 warnings generated.
vim +68 drivers/net/wireguard/queueing.c
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 64
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 65 static void __wg_prev_queue_enqueue(struct prev_queue *queue, struct sk_buff *skb)
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 66 {
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 67 WRITE_ONCE(NEXT(skb), NULL);
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 @68 WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 69 }
8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 70
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V8 07/10] riscv: Add qspinlock support
2022-07-28 0:04 ` kernel test robot
@ 2022-07-28 3:35 ` Guo Ren
2022-07-28 8:14 ` Arnd Bergmann
0 siblings, 1 reply; 18+ messages in thread
From: Guo Ren @ 2022-07-28 3:35 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Heiko Stübner, Christoph Hellwig, Arnd Bergmann,
Peter Zijlstra, Will Deacon, Boqun Feng, Waiman Long,
Ingo Molnar, Philipp Tomsich, Christoph Muellner,
Linux Kernel Mailing List, David Laight, llvm, kbuild-all,
linux-riscv, linux-csky, Guo Ren
Hi Palmer,
The warning is from a clang problem.
drivers/net/wireguard/queueing.c:
static void __wg_prev_queue_enqueue(struct prev_queue *queue, struct
sk_buff *skb)
{
WRITE_ONCE(NEXT(skb), NULL);
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
}
The queue->head is 64bit pointer size.
#define __xchg_relaxed(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
switch (size) { \
case 2: { \
... Clang shouldn't give warning from here, because code won't enter the path.
break; \
} \
case 4: \
...
break; \
case 8: \
... The case would enter this path.
break; \
default: \
BUILD_BUG(); \
} \
__ret; \
})
On Thu, Jul 28, 2022 at 8:05 AM kernel test robot <lkp@intel.com> wrote:
>
> Hi,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on arnd-asm-generic/master]
> [also build test WARNING on linus/master v5.19-rc8 next-20220727]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/guoren-kernel-org/arch-Add-qspinlock-support-with-combo-style/20220724-202743
> base: https://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic.git master
> config: riscv-randconfig-r026-20220727 (https://download.01.org/0day-ci/archive/20220728/202207280822.VHS6qieH-lkp@intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 8dfaecc4c24494337933aff9d9166486ca0949f1)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install riscv cross compiling tool for clang build
> # apt-get install binutils-riscv64-linux-gnu
> # https://github.com/intel-lab-lkp/linux/commit/980c0acb7f432777e3473ab9a5696044e03b3f3d
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review guoren-kernel-org/arch-Add-qspinlock-support-with-combo-style/20220724-202743
> git checkout 980c0acb7f432777e3473ab9a5696044e03b3f3d
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/net/wireguard/
>
> If you fix the issue, kindly add following tag where applicable
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> In file included from drivers/net/wireguard/queueing.c:6:
> In file included from drivers/net/wireguard/queueing.h:9:
> In file included from drivers/net/wireguard/peer.h:9:
> In file included from drivers/net/wireguard/device.h:9:
> In file included from drivers/net/wireguard/noise.h:8:
> In file included from drivers/net/wireguard/messages.h:10:
> In file included from include/crypto/chacha20poly1305.h:10:
> In file included from include/linux/scatterlist.h:9:
> In file included from arch/riscv/include/asm/io.h:136:
> include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> val = __raw_readb(PCI_IOBASE + addr);
> ~~~~~~~~~~ ^
> include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
> ~~~~~~~~~~ ^
> include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
> #define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
> ^
> In file included from drivers/net/wireguard/queueing.c:6:
> In file included from drivers/net/wireguard/queueing.h:9:
> In file included from drivers/net/wireguard/peer.h:9:
> In file included from drivers/net/wireguard/device.h:9:
> In file included from drivers/net/wireguard/noise.h:8:
> In file included from drivers/net/wireguard/messages.h:10:
> In file included from include/crypto/chacha20poly1305.h:10:
> In file included from include/linux/scatterlist.h:9:
> In file included from arch/riscv/include/asm/io.h:136:
> include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
> ~~~~~~~~~~ ^
> include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
> #define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
> ^
> In file included from drivers/net/wireguard/queueing.c:6:
> In file included from drivers/net/wireguard/queueing.h:9:
> In file included from drivers/net/wireguard/peer.h:9:
> In file included from drivers/net/wireguard/device.h:9:
> In file included from drivers/net/wireguard/noise.h:8:
> In file included from drivers/net/wireguard/messages.h:10:
> In file included from include/crypto/chacha20poly1305.h:10:
> In file included from include/linux/scatterlist.h:9:
> In file included from arch/riscv/include/asm/io.h:136:
> include/asm-generic/io.h:584:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> __raw_writeb(value, PCI_IOBASE + addr);
> ~~~~~~~~~~ ^
> include/asm-generic/io.h:594:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
> ~~~~~~~~~~ ^
> include/asm-generic/io.h:604:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
> ~~~~~~~~~~ ^
> include/asm-generic/io.h:1107:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
> ~~~~~~~~~~ ^
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ^~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ^~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ^~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ^~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ^~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ^~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ^~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ^~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 7 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 6 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ^~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ^~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 6 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> include/linux/compiler_types.h:352:22: note: expanded from macro 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
> ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:340:23: note: expanded from macro '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/compiler_types.h:332:9: note: expanded from macro '__compiletime_assert'
> if (!(condition)) \
> ^~~~~~~~~
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
> #define NEXT(skb) ((skb)->prev)
> ^~~
> include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
> __WRITE_ONCE(x, val); \
> ^
> include/asm-generic/rwonce.h:55:20: note: expanded from macro '__WRITE_ONCE'
> *(volatile typeof(x) *)&(x) = (val); \
> ^
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
> #define NEXT(skb) ((skb)->prev)
> ^
> include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
> __WRITE_ONCE(x, val); \
> ~~~~~~~~~~~~~^~~~~~~
> include/asm-generic/rwonce.h:55:20: note: expanded from macro '__WRITE_ONCE'
> *(volatile typeof(x) *)&(x) = (val); \
> ^
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to smaller integer type 'u32' (aka 'unsigned int') from 'typeof (_x_)' (aka 'struct sk_buff *') [-Wpointer-to-int-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^~~~~~~~~~~~~~~~~~
> note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
> #define NEXT(skb) ((skb)->prev)
> ^~~
> include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
> __WRITE_ONCE(x, val); \
> ^
> include/asm-generic/rwonce.h:55:27: note: expanded from macro '__WRITE_ONCE'
> *(volatile typeof(x) *)&(x) = (val); \
> ^
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> include/linux/atomic/atomic-instrumented.h:1901:2: note: expanded from macro 'xchg_release'
> arch_xchg_release(__ai_ptr, __VA_ARGS__); \
> ^
> include/linux/atomic/atomic-arch-fallback.h:24:2: note: expanded from macro 'arch_xchg_release'
> __atomic_op_release(arch_xchg, __VA_ARGS__)
> ^
> include/linux/atomic.h:68:2: note: expanded from macro '__atomic_op_release'
> op##_relaxed(args); \
> ^
> note: (skipping 3 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
> drivers/net/wireguard/queueing.c:49:21: note: expanded from macro 'NEXT'
> #define NEXT(skb) ((skb)->prev)
> ^
> include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
> __WRITE_ONCE(x, val); \
> ~~~~~~~~~~~~~^~~~~~~
> include/asm-generic/rwonce.h:55:27: note: expanded from macro '__WRITE_ONCE'
> *(volatile typeof(x) *)&(x) = (val); \
> ^
> 21 warnings generated.
>
>
> vim +68 drivers/net/wireguard/queueing.c
>
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 64
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 65 static void __wg_prev_queue_enqueue(struct prev_queue *queue, struct sk_buff *skb)
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 66 {
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 67 WRITE_ONCE(NEXT(skb), NULL);
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 @68 WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 69 }
> 8b5553ace83cced7 Jason A. Donenfeld 2021-02-22 70
>
> --
> 0-DAY CI Kernel Test Service
> https://01.org/lkp
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V8 07/10] riscv: Add qspinlock support
2022-07-28 3:35 ` Guo Ren
@ 2022-07-28 8:14 ` Arnd Bergmann
2022-07-28 8:34 ` Guo Ren
0 siblings, 1 reply; 18+ messages in thread
From: Arnd Bergmann @ 2022-07-28 8:14 UTC (permalink / raw)
To: Guo Ren
Cc: Palmer Dabbelt, Heiko Stübner, Christoph Hellwig,
Arnd Bergmann, Peter Zijlstra, Will Deacon, Boqun Feng,
Waiman Long, Ingo Molnar, Philipp Tomsich, Christoph Muellner,
Linux Kernel Mailing List, David Laight, clang-built-linux,
kbuild-all, linux-riscv, linux-csky, Guo Ren, Niklas Schnelle
On Thu, Jul 28, 2022 at 5:35 AM Guo Ren <guoren@kernel.org> wrote:
>
> Hi Palmer,
>
> The warning is from a clang problem.
>
> drivers/net/wireguard/queueing.c:
> static void __wg_prev_queue_enqueue(struct prev_queue *queue, struct
> sk_buff *skb)
> {
> WRITE_ONCE(NEXT(skb), NULL);
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> }
>
> The queue->head is 64bit pointer size.
>
> #define __xchg_relaxed(ptr, new, size) \
> ({ \
> __typeof__(ptr) __ptr = (ptr); \
> __typeof__(new) __new = (new); \
> __typeof__(*(ptr)) __ret; \
> switch (size) { \
> case 2: { \
> ... Clang shouldn't give warning from here, because code won't enter the path.
> break; \
> } \
> case 4: \
> ...
> break; \
> case 8: \
> ... The case would enter this path.
> break; \
> default: \
> BUILD_BUG(); \
> } \
> __ret; \
> })
I assume it's this warning you are referring to?
>> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
I don't consider this a bug in clang, it just performs the normal type checking
before dead code elimination and complains about code that clearly violates
the type rules.
I would suggest you split out the 16-bit xchg() into a properly typed inline
function and add type casts when calling it. In fact, I would love to
completely eliminate the 8-bit and 16-bit cases from the regular xchg()
and cmpxchg() interface and require all callers to explicitly call the
xchg16()/cmpxchg16() instead, as we require for cmpxchg64() on 32-bit
architectures already. This is something to do for another time though.
> > include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> > val = __raw_readb(PCI_IOBASE + addr);
> > ~~~~~~~~~~ ^
> > include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> > val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
Not your bug, but I see that CONFIG_MMU=n risc-v has the same bug that s390 has
with missing I/O space support. The correct workaround for this is to mark all
drivers using PCI I/O space as 'depends on HAS_IO_PORT' or similar and then
leaving out the definitions from the asm-generic header. Niklas Schnelle has
spent a lot of time working on patches for this, but they are somewhat stuck
in review. If RISC-V has the same problem, I hope we can get more people
interested in it. I think OpenRISC and C-Sky have this as well, but I'm not
sure if there is any plan to upstream clang support for those.
Arnd
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V8 07/10] riscv: Add qspinlock support
2022-07-28 8:14 ` Arnd Bergmann
@ 2022-07-28 8:34 ` Guo Ren
0 siblings, 0 replies; 18+ messages in thread
From: Guo Ren @ 2022-07-28 8:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Palmer Dabbelt, Heiko Stübner, Christoph Hellwig,
Peter Zijlstra, Will Deacon, Boqun Feng, Waiman Long,
Ingo Molnar, Philipp Tomsich, Christoph Muellner,
Linux Kernel Mailing List, David Laight, clang-built-linux,
kbuild-all, linux-riscv, linux-csky, Guo Ren, Niklas Schnelle
On Thu, Jul 28, 2022 at 4:14 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Thu, Jul 28, 2022 at 5:35 AM Guo Ren <guoren@kernel.org> wrote:
> >
> > Hi Palmer,
> >
> > The warning is from a clang problem.
> >
> > drivers/net/wireguard/queueing.c:
> > static void __wg_prev_queue_enqueue(struct prev_queue *queue, struct
> > sk_buff *skb)
> > {
> > WRITE_ONCE(NEXT(skb), NULL);
> > WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
> > }
> >
> > The queue->head is 64bit pointer size.
> >
> > #define __xchg_relaxed(ptr, new, size) \
> > ({ \
> > __typeof__(ptr) __ptr = (ptr); \
> > __typeof__(new) __new = (new); \
> > __typeof__(*(ptr)) __ret; \
> > switch (size) { \
> > case 2: { \
> > ... Clang shouldn't give warning from here, because code won't enter the path.
> > break; \
> > } \
> > case 4: \
> > ...
> > break; \
> > case 8: \
> > ... The case would enter this path.
> > break; \
> > default: \
> > BUILD_BUG(); \
> > } \
> > __ret; \
> > })
>
> I assume it's this warning you are referring to?
>
> >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast]
> WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb);
>
> I don't consider this a bug in clang, it just performs the normal type checking
> before dead code elimination and complains about code that clearly violates
> the type rules.
>
> I would suggest you split out the 16-bit xchg() into a properly typed inline
> function and add type casts when calling it.
Okay, I would try that style.
> In fact, I would love to
> completely eliminate the 8-bit and 16-bit cases from the regular xchg()
> and cmpxchg() interface and require all callers to explicitly call the
> xchg16()/cmpxchg16() instead, as we require for cmpxchg64() on 32-bit
> architectures already. This is something to do for another time though.
>
> > > include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> > > val = __raw_readb(PCI_IOBASE + addr);
> > > ~~~~~~~~~~ ^
> > > include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
> > > val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
>
> Not your bug, but I see that CONFIG_MMU=n risc-v has the same bug that s390 has
> with missing I/O space support. The correct workaround for this is to mark all
> drivers using PCI I/O space as 'depends on HAS_IO_PORT' or similar and then
> leaving out the definitions from the asm-generic header. Niklas Schnelle has
> spent a lot of time working on patches for this, but they are somewhat stuck
> in review. If RISC-V has the same problem, I hope we can get more people
> interested in it. I think OpenRISC and C-Sky have this as well, but I'm not
> sure if there is any plan to upstream clang support for those.
C-SKY hasn't any plan to support clang, as I know.
>
> Arnd
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH V8 08/10] riscv: Add combo spinlock support
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (6 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 07/10] riscv: Add qspinlock support guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 09/10] csky: Enable ARCH_INLINE_READ*/WRITE*/SPIN* guoren
2022-07-24 12:25 ` [PATCH V8 10/10] csky: Add qspinlock support guoren
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Combo spinlock could support queued and ticket in one Linux Image and
select them during boot time with command line option. Here is the
func-size(Bytes) comparison table below:
TYPE : COMBO | TICKET | QUEUED
arch_spin_lock : 106 | 60 | 50
arch_spin_unlock : 54 | 36 | 26
arch_spin_trylock : 110 | 72 | 54
arch_spin_is_locked : 48 | 34 | 20
arch_spin_is_contended : 56 | 40 | 24
rch_spin_value_unlocked : 48 | 34 | 24
One example of disassemble combo arch_spin_unlock:
0xffffffff8000409c <+14>: nop # jump label slot
0xffffffff800040a0 <+18>: fence rw,w # queued spinlock start
0xffffffff800040a4 <+22>: sb zero,0(a4) # queued spinlock end
0xffffffff800040a8 <+26>: ld s0,8(sp)
0xffffffff800040aa <+28>: addi sp,sp,16
0xffffffff800040ac <+30>: ret
0xffffffff800040ae <+32>: lw a5,0(a4) # ticket spinlock start
0xffffffff800040b0 <+34>: sext.w a5,a5
0xffffffff800040b2 <+36>: fence rw,w
0xffffffff800040b6 <+40>: addiw a5,a5,1
0xffffffff800040b8 <+42>: slli a5,a5,0x30
0xffffffff800040ba <+44>: srli a5,a5,0x30
0xffffffff800040bc <+46>: sh a5,0(a4) # ticket spinlock end
0xffffffff800040c0 <+50>: ld s0,8(sp)
0xffffffff800040c2 <+52>: addi sp,sp,16
0xffffffff800040c4 <+54>: ret
We could see queued spinlock is better than ticket-lock when there is no
contend into queued_spin_lock_slowpath. And combo could provide a
compatible Linux Image for a different kind of micro-arch design.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/Kconfig | 9 +++-
arch/riscv/include/asm/Kbuild | 1 -
arch/riscv/include/asm/spinlock.h | 77 +++++++++++++++++++++++++++++++
arch/riscv/kernel/setup.c | 22 +++++++++
4 files changed, 107 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/include/asm/spinlock.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 721f098228a8..f1d68491a1cf 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -361,7 +361,7 @@ config NODES_SHIFT
choice
prompt "RISC-V spinlock type"
- default RISCV_TICKET_SPINLOCKS
+ default RISCV_COMBO_SPINLOCKS
config RISCV_TICKET_SPINLOCKS
bool "Using ticket spinlock"
@@ -373,6 +373,13 @@ config RISCV_QUEUED_SPINLOCKS
help
Make sure your micro arch LL/SC has a strong forward progress guarantee.
Otherwise, stay at ticket-lock/combo-lock.
+
+config RISCV_COMBO_SPINLOCKS
+ bool "Using combo spinlock"
+ depends on SMP && MMU
+ select ARCH_USE_QUEUED_SPINLOCKS
+ help
+ Select queued spinlock or ticket-lock with jump_label.
endchoice
config RISCV_ALTERNATIVE
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 2cce98c7b653..59d5ea7390ea 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -5,7 +5,6 @@ generic-y += kvm_para.h
generic-y += mcs_spinlock.h
generic-y += parport.h
generic-y += qspinlock.h
-generic-y += spinlock.h
generic-y += spinlock_types.h
generic-y += qrwlock.h
generic-y += qrwlock_types.h
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
new file mode 100644
index 000000000000..b079462d818b
--- /dev/null
+++ b/arch/riscv/include/asm/spinlock.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_RISCV_SPINLOCK_H
+#define __ASM_RISCV_SPINLOCK_H
+
+#ifdef CONFIG_RISCV_COMBO_SPINLOCKS
+#include <asm-generic/ticket_spinlock.h>
+
+#undef arch_spin_is_locked
+#undef arch_spin_is_contended
+#undef arch_spin_value_unlocked
+#undef arch_spin_lock
+#undef arch_spin_trylock
+#undef arch_spin_unlock
+
+#include <asm-generic/qspinlock.h>
+#include <linux/jump_label.h>
+
+#undef arch_spin_is_locked
+#undef arch_spin_is_contended
+#undef arch_spin_value_unlocked
+#undef arch_spin_lock
+#undef arch_spin_trylock
+#undef arch_spin_unlock
+
+DECLARE_STATIC_KEY_TRUE(qspinlock_key);
+
+static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
+{
+ if (static_branch_likely(&qspinlock_key))
+ queued_spin_lock(lock);
+ else
+ ticket_spin_lock(lock);
+}
+
+static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
+{
+ if (static_branch_likely(&qspinlock_key))
+ return queued_spin_trylock(lock);
+ return ticket_spin_trylock(lock);
+}
+
+static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
+{
+ if (static_branch_likely(&qspinlock_key))
+ queued_spin_unlock(lock);
+ else
+ ticket_spin_unlock(lock);
+}
+
+static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
+{
+ if (static_branch_likely(&qspinlock_key))
+ return queued_spin_value_unlocked(lock);
+ else
+ return ticket_spin_value_unlocked(lock);
+}
+
+static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+ if (static_branch_likely(&qspinlock_key))
+ return queued_spin_is_locked(lock);
+ return ticket_spin_is_locked(lock);
+}
+
+static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
+{
+ if (static_branch_likely(&qspinlock_key))
+ return queued_spin_is_contended(lock);
+ return ticket_spin_is_contended(lock);
+}
+#include <asm/qrwlock.h>
+#else
+#include <asm-generic/spinlock.h>
+#endif /* CONFIG_RISCV_COMBO_SPINLOCKS */
+
+#endif /* __ASM_RISCV_SPINLOCK_H */
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index f0f36a4a0e9b..b763039bf49b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -261,6 +261,13 @@ static void __init parse_dtb(void)
#endif
}
+#ifdef CONFIG_RISCV_COMBO_SPINLOCKS
+DEFINE_STATIC_KEY_TRUE_RO(qspinlock_key);
+EXPORT_SYMBOL(qspinlock_key);
+
+static bool qspinlock_flag __initdata = false;
+#endif
+
void __init setup_arch(char **cmdline_p)
{
parse_dtb();
@@ -295,10 +302,25 @@ void __init setup_arch(char **cmdline_p)
setup_smp();
#endif
+#ifdef CONFIG_RISCV_COMBO_SPINLOCKS
+ if (!qspinlock_flag)
+ static_branch_disable(&qspinlock_key);
+#endif
+
riscv_fill_hwcap();
apply_boot_alternatives();
}
+#ifdef CONFIG_RISCV_COMBO_SPINLOCKS
+static int __init enable_qspinlock(char *p)
+{
+ qspinlock_flag = true;
+
+ return 0;
+}
+early_param("qspinlock", enable_qspinlock);
+#endif
+
static int __init topology_init(void)
{
int i, ret;
--
2.36.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 09/10] csky: Enable ARCH_INLINE_READ*/WRITE*/SPIN*
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (7 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 08/10] riscv: Add combo spinlock support guoren
@ 2022-07-24 12:25 ` guoren
2022-07-24 12:25 ` [PATCH V8 10/10] csky: Add qspinlock support guoren
9 siblings, 0 replies; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Enable ARCH_INLINE_READ*/WRITE*/SPIN* when !PREEMPTION, it is copied
from arch/arm64. It could reduce procedure calls and improves
performance.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/csky/Kconfig | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig
index 21d72b078eef..dfdb436b6078 100644
--- a/arch/csky/Kconfig
+++ b/arch/csky/Kconfig
@@ -8,6 +8,32 @@ config CSKY
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_QUEUED_RWLOCKS
+ select ARCH_INLINE_READ_LOCK if !PREEMPTION
+ select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
+ select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
+ select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
+ select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
+ select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
select COMMON_CLK
--
2.36.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH V8 10/10] csky: Add qspinlock support
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
` (8 preceding siblings ...)
2022-07-24 12:25 ` [PATCH V8 09/10] csky: Enable ARCH_INLINE_READ*/WRITE*/SPIN* guoren
@ 2022-07-24 12:25 ` guoren
2022-07-25 2:08 ` Waiman Long
9 siblings, 1 reply; 18+ messages in thread
From: guoren @ 2022-07-24 12:25 UTC (permalink / raw)
To: palmer, heiko, hch, arnd, peterz, will, boqun.feng, longman,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Enable qspinlock by the requirements mentioned in a8ad07e5240c9
("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
C-SKY only has "ldex/stex" for all atomic operations. So csky give a
strong forward guarantee for "ldex/stex." That means when ldex grabbed
the cache line into $L1, it would block other cores from snooping the
address with several cycles.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/csky/Kconfig | 16 ++++++++++++++++
arch/csky/include/asm/Kbuild | 2 ++
arch/csky/include/asm/cmpxchg.h | 20 ++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig
index dfdb436b6078..09f7d1f06bca 100644
--- a/arch/csky/Kconfig
+++ b/arch/csky/Kconfig
@@ -354,6 +354,22 @@ config HAVE_EFFICIENT_UNALIGNED_STRING_OPS
Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could
deal with unaligned access by hardware.
+choice
+ prompt "C-SKY spinlock type"
+ default CSKY_TICKET_SPINLOCKS
+
+config CSKY_TICKET_SPINLOCKS
+ bool "Using ticket spinlock"
+
+config CSKY_QUEUED_SPINLOCKS
+ bool "Using queued spinlock"
+ depends on SMP
+ select ARCH_USE_QUEUED_SPINLOCKS
+ help
+ Make sure your micro arch LL/SC has a strong forward progress guarantee.
+ Otherwise, stay at ticket-lock/combo-lock.
+endchoice
+
endmenu
source "arch/csky/Kconfig.platforms"
diff --git a/arch/csky/include/asm/Kbuild b/arch/csky/include/asm/Kbuild
index 103207a58f97..b70b14de904f 100644
--- a/arch/csky/include/asm/Kbuild
+++ b/arch/csky/include/asm/Kbuild
@@ -3,10 +3,12 @@ generic-y += asm-offsets.h
generic-y += extable.h
generic-y += gpio.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
generic-y += spinlock.h
generic-y += spinlock_types.h
generic-y += qrwlock.h
generic-y += qrwlock_types.h
+generic-y += qspinlock.h
generic-y += parport.h
generic-y += user.h
generic-y += vmlinux.lds.h
diff --git a/arch/csky/include/asm/cmpxchg.h b/arch/csky/include/asm/cmpxchg.h
index 5b8faccd65e4..5f693fadb56c 100644
--- a/arch/csky/include/asm/cmpxchg.h
+++ b/arch/csky/include/asm/cmpxchg.h
@@ -15,6 +15,26 @@ extern void __bad_xchg(void);
__typeof__(*(ptr)) __ret; \
unsigned long tmp; \
switch (size) { \
+ case 2: { \
+ u32 ret; \
+ u32 shif = ((ulong)__ptr & 2) ? 16 : 0; \
+ u32 mask = 0xffff << shif; \
+ __ptr = (__typeof__(ptr))((ulong)__ptr & ~2); \
+ __asm__ __volatile__ ( \
+ "1: ldex.w %0, (%4)\n" \
+ " and %1, %0, %2\n" \
+ " or %1, %1, %3\n" \
+ " stex.w %1, (%4)\n" \
+ " bez %1, 1b\n" \
+ : "=&r" (ret), "=&r" (tmp) \
+ : "r" (~mask), \
+ "r" ((u32)__new << shif), \
+ "r" (__ptr) \
+ : "memory"); \
+ __ret = (__typeof__(*(ptr))) \
+ ((ret & mask) >> shif); \
+ break; \
+ } \
case 4: \
asm volatile ( \
"1: ldex.w %0, (%3) \n" \
--
2.36.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH V8 10/10] csky: Add qspinlock support
2022-07-24 12:25 ` [PATCH V8 10/10] csky: Add qspinlock support guoren
@ 2022-07-25 2:08 ` Waiman Long
2022-07-25 2:30 ` Guo Ren
0 siblings, 1 reply; 18+ messages in thread
From: Waiman Long @ 2022-07-25 2:08 UTC (permalink / raw)
To: guoren, palmer, heiko, hch, arnd, peterz, will, boqun.feng,
mingo, philipp.tomsich, cmuellner, linux-kernel, David.Laight
Cc: linux-riscv, linux-csky, Guo Ren
On 7/24/22 08:25, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Enable qspinlock by the requirements mentioned in a8ad07e5240c9
> ("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
>
> C-SKY only has "ldex/stex" for all atomic operations. So csky give a
> strong forward guarantee for "ldex/stex." That means when ldex grabbed
> the cache line into $L1, it would block other cores from snooping the
> address with several cycles.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
> arch/csky/Kconfig | 16 ++++++++++++++++
> arch/csky/include/asm/Kbuild | 2 ++
> arch/csky/include/asm/cmpxchg.h | 20 ++++++++++++++++++++
> 3 files changed, 38 insertions(+)
>
> diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig
> index dfdb436b6078..09f7d1f06bca 100644
> --- a/arch/csky/Kconfig
> +++ b/arch/csky/Kconfig
> @@ -354,6 +354,22 @@ config HAVE_EFFICIENT_UNALIGNED_STRING_OPS
> Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could
> deal with unaligned access by hardware.
>
> +choice
> + prompt "C-SKY spinlock type"
> + default CSKY_TICKET_SPINLOCKS
> +
> +config CSKY_TICKET_SPINLOCKS
> + bool "Using ticket spinlock"
> +
> +config CSKY_QUEUED_SPINLOCKS
> + bool "Using queued spinlock"
> + depends on SMP
> + select ARCH_USE_QUEUED_SPINLOCKS
> + help
> + Make sure your micro arch LL/SC has a strong forward progress guarantee.
> + Otherwise, stay at ticket-lock/combo-lock.
"combo-lock"? It is a cut-and-paste error. Right?
Cheers,
Longman
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH V8 10/10] csky: Add qspinlock support
2022-07-25 2:08 ` Waiman Long
@ 2022-07-25 2:30 ` Guo Ren
0 siblings, 0 replies; 18+ messages in thread
From: Guo Ren @ 2022-07-25 2:30 UTC (permalink / raw)
To: Waiman Long
Cc: Palmer Dabbelt, Heiko Stübner, Christoph Hellwig,
Arnd Bergmann, Peter Zijlstra, Will Deacon, Boqun Feng,
Ingo Molnar, Philipp Tomsich, Christoph Muellner,
Linux Kernel Mailing List, David Laight, linux-riscv, linux-csky,
Guo Ren
On Mon, Jul 25, 2022 at 10:08 AM Waiman Long <longman@redhat.com> wrote:
>
> On 7/24/22 08:25, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Enable qspinlock by the requirements mentioned in a8ad07e5240c9
> > ("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
> >
> > C-SKY only has "ldex/stex" for all atomic operations. So csky give a
> > strong forward guarantee for "ldex/stex." That means when ldex grabbed
> > the cache line into $L1, it would block other cores from snooping the
> > address with several cycles.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/csky/Kconfig | 16 ++++++++++++++++
> > arch/csky/include/asm/Kbuild | 2 ++
> > arch/csky/include/asm/cmpxchg.h | 20 ++++++++++++++++++++
> > 3 files changed, 38 insertions(+)
> >
> > diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig
> > index dfdb436b6078..09f7d1f06bca 100644
> > --- a/arch/csky/Kconfig
> > +++ b/arch/csky/Kconfig
> > @@ -354,6 +354,22 @@ config HAVE_EFFICIENT_UNALIGNED_STRING_OPS
> > Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could
> > deal with unaligned access by hardware.
> >
> > +choice
> > + prompt "C-SKY spinlock type"
> > + default CSKY_TICKET_SPINLOCKS
> > +
> > +config CSKY_TICKET_SPINLOCKS
> > + bool "Using ticket spinlock"
> > +
> > +config CSKY_QUEUED_SPINLOCKS
> > + bool "Using queued spinlock"
> > + depends on SMP
> > + select ARCH_USE_QUEUED_SPINLOCKS
> > + help
> > + Make sure your micro arch LL/SC has a strong forward progress guarantee.
> > + Otherwise, stay at ticket-lock/combo-lock.
>
> "combo-lock"? It is a cut-and-paste error. Right?
Yes, it's a typo. No combo-lock for csky.
>
> Cheers,
> Longman
>
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 18+ messages in thread