Linux-rt-users archive on lore.kernel.org
 help / color / Atom feed
* "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
@ 2019-10-31  3:53 Kar Hin Ong
  2019-10-31 23:05 ` Bjorn Helgaas
  0 siblings, 1 reply; 6+ messages in thread
From: Kar Hin Ong @ 2019-10-31  3:53 UTC (permalink / raw)
  To: linux-rt-users, linux-kernel, linux-x86_64, linux-pci

Hi,

I've an Intel Haswell system running Linux kernel v4.14 with preempt_rt patch. The system contain 2 IOAPICs: IOAPIC 1 is on the PCH where IOAPIC 2 is on the CPU.

I observed that whenever a PCI device is firing interrupt (INTx) to Pin 20 of IOAPIC 2 (GSI 44); the kernel will receives 2 interrupts: 
   1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
   2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED, erroneously triggered

The unexpected interrupt is unhandled eventually. When this scenario happen more than 99,000 times, kernel disables the interrupt line (Pin 19 of IOAPIC 1) and causing device that has requested it become malfunction.

I managed to also reproduced this issue on RHEL 8 and Ubuntu 19-04 (without preempt_rt patch) after added "threadirqs" to the kernel command line.

After digging further, I noticed that the said issue is happened whenever an interrupt pin on IOAPIC 2 is masked:
 - Masking Pin 20 of IOAPIC 2 triggers Pin 19 of IOAPIC 1  
 - Masking Pin 22 of IOAPIC 2 triggers Pin 18 of IOAPIC 1  

I also noticed that kernel will explicitly mask a specific interrupt pin before execute its handler, if the interrupt is configured as "oneshot" (i.e. threaded). See https://elixir.bootlin.com/linux/v4.14/source/kernel/irq/chip.c#L695  
This explained why it only happened on RTOS and Desktop Linux with "threadirqs" flag, because these configurations force the interrupt handler to be threaded.

From Intel Xeon Processor E5/E7 v3 Product Family External Design Specification (EDS), Volume One: Architecture, section 13.1 (Legacy PCI Interrupt Handling), it mention:
"If the I/OxAPIC entry is masked (via the 'mask' bit in the corresponding Redirection Table Entry), then the corresponding PCI Express interrupt(s) is forwarded to the legacy PCH"

My interpretation is: when kernel receive a "oneshot" interrupt, it mask the line before start handling it (or sending the eoi signal). 
At this moment, if the interrupt line is still asserting, then the interrupt signal will be routed to the IOAPIC in PCH, and hence causing another interrupt to be fired erroneously.  

I would like to understand if my interpretation is make sense. If yes, should the "oneshot" algorithm need to be updated to support Haswell system?

Thanks.
Kar Hin Ong


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
  2019-10-31  3:53 "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system Kar Hin Ong
@ 2019-10-31 23:05 ` Bjorn Helgaas
  2019-11-01  7:46   ` Kar Hin Ong
  2019-11-04 23:41   ` Thomas Gleixner
  0 siblings, 2 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2019-10-31 23:05 UTC (permalink / raw)
  To: Kar Hin Ong
  Cc: linux-rt-users, linux-kernel, linux-x86_64, linux-pci, Thomas Gleixner

[+cc Thomas, IRQ maintainer]

On Thu, Oct 31, 2019 at 03:53:50AM +0000, Kar Hin Ong wrote:
> Hi,
> 
> I've an Intel Haswell system running Linux kernel v4.14 with
> preempt_rt patch. The system contain 2 IOAPICs: IOAPIC 1 is on the
> PCH where IOAPIC 2 is on the CPU.
> 
> I observed that whenever a PCI device is firing interrupt (INTx) to
> Pin 20 of IOAPIC 2 (GSI 44); the kernel will receives 2 interrupts: 
>    1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
>    2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED, erroneously
>       triggered
> 
> The unexpected interrupt is unhandled eventually. When this scenario
> happen more than 99,000 times, kernel disables the interrupt line
> (Pin 19 of IOAPIC 1) and causing device that has requested it become
> malfunction.
> 
> I managed to also reproduced this issue on RHEL 8 and Ubuntu 19-04
> (without preempt_rt patch) after added "threadirqs" to the kernel
> command line.
> 
> After digging further, I noticed that the said issue is happened
> whenever an interrupt pin on IOAPIC 2 is masked:
>  - Masking Pin 20 of IOAPIC 2 triggers Pin 19 of IOAPIC 1  
>  - Masking Pin 22 of IOAPIC 2 triggers Pin 18 of IOAPIC 1  
> 
> I also noticed that kernel will explicitly mask a specific interrupt
> pin before execute its handler, if the interrupt is configured as
> "oneshot" (i.e. threaded). See
> https://elixir.bootlin.com/linux/v4.14/source/kernel/irq/chip.c#L695
> This explained why it only happened on RTOS and Desktop Linux with
> "threadirqs" flag, because these configurations force the interrupt
> handler to be threaded.
> 
> From Intel Xeon Processor E5/E7 v3 Product Family External Design
> Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
> PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is
> masked (via the 'mask' bit in the corresponding Redirection Table
> Entry), then the corresponding PCI Express interrupt(s) is forwarded
> to the legacy PCH"
> 
> My interpretation is: when kernel receive a "oneshot" interrupt, it
> mask the line before start handling it (or sending the eoi signal).
> At this moment, if the interrupt line is still asserting, then the
> interrupt signal will be routed to the IOAPIC in PCH, and hence
> causing another interrupt to be fired erroneously.  
> 
> I would like to understand if my interpretation is make sense. If
> yes, should the "oneshot" algorithm need to be updated to support
> Haswell system?

Just to make sure this hasn't already been fixed, can you reproduce
the problem on a current kernel, e.g., v5.3 or v5.4-rc5?

Bjorn

^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
  2019-10-31 23:05 ` Bjorn Helgaas
@ 2019-11-01  7:46   ` Kar Hin Ong
  2019-11-04 23:41   ` Thomas Gleixner
  1 sibling, 0 replies; 6+ messages in thread
From: Kar Hin Ong @ 2019-11-01  7:46 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-rt-users, linux-kernel, linux-x86_64, linux-pci, Thomas Gleixner

> [+cc Thomas, IRQ maintainer]
> 
> On Thu, Oct 31, 2019 at 03:53:50AM +0000, Kar Hin Ong wrote:
> > Hi,
> >
> > I've an Intel Haswell system running Linux kernel v4.14 with
> > preempt_rt patch. The system contain 2 IOAPICs: IOAPIC 1 is on the PCH
> > where IOAPIC 2 is on the CPU.
> >
> > I observed that whenever a PCI device is firing interrupt (INTx) to
> > Pin 20 of IOAPIC 2 (GSI 44); the kernel will receives 2 interrupts:
> >    1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
> >    2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED, erroneously
> >       triggered
> >
> > The unexpected interrupt is unhandled eventually. When this scenario
> > happen more than 99,000 times, kernel disables the interrupt line (Pin
> > 19 of IOAPIC 1) and causing device that has requested it become
> > malfunction.
> >
> > I managed to also reproduced this issue on RHEL 8 and Ubuntu 19-04
> > (without preempt_rt patch) after added "threadirqs" to the kernel
> > command line.
> >
> > After digging further, I noticed that the said issue is happened
> > whenever an interrupt pin on IOAPIC 2 is masked:
> >  - Masking Pin 20 of IOAPIC 2 triggers Pin 19 of IOAPIC 1
> >  - Masking Pin 22 of IOAPIC 2 triggers Pin 18 of IOAPIC 1
> >
> > I also noticed that kernel will explicitly mask a specific interrupt
> > pin before execute its handler, if the interrupt is configured as
> > "oneshot" (i.e. threaded). See
> > https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v4.14/sou
> > rce/kernel/irq/chip.c*L695__;Iw!fqWJcnlTkjM!89koUU9_SERIAj1lseZyKsfYfm
> > guRciK8coEnuqi0cnJ4tIO3OV5vG3Lbhn6-g$
> > This explained why it only happened on RTOS and Desktop Linux with
> > "threadirqs" flag, because these configurations force the interrupt
> > handler to be threaded.
> >
> > From Intel Xeon Processor E5/E7 v3 Product Family External Design
> > Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
> > PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is masked
> > (via the 'mask' bit in the corresponding Redirection Table Entry),
> > then the corresponding PCI Express interrupt(s) is forwarded to the
> > legacy PCH"
> >
> > My interpretation is: when kernel receive a "oneshot" interrupt, it
> > mask the line before start handling it (or sending the eoi signal).
> > At this moment, if the interrupt line is still asserting, then the
> > interrupt signal will be routed to the IOAPIC in PCH, and hence
> > causing another interrupt to be fired erroneously.
> >
> > I would like to understand if my interpretation is make sense. If yes,
> > should the "oneshot" algorithm need to be updated to support Haswell
> > system?
> 
> Just to make sure this hasn't already been fixed, can you reproduce the problem
> on a current kernel, e.g., v5.3 or v5.4-rc5?
The problem is reproducible on Ubuntu 19.10 (with kernel version 5.3.0-19-generic) as well.

> 
> Bjorn

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
  2019-10-31 23:05 ` Bjorn Helgaas
  2019-11-01  7:46   ` Kar Hin Ong
@ 2019-11-04 23:41   ` Thomas Gleixner
  2019-11-07  9:38     ` Kar Hin Ong
  1 sibling, 1 reply; 6+ messages in thread
From: Thomas Gleixner @ 2019-11-04 23:41 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: Kar Hin Ong, linux-rt-users, LKML, linux-x86_64, linux-pci,
	H. Peter Anvin, Dave Hansen

On Thu, 31 Oct 2019, Bjorn Helgaas wrote:
> On Thu, Oct 31, 2019 at 03:53:50AM +0000, Kar Hin Ong wrote:
> > I've an Intel Haswell system running Linux kernel v4.14 with
> > preempt_rt patch. The system contain 2 IOAPICs: IOAPIC 1 is on the
> > PCH where IOAPIC 2 is on the CPU.
> > 
> > I observed that whenever a PCI device is firing interrupt (INTx) to
> > Pin 20 of IOAPIC 2 (GSI 44); the kernel will receives 2 interrupts: 
> >    1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
> >    2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED, erroneously
> >       triggered
> >
> > The unexpected interrupt is unhandled eventually. When this scenario
> > happen more than 99,000 times, kernel disables the interrupt line
> > (Pin 19 of IOAPIC 1) and causing device that has requested it become
> > malfunction.
> > 
> > I managed to also reproduced this issue on RHEL 8 and Ubuntu 19-04
> > (without preempt_rt patch) after added "threadirqs" to the kernel
> > command line.
> > 
> > After digging further, I noticed that the said issue is happened
> > whenever an interrupt pin on IOAPIC 2 is masked:
> >  - Masking Pin 20 of IOAPIC 2 triggers Pin 19 of IOAPIC 1  
> >  - Masking Pin 22 of IOAPIC 2 triggers Pin 18 of IOAPIC 1

This is pretty much the same problem which we had analyzed and worked
around years ago.

> > From Intel Xeon Processor E5/E7 v3 Product Family External Design
> > Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
> > PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is
> > masked (via the 'mask' bit in the corresponding Redirection Table
> > Entry), then the corresponding PCI Express interrupt(s) is forwarded
> > to the legacy PCH"

Oh well. Really useful behaviour - NOT!

> > I would like to understand if my interpretation is make sense. If
> > yes, should the "oneshot" algorithm need to be updated to support
> > Haswell system?

No. You cannot change the oneshot algorithm.

The workarounds for this are enabled by PCI quirls and either
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y or 'ioapicreroute' on the command
line.

It might be wortha try to add the PCI ID of that box to the quirk list,
i.e. the PCI ID matches in drivers/pci/quirks.c which belong to the
function: quirk_reroute_to_boot_interrupts_intel().

Thanks,

	tglx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
  2019-11-04 23:41   ` Thomas Gleixner
@ 2019-11-07  9:38     ` Kar Hin Ong
  2019-11-21 11:22       ` Kar Hin Ong
  0 siblings, 1 reply; 6+ messages in thread
From: Kar Hin Ong @ 2019-11-07  9:38 UTC (permalink / raw)
  To: Thomas Gleixner, Bjorn Helgaas
  Cc: linux-rt-users, LKML, linux-x86_64, linux-pci, H. Peter Anvin,
	Dave Hansen, Julia Cartwright, Keng Soon Cheah

> On Thu, 31 Oct 2019, Bjorn Helgaas wrote:
> > On Thu, Oct 31, 2019 at 03:53:50AM +0000, Kar Hin Ong wrote:
> > > I've an Intel Haswell system running Linux kernel v4.14 with
> > > preempt_rt patch. The system contain 2 IOAPICs: IOAPIC 1 is on the
> > > PCH where IOAPIC 2 is on the CPU.
> > >
> > > I observed that whenever a PCI device is firing interrupt (INTx) to
> > > Pin 20 of IOAPIC 2 (GSI 44); the kernel will receives 2 interrupts:
> > >    1. Interrupt from Pin 20 of IOAPIC 2  -> Expected
> > >    2. Interrupt from Pin 19 of IOAPIC 1  -> UNEXPECTED, erroneously
> > >       triggered
> > >
> > > The unexpected interrupt is unhandled eventually. When this scenario
> > > happen more than 99,000 times, kernel disables the interrupt line
> > > (Pin 19 of IOAPIC 1) and causing device that has requested it become
> > > malfunction.
> > >
> > > I managed to also reproduced this issue on RHEL 8 and Ubuntu 19-04
> > > (without preempt_rt patch) after added "threadirqs" to the kernel
> > > command line.
> > >
> > > After digging further, I noticed that the said issue is happened
> > > whenever an interrupt pin on IOAPIC 2 is masked:
> > >  - Masking Pin 20 of IOAPIC 2 triggers Pin 19 of IOAPIC 1
> > >  - Masking Pin 22 of IOAPIC 2 triggers Pin 18 of IOAPIC 1
> 
> This is pretty much the same problem which we had analyzed and worked around
> years ago.
> 
> > > From Intel Xeon Processor E5/E7 v3 Product Family External Design
> > > Specification (EDS), Volume One: Architecture, section 13.1 (Legacy
> > > PCI Interrupt Handling), it mention: "If the I/OxAPIC entry is
> > > masked (via the 'mask' bit in the corresponding Redirection Table
> > > Entry), then the corresponding PCI Express interrupt(s) is forwarded
> > > to the legacy PCH"
> 
> Oh well. Really useful behaviour - NOT!
> 
> > > I would like to understand if my interpretation is make sense. If
> > > yes, should the "oneshot" algorithm need to be updated to support
> > > Haswell system?
> 
> No. You cannot change the oneshot algorithm.
> 
> The workarounds for this are enabled by PCI quirls and either
> CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y or 'ioapicreroute' on the
> command line.
> 
> It might be wortha try to add the PCI ID of that box to the quirk list, i.e. the PCI ID
> matches in drivers/pci/quirks.c which belong to the
> function: quirk_reroute_to_boot_interrupts_intel().

Do you mean adding the PCI ID of the device that actually fires interrupt? It can be any PCI card though (example: external ETH controller, data acquisition module, etc).
Or you mean to add the ID of all PCIe root ports that routed to IOAPIC 2?

Based on Haswell specification, seems like every entry on IOAPIC 2 will experience this problem.
If to reroute every entry on IOAPIC 2 to IOAPIC 1, probably we should just disable IOAPIC 2 instead?


^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
  2019-11-07  9:38     ` Kar Hin Ong
@ 2019-11-21 11:22       ` Kar Hin Ong
  0 siblings, 0 replies; 6+ messages in thread
From: Kar Hin Ong @ 2019-11-21 11:22 UTC (permalink / raw)
  To: Thomas Gleixner, Bjorn Helgaas
  Cc: linux-rt-users, LKML, linux-x86_64, linux-pci, H. Peter Anvin,
	Dave Hansen, Julia Cartwright, Keng Soon Cheah

> > The workarounds for this are enabled by PCI quirls and either
> > CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y or 'ioapicreroute' on
> the
> > command line.
> >
> > It might be wortha try to add the PCI ID of that box to the quirk
> > list, i.e. the PCI ID matches in drivers/pci/quirks.c which belong to
> > the
> > function: quirk_reroute_to_boot_interrupts_intel().
> 
> Do you mean adding the PCI ID of the device that actually fires interrupt? It
> can be any PCI card though (example: external ETH controller, data
> acquisition module, etc).
> Or you mean to add the ID of all PCIe root ports that routed to IOAPIC 2?
> 
> Based on Haswell specification, seems like every entry on IOAPIC 2 will
> experience this problem.
> If to reroute every entry on IOAPIC 2 to IOAPIC 1, probably we should just
> disable IOAPIC 2 instead?

Hi Thomas, Bjorn, 
Any thoughts on this?

Thanks.
Kar Hin Ong 


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, back to index

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-31  3:53 "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system Kar Hin Ong
2019-10-31 23:05 ` Bjorn Helgaas
2019-11-01  7:46   ` Kar Hin Ong
2019-11-04 23:41   ` Thomas Gleixner
2019-11-07  9:38     ` Kar Hin Ong
2019-11-21 11:22       ` Kar Hin Ong

Linux-rt-users archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-rt-users/0 linux-rt-users/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-rt-users linux-rt-users/ https://lore.kernel.org/linux-rt-users \
		linux-rt-users@vger.kernel.org
	public-inbox-index linux-rt-users

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-rt-users


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git