From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org,
eranian@google.com, namhyung@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, yao.jin@linux.intel.com
Subject: Re: [PATCH 03/12] perf/x86/intel: Add perf core PMU support for Sapphire Rapids
Date: Tue, 26 Jan 2021 11:21:21 -0500 [thread overview]
Message-ID: <0272153e-f2a5-67df-9402-16d3cc118713@linux.intel.com> (raw)
In-Reply-To: <YBA3V59bsOA9j/wj@hirez.programming.kicks-ass.net>
On 1/26/2021 10:37 AM, Peter Zijlstra wrote:
> On Tue, Jan 19, 2021 at 12:38:22PM -0800, kan.liang@linux.intel.com wrote:
>> @@ -1577,9 +1668,20 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
>> }
>>
>> if (format_size & PEBS_DATACFG_MEMINFO) {
>> + if (sample_type & PERF_SAMPLE_WEIGHT) {
>> + u64 weight = meminfo->latency;
>> +
>> + if (x86_pmu.flags & PMU_FL_INSTR_LATENCY)
>> + weight >>= PEBS_CACHE_LATENCY_OFFSET;
>> + data->weight = weight & PEBS_LATENCY_MASK ?:
>> intel_get_tsx_weight(meminfo->tsx_tuning);
>> + }
>> +
>> + if (sample_type & PERF_SAMPLE_WEIGHT_EXT) {
>> + data->weight_ext.val = 0;
>> + if (x86_pmu.flags & PMU_FL_INSTR_LATENCY)
>> + data->weight_ext.instr_latency = meminfo->latency & PEBS_LATENCY_MASK;
>> + }
>>
>> if (sample_type & PERF_SAMPLE_DATA_SRC)
>> data->data_src.val = get_data_src(event, meminfo->aux);
>
> Talk to me about that SAMPLE_WEIGHT stuff.... I'm not liking it.
>
> Sure you want multiple dimensions, but urgh.
>
> Also, afaict, as proposed you're wasting 80/128 bits. That is, all data
> you want to export fits in a single u64 and yet you're using two, which
> is mighty daft.
>
> Sure, pebs::lat / pebs_meminfo::latency is defined as a u64, but you
> can't tell me that that is ever actually more than 4G cycles. Even the
> TSX block latency is u32.
>
> So how about defining SAMPLE_WEIGHT_STRUCT which uses the exact same
> data as SAMPLE_WEIGHT but unions it with a struct. I'm not sure if we
> want:
>
> union sample_weight {
> u64 weight;
>
> struct {
> u32 low_dword;
> u32 high_dword;
> };
>
> /* or */
>
> struct {
> u32 low_dword;
> u16 high_word;
> u16 higher_word;
> };
> };
>
> Then have the core code enforce SAMPLE_WEIGHT ^ SAMPLE_WEIGHT_STRUCT and
> make the existing code never set the high dword.
So the kernel will only accept either SAMPLE_WEIGHT type or
SAMPLE_WEIGHT_STRUCT type. It should error out if both types are set, right?
I will check if u32 is enough for meminfo::latency on the previous
platforms.
Thanks,
Kan
next prev parent reply other threads:[~2021-01-26 16:24 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 20:38 [PATCH 00/12] perf core PMU support for Sapphire Rapids kan.liang
2021-01-19 20:38 ` [PATCH 01/12] perf/core: Add PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-26 14:42 ` Peter Zijlstra
2021-01-26 15:33 ` Liang, Kan
2021-01-26 15:55 ` Peter Zijlstra
2021-01-19 20:38 ` [PATCH 02/12] perf/x86/intel: Factor out intel_update_topdown_event() kan.liang
2021-01-19 20:38 ` [PATCH 03/12] perf/x86/intel: Add perf core PMU support for Sapphire Rapids kan.liang
2021-01-26 14:43 ` Peter Zijlstra
2021-01-26 15:34 ` Liang, Kan
2021-01-26 14:44 ` Peter Zijlstra
2021-01-26 15:44 ` Liang, Kan
2021-01-27 19:16 ` Peter Zijlstra
2021-01-26 14:49 ` Peter Zijlstra
2021-01-26 15:37 ` Peter Zijlstra
2021-01-26 16:21 ` Liang, Kan [this message]
2021-01-19 20:38 ` [PATCH 04/12] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2021-01-26 15:44 ` Peter Zijlstra
2021-01-26 15:53 ` Peter Zijlstra
2021-01-19 20:38 ` [PATCH 05/12] tools headers uapi: Update tools's copy of linux/perf_event.h kan.liang
2021-01-19 20:38 ` [PATCH 06/12] perf tools: Support data block and addr block kan.liang
2021-01-19 20:38 ` [PATCH 07/12] perf c2c: " kan.liang
2021-01-19 20:38 ` [PATCH 08/12] perf tools: Support PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-19 20:38 ` [PATCH 09/12] perf report: Support instruction latency kan.liang
2021-01-19 20:38 ` [PATCH 10/12] perf test: Support PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-19 20:38 ` [PATCH 11/12] perf stat: Support L2 Topdown events kan.liang
2021-01-19 20:38 ` [PATCH 12/12] perf, tools: Update topdown documentation for Sapphire Rapids kan.liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0272153e-f2a5-67df-9402-16d3cc118713@linux.intel.com \
--to=kan.liang@linux.intel.com \
--cc=acme@kernel.org \
--cc=ak@linux.intel.com \
--cc=eranian@google.com \
--cc=jolsa@redhat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=yao.jin@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).