From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org,
eranian@google.com, namhyung@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, yao.jin@linux.intel.com
Subject: Re: [PATCH 04/12] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters
Date: Tue, 26 Jan 2021 16:44:23 +0100 [thread overview]
Message-ID: <YBA417xr4BxLfYvL@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1611088711-17177-5-git-send-email-kan.liang@linux.intel.com>
On Tue, Jan 19, 2021 at 12:38:23PM -0800, kan.liang@linux.intel.com wrote:
> @@ -5228,7 +5231,7 @@ __init int intel_pmu_init(void)
> * Check whether the Architectural PerfMon supports
> * Branch Misses Retired hw_event or not.
> */
> - cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
> + cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
> if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
> return -ENODEV;
>
> @@ -5255,8 +5258,16 @@ __init int intel_pmu_init(void)
> if (version > 1) {
> int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
>
> - x86_pmu.num_counters_fixed =
> - max((int)edx.split.num_counters_fixed, assume);
> + if (!fixed_mask) {
> + x86_pmu.num_counters_fixed =
> + max((int)edx.split.num_counters_fixed, assume);
> + } else {
> + /*
> + * The fixed-purpose counters are enumerated in the ECX
> + * since V5 perfmon.
> + */
But that's not what the code implements.
> + x86_pmu.num_counters_fixed = fls(fixed_mask);
> + }
> }
What you were looking for is something like this:
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index fe940082d49a..9ad42cb59606 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4817,6 +4817,13 @@ __init int intel_pmu_init(void)
x86_pmu.num_counters_fixed =
max((int)edx.split.num_counters_fixed, assume);
+
+ if (version >= 5) {
+ /*
+ * V5 and later provide a fixed counter mask.
+ */
+ x86_pmu.num_counters_fixed = fls(fixed_mask);
+ }
}
if (boot_cpu_has(X86_FEATURE_PDCM)) {
next prev parent reply other threads:[~2021-01-26 15:47 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 20:38 [PATCH 00/12] perf core PMU support for Sapphire Rapids kan.liang
2021-01-19 20:38 ` [PATCH 01/12] perf/core: Add PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-26 14:42 ` Peter Zijlstra
2021-01-26 15:33 ` Liang, Kan
2021-01-26 15:55 ` Peter Zijlstra
2021-01-19 20:38 ` [PATCH 02/12] perf/x86/intel: Factor out intel_update_topdown_event() kan.liang
2021-01-19 20:38 ` [PATCH 03/12] perf/x86/intel: Add perf core PMU support for Sapphire Rapids kan.liang
2021-01-26 14:43 ` Peter Zijlstra
2021-01-26 15:34 ` Liang, Kan
2021-01-26 14:44 ` Peter Zijlstra
2021-01-26 15:44 ` Liang, Kan
2021-01-27 19:16 ` Peter Zijlstra
2021-01-26 14:49 ` Peter Zijlstra
2021-01-26 15:37 ` Peter Zijlstra
2021-01-26 16:21 ` Liang, Kan
2021-01-19 20:38 ` [PATCH 04/12] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2021-01-26 15:44 ` Peter Zijlstra [this message]
2021-01-26 15:53 ` Peter Zijlstra
2021-01-19 20:38 ` [PATCH 05/12] tools headers uapi: Update tools's copy of linux/perf_event.h kan.liang
2021-01-19 20:38 ` [PATCH 06/12] perf tools: Support data block and addr block kan.liang
2021-01-19 20:38 ` [PATCH 07/12] perf c2c: " kan.liang
2021-01-19 20:38 ` [PATCH 08/12] perf tools: Support PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-19 20:38 ` [PATCH 09/12] perf report: Support instruction latency kan.liang
2021-01-19 20:38 ` [PATCH 10/12] perf test: Support PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-19 20:38 ` [PATCH 11/12] perf stat: Support L2 Topdown events kan.liang
2021-01-19 20:38 ` [PATCH 12/12] perf, tools: Update topdown documentation for Sapphire Rapids kan.liang
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