From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org,
eranian@google.com, namhyung@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, yao.jin@linux.intel.com
Subject: Re: [PATCH 03/12] perf/x86/intel: Add perf core PMU support for Sapphire Rapids
Date: Tue, 26 Jan 2021 15:49:44 +0100 [thread overview]
Message-ID: <YBAsCE1dz7Xq/kFg@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1611088711-17177-4-git-send-email-kan.liang@linux.intel.com>
On Tue, Jan 19, 2021 at 12:38:22PM -0800, kan.liang@linux.intel.com wrote:
> Add pebs_no_block to
> explicitly indicate the previous platforms which don't support the new
> block fields. Accessing the new block fields are ignored on those
> platforms.
> @@ -5475,6 +5749,7 @@ __init int intel_pmu_init(void)
> x86_pmu.extra_regs = intel_icl_extra_regs;
> x86_pmu.pebs_aliases = NULL;
> x86_pmu.pebs_prec_dist = true;
> + x86_pmu.pebs_no_block = true;
> x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
>
> @@ -198,6 +206,63 @@ static u64 load_latency_data(u64 status)
> if (dse.ld_locked)
> val |= P(LOCK, LOCKED);
>
> + /*
> + * Ice Lake and earlier models do not support block infos.
> + */
> + if (x86_pmu.pebs_no_block) {
> + val |= P(BLK, NA);
> + return val;
> + }
> @@ -2026,8 +2128,10 @@ void __init intel_ds_init(void)
> x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
> x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
> x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
> - if (x86_pmu.version <= 4)
> + if (x86_pmu.version <= 4) {
> x86_pmu.pebs_no_isolation = 1;
> + x86_pmu.pebs_no_block = 1;
> + }
>
> if (x86_pmu.pebs) {
> char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
> @@ -724,7 +729,8 @@ struct x86_pmu {
> pebs_broken :1,
> pebs_prec_dist :1,
> pebs_no_tlb :1,
> - pebs_no_isolation :1;
> + pebs_no_isolation :1,
> + pebs_no_block :1;
> int pebs_record_size;
> int pebs_buffer_size;
> int max_pebs_events;
I suppose the existing pebs_no_isolation set the bad precedent, but this
is ofcourse a bit backwards. Since we're 0 initialized, new features
should be 1, and not the other way around.
next prev parent reply other threads:[~2021-01-26 14:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 20:38 [PATCH 00/12] perf core PMU support for Sapphire Rapids kan.liang
2021-01-19 20:38 ` [PATCH 01/12] perf/core: Add PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-26 14:42 ` Peter Zijlstra
2021-01-26 15:33 ` Liang, Kan
2021-01-26 15:55 ` Peter Zijlstra
2021-01-19 20:38 ` [PATCH 02/12] perf/x86/intel: Factor out intel_update_topdown_event() kan.liang
2021-01-19 20:38 ` [PATCH 03/12] perf/x86/intel: Add perf core PMU support for Sapphire Rapids kan.liang
2021-01-26 14:43 ` Peter Zijlstra
2021-01-26 15:34 ` Liang, Kan
2021-01-26 14:44 ` Peter Zijlstra
2021-01-26 15:44 ` Liang, Kan
2021-01-27 19:16 ` Peter Zijlstra
2021-01-26 14:49 ` Peter Zijlstra [this message]
2021-01-26 15:37 ` Peter Zijlstra
2021-01-26 16:21 ` Liang, Kan
2021-01-19 20:38 ` [PATCH 04/12] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2021-01-26 15:44 ` Peter Zijlstra
2021-01-26 15:53 ` Peter Zijlstra
2021-01-19 20:38 ` [PATCH 05/12] tools headers uapi: Update tools's copy of linux/perf_event.h kan.liang
2021-01-19 20:38 ` [PATCH 06/12] perf tools: Support data block and addr block kan.liang
2021-01-19 20:38 ` [PATCH 07/12] perf c2c: " kan.liang
2021-01-19 20:38 ` [PATCH 08/12] perf tools: Support PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-19 20:38 ` [PATCH 09/12] perf report: Support instruction latency kan.liang
2021-01-19 20:38 ` [PATCH 10/12] perf test: Support PERF_SAMPLE_WEIGHT_EXT kan.liang
2021-01-19 20:38 ` [PATCH 11/12] perf stat: Support L2 Topdown events kan.liang
2021-01-19 20:38 ` [PATCH 12/12] perf, tools: Update topdown documentation for Sapphire Rapids kan.liang
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