* [PATCH 1/3] x86, intel: Output microcode revision v3
@ 2011-07-01 19:21 Andi Kleen
2011-07-01 19:21 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-07-01 19:21 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
0 siblings, 2 replies; 15+ messages in thread
From: Andi Kleen @ 2011-07-01 19:21 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
v3: Rename cpu_update to microcode. Misc changes from feedback.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 4 +++-
arch/x86/kernel/cpu/intel.c | 13 +++++++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++--
arch/x86/kernel/cpu/proc.c | 3 ++-
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 2193715..9ded5bb 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ u32 microcode;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1edf5ba..ebedd27 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -364,6 +364,19 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
early_init_intel(c);
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* The CPUID 1 fills in the MSR as documented in the SDM */
+ /*
+ * Wrong comment from microcode_intel.c:
+ * see notes above for revision 1.07. Apparent chip bug
+ */
+ cpuid_eax(1);
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+ }
+
intel_workarounds(c);
/*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index ff1ae9b..82eb8be 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -220,8 +220,13 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ /*
+ * Note this output is parsed by external tools and old fields
+ * should not be changed.
+ */
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).microcode);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..48ac015 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->microcode)
+ seq_printf(m, "microcode\t: %u\n", c->microcode);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
@@ -132,7 +134,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, " [%d]", i);
}
}
-
seq_printf(m, "\n\n");
return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..3ca42d0 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->microcode;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->microcode = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-07-01 19:21 [PATCH 1/3] x86, intel: Output microcode revision v3 Andi Kleen
@ 2011-07-01 19:21 ` Andi Kleen
2011-07-01 19:21 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
1 sibling, 0 replies; 15+ messages in thread
From: Andi Kleen @ 2011-07-01 19:21 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ebedd27..6f75c45 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->microcode < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2
2011-07-01 19:21 [PATCH 1/3] x86, intel: Output microcode revision v3 Andi Kleen
2011-07-01 19:21 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
@ 2011-07-01 19:21 ` Andi Kleen
1 sibling, 0 replies; 15+ messages in thread
From: Andi Kleen @ 2011-07-01 19:21 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen, jbeulich, fenghua.yu, khali
From: Andi Kleen <ak@linux.intel.com>
Now that the ucode revision is available in cpu_data remove
the existing code in coretemp.c to query it manually. Read the ucode
revision from cpu_data instead
v2: Fix misplaced variable init. Remove unused variables.
Cc: jbeulich@novell.com
Cc: fenghua.yu@intel.com
Cc: khali@linux-fr.org
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
drivers/hwmon/coretemp.c | 31 +++++--------------------------
1 files changed, 5 insertions(+), 26 deletions(-)
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 0070d54..2d038e3 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -307,15 +307,6 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
return adjust_tjmax(c, id, dev);
}
-static void __devinit get_ucode_rev_on_cpu(void *edx)
-{
- u32 eax;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx);
-}
-
static int get_pkg_tjmax(unsigned int cpu, struct device *dev)
{
int err;
@@ -410,29 +401,17 @@ static void update_ttarget(__u8 cpu_model, struct temp_data *tdata,
static int __devinit chk_ucode_version(struct platform_device *pdev)
{
struct cpuinfo_x86 *c = &cpu_data(pdev->id);
- int err;
- u32 edx;
/*
* Check if we have problem with errata AE18 of Core processors:
* Readings might stop update when processor visited too deep sleep,
* fixed for stepping D0 (6EC).
*/
- if (c->x86_model == 0xe && c->x86_mask < 0xc) {
- /* check for microcode update */
- err = smp_call_function_single(pdev->id, get_ucode_rev_on_cpu,
- &edx, 1);
- if (err) {
- dev_err(&pdev->dev,
- "Cannot determine microcode revision of "
- "CPU#%u (%d)!\n", pdev->id, err);
- return -ENODEV;
- } else if (edx < 0x39) {
- dev_err(&pdev->dev,
- "Errata AE18 not fixed, update BIOS or "
- "microcode of the CPU!\n");
- return -ENODEV;
- }
+ if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
+ dev_err(&pdev->dev,
+ "Errata AE18 not fixed, update BIOS or "
+ "microcode of the CPU!\n");
+ return -ENODEV;
}
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision v7
@ 2011-10-13 22:55 Andi Kleen
2011-10-13 22:55 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-10-13 22:55 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
v3: Rename cpu_update to microcode. Misc changes from feedback.
v4: minor updates. rebased.
v5: move MSR read to early_intel_init()
v6: Use sync_core() instead of CPUID 1. Drop a white space change.
v7: Add Acked-bys.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/include/asm/processor.h | 4 +++-
arch/x86/kernel/cpu/intel.c | 9 +++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++--
arch/x86/kernel/cpu/proc.c | 2 ++
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 0d1171c..b650435 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ u32 microcode;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ed6086e..26627a3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* Required by the SDM */
+ sync_core();
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+ }
+
/*
* Atom erratum AAE44/AAF40/AAG38/AAH41:
*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 08363b0..8af6fa4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ /*
+ * Note this output is parsed by external tools and old fields
+ * should not be changed.
+ */
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).microcode);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..6254fda 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->microcode)
+ seq_printf(m, "microcode\t: %u\n", c->microcode);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..3ca42d0 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->microcode;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->microcode = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-10-13 22:55 [PATCH 1/3] x86, intel: Output microcode revision v7 Andi Kleen
@ 2011-10-13 22:55 ` Andi Kleen
0 siblings, 0 replies; 15+ messages in thread
From: Andi Kleen @ 2011-10-13 22:55 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 26627a3..5231312 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -64,17 +64,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->microcode < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision v6
@ 2011-10-13 0:46 Andi Kleen
2011-10-13 0:46 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-10-13 0:46 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
v3: Rename cpu_update to microcode. Misc changes from feedback.
v4: minor updates. rebased.
v5: move MSR read to early_intel_init()
v6: Use sync_core() instead of CPUID 1. Drop a white space change.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 4 +++-
arch/x86/kernel/cpu/intel.c | 9 +++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++--
arch/x86/kernel/cpu/proc.c | 2 ++
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 0d1171c..b650435 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ u32 microcode;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ed6086e..26627a3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* Required by the SDM */
+ sync_core();
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+ }
+
/*
* Atom erratum AAE44/AAF40/AAG38/AAH41:
*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 08363b0..8af6fa4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ /*
+ * Note this output is parsed by external tools and old fields
+ * should not be changed.
+ */
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).microcode);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..6254fda 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->microcode)
+ seq_printf(m, "microcode\t: %u\n", c->microcode);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..3ca42d0 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->microcode;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->microcode = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-10-13 0:46 [PATCH 1/3] x86, intel: Output microcode revision v6 Andi Kleen
@ 2011-10-13 0:46 ` Andi Kleen
2011-10-13 5:38 ` H. Peter Anvin
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-10-13 0:46 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 26627a3..5231312 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -64,17 +64,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->microcode < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision v5
@ 2011-09-28 23:19 Andi Kleen
2011-09-28 23:19 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-09-28 23:19 UTC (permalink / raw)
To: linux-kernel; +Cc: hpa, mingo, tglx, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
v3: Rename cpu_update to microcode. Misc changes from feedback.
v4: minor updates. rebased.
v5: move MSR read to early_intel_init()
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 4 +++-
arch/x86/kernel/cpu/intel.c | 9 +++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++--
arch/x86/kernel/cpu/proc.c | 3 ++-
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 0d1171c..b650435 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ u32 microcode;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ed6086e..6b178c8 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* The CPUID 1 fills in the MSR as documented in the SDM */
+ cpuid_eax(1);
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+ }
+
/*
* Atom erratum AAE44/AAF40/AAG38/AAH41:
*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 08363b0..b84b3cf 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ /*
+ * Note this output is parsed by external tools and old fields
+ * should not be changed.
+ */
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).microcode);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..48ac015 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->microcode)
+ seq_printf(m, "microcode\t: %u\n", c->microcode);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
@@ -132,7 +134,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, " [%d]", i);
}
}
-
seq_printf(m, "\n\n");
return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..3ca42d0 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->microcode;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->microcode = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-09-28 23:19 [PATCH 1/3] x86, intel: Output microcode revision v5 Andi Kleen
@ 2011-09-28 23:19 ` Andi Kleen
0 siblings, 0 replies; 15+ messages in thread
From: Andi Kleen @ 2011-09-28 23:19 UTC (permalink / raw)
To: linux-kernel; +Cc: hpa, mingo, tglx, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 6b178c8..aef3bfc 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -64,17 +64,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->microcode < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision v4
@ 2011-08-29 23:47 Andi Kleen
2011-08-29 23:47 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-08-29 23:47 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
0 siblings, 2 replies; 15+ messages in thread
From: Andi Kleen @ 2011-08-29 23:47 UTC (permalink / raw)
To: linux-kernel; +Cc: x86, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
v3: Rename cpu_update to microcode. Misc changes from feedback.
v4: minor updates. rebased.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 4 +++-
arch/x86/kernel/cpu/intel.c | 9 +++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++--
arch/x86/kernel/cpu/proc.c | 3 ++-
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 0d1171c..b650435 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ u32 microcode;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ed6086e..5c9670d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -364,6 +364,15 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
early_init_intel(c);
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* The CPUID 1 fills in the MSR as documented in the SDM */
+ cpuid_eax(1);
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+ }
+
intel_workarounds(c);
/*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 08363b0..b84b3cf 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ /*
+ * Note this output is parsed by external tools and old fields
+ * should not be changed.
+ */
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).microcode);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..48ac015 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->microcode)
+ seq_printf(m, "microcode\t: %u\n", c->microcode);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
@@ -132,7 +134,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, " [%d]", i);
}
}
-
seq_printf(m, "\n\n");
return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..3ca42d0 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->microcode;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->microcode = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-08-29 23:47 [PATCH 1/3] x86, intel: Output microcode revision v4 Andi Kleen
@ 2011-08-29 23:47 ` Andi Kleen
2011-08-29 23:47 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
1 sibling, 0 replies; 15+ messages in thread
From: Andi Kleen @ 2011-08-29 23:47 UTC (permalink / raw)
To: linux-kernel; +Cc: x86, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5c9670d..3f57854 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->microcode < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2
2011-08-29 23:47 [PATCH 1/3] x86, intel: Output microcode revision v4 Andi Kleen
2011-08-29 23:47 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
@ 2011-08-29 23:47 ` Andi Kleen
2011-08-30 1:08 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Yu, Fenghua
1 sibling, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-08-29 23:47 UTC (permalink / raw)
To: linux-kernel; +Cc: x86, Andi Kleen, jbeulich, fenghua.yu, khali
From: Andi Kleen <ak@linux.intel.com>
Now that the ucode revision is available in cpu_data remove
the existing code in coretemp.c to query it manually. Read the ucode
revision from cpu_data instead
v2: Fix misplaced variable init. Remove unused variables.
Cc: jbeulich@novell.com
Cc: fenghua.yu@intel.com
Cc: khali@linux-fr.org
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
drivers/hwmon/coretemp.c | 31 +++++--------------------------
1 files changed, 5 insertions(+), 26 deletions(-)
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 59d83e8..c407794 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -405,15 +405,6 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
return adjust_tjmax(c, id, dev);
}
-static void __devinit get_ucode_rev_on_cpu(void *edx)
-{
- u32 eax;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx);
-}
-
static int get_pkg_tjmax(unsigned int cpu, struct device *dev)
{
int err;
@@ -484,29 +475,17 @@ exit_free:
static int __devinit chk_ucode_version(struct platform_device *pdev)
{
struct cpuinfo_x86 *c = &cpu_data(pdev->id);
- int err;
- u32 edx;
/*
* Check if we have problem with errata AE18 of Core processors:
* Readings might stop update when processor visited too deep sleep,
* fixed for stepping D0 (6EC).
*/
- if (c->x86_model == 0xe && c->x86_mask < 0xc) {
- /* check for microcode update */
- err = smp_call_function_single(pdev->id, get_ucode_rev_on_cpu,
- &edx, 1);
- if (err) {
- dev_err(&pdev->dev,
- "Cannot determine microcode revision of "
- "CPU#%u (%d)!\n", pdev->id, err);
- return -ENODEV;
- } else if (edx < 0x39) {
- dev_err(&pdev->dev,
- "Errata AE18 not fixed, update BIOS or "
- "microcode of the CPU!\n");
- return -ENODEV;
- }
+ if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
+ dev_err(&pdev->dev,
+ "Errata AE18 not fixed, update BIOS or "
+ "microcode of the CPU!\n");
+ return -ENODEV;
}
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* RE: [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-08-29 23:47 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
@ 2011-08-30 1:08 ` Yu, Fenghua
0 siblings, 0 replies; 15+ messages in thread
From: Yu, Fenghua @ 2011-08-30 1:08 UTC (permalink / raw)
To: Andi Kleen, linux-kernel; +Cc: x86, Andi Kleen, jbeulich, khali, Yu, Fenghua
>--- a/arch/x86/kernel/cpu/intel.c
>+++ b/arch/x86/kernel/cpu/intel.c
>@@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
> * need the microcode to have already been loaded... so if it is
> * not, recommend a BIOS update and disable large pages.
> */
>- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
>- u32 ucode, junk;
>-
>- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
>- sync_core();
>- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
>-
>- if (ucode < 0x20e) {
>- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
>- clear_cpu_cap(c, X86_FEATURE_PSE);
>- }
>+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
>+ c->microcode < 0x20e) {
>+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
>+ clear_cpu_cap(c, X86_FEATURE_PSE);
> }
c->microcode is used here BEFORE it's initialized in init_intel() in your patch set [1/3].
Thanks.
-Fenghua
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision v3
@ 2011-07-06 23:57 Andi Kleen
2011-07-06 23:57 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-07-06 23:57 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, akpm, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "microcode" field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
v3: Rename cpu_update to microcode. Misc changes from feedback.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 4 +++-
arch/x86/kernel/cpu/intel.c | 13 +++++++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 9 +++++++--
arch/x86/kernel/cpu/proc.c | 3 ++-
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 30 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 2193715..9ded5bb 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ u32 microcode;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1edf5ba..ebedd27 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -364,6 +364,19 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
early_init_intel(c);
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* The CPUID 1 fills in the MSR as documented in the SDM */
+ /*
+ * Wrong comment from microcode_intel.c:
+ * see notes above for revision 1.07. Apparent chip bug
+ */
+ cpuid_eax(1);
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+ }
+
intel_workarounds(c);
/*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index ff1ae9b..82eb8be 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -220,8 +220,13 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ /*
+ * Note this output is parsed by external tools and old fields
+ * should not be changed.
+ */
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).microcode);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..48ac015 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->microcode)
+ seq_printf(m, "microcode\t: %u\n", c->microcode);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
@@ -132,7 +134,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, " [%d]", i);
}
}
-
seq_printf(m, "\n\n");
return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..3ca42d0 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->microcode;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->microcode = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-07-06 23:57 [PATCH 1/3] x86, intel: Output microcode revision v3 Andi Kleen
@ 2011-07-06 23:57 ` Andi Kleen
2011-07-11 8:19 ` Jean Delvare
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-07-06 23:57 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, akpm, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ebedd27..6f75c45 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->microcode < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-07-06 23:57 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
@ 2011-07-11 8:19 ` Jean Delvare
0 siblings, 0 replies; 15+ messages in thread
From: Jean Delvare @ 2011-07-11 8:19 UTC (permalink / raw)
To: Andi Kleen; +Cc: x86, linux-kernel, akpm, Andi Kleen
On Wed, 6 Jul 2011 16:57:02 -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> Now that the cpu update level is available the Atom PSE errata
> check can use it directly without reading the MSR again.
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
> arch/x86/kernel/cpu/intel.c | 15 ++++-----------
> 1 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index ebedd27..6f75c45 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
> * need the microcode to have already been loaded... so if it is
> * not, recommend a BIOS update and disable large pages.
> */
> - if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
> - u32 ucode, junk;
> -
> - wrmsr(MSR_IA32_UCODE_REV, 0, 0);
> - sync_core();
> - rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
> -
> - if (ucode < 0x20e) {
> - printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
> - clear_cpu_cap(c, X86_FEATURE_PSE);
> - }
> + if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
> + c->microcode < 0x20e) {
> + printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
> + clear_cpu_cap(c, X86_FEATURE_PSE);
> }
>
> #ifdef CONFIG_X86_64
Looks good.
Acked-by: Jean Delvare <khali@linux-fr.org>
--
Jean Delvare
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision v2
@ 2011-05-25 19:32 Andi Kleen
2011-05-25 19:32 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-05-25 19:32 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "cpu update" field to /proc/cpuinfo,
which I added at the end to minimize impact on parsers.
The update level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
v2: Lots of updates based on feedback.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 5 ++++-
arch/x86/kernel/cpu/intel.c | 14 ++++++++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
arch/x86/kernel/cpu/proc.c | 3 ++-
arch/x86/kernel/microcode_intel.c | 14 +++++---------
5 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 4c25ab4..3d0f214 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,8 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ /* CPU update signature */
+ u32 cpu_update;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +181,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1edf5ba..ba5ba17 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -364,6 +364,20 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
early_init_intel(c);
+ /* Determine CPU update level */
+ if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+ unsigned lower_word;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* The CPUID 1 fills in the MSR as documented in the SDM */
+ /*
+ * Wrong comment from microcode_intel.c:
+ * see notes above for revision 1.07. Apparent chip bug
+ */
+ cpuid_eax(1);
+ rdmsr(MSR_IA32_UCODE_REV, lower_word, c->cpu_update);
+ }
+
intel_workarounds(c);
/*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index ff1ae9b..1d3cf21 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -220,8 +220,9 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x CPU-UPDATE %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).cpu_update);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..f27d6e5 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "stepping\t: %d\n", c->x86_mask);
else
seq_printf(m, "stepping\t: unknown\n");
+ if (c->cpu_update)
+ seq_printf(m, "cpu update\t: %u\n", c->cpu_update);
if (cpu_has(c, X86_FEATURE_TSC)) {
unsigned int freq = cpufreq_quick_get(cpu);
@@ -132,7 +134,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, " [%d]", i);
}
}
-
seq_printf(m, "\n\n");
return 0;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..1efe9d4 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->cpu_update;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
struct microcode_intel *mc_intel;
struct ucode_cpu_info *uci;
unsigned int val[2];
- int cpu_num;
+ int cpu_num = raw_smp_processor_id();
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
- cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
mc_intel = uci->mc;
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
(unsigned long) mc_intel->bits >> 16 >> 16);
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
+ /* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->cpu_update = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-05-25 19:32 [PATCH 1/3] x86, intel: Output microcode revision v2 Andi Kleen
@ 2011-05-25 19:32 ` Andi Kleen
2011-05-26 7:39 ` Jean Delvare
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-05-25 19:32 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ba5ba17..701efa4 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->cpu_update < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-05-25 19:32 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
@ 2011-05-26 7:39 ` Jean Delvare
0 siblings, 0 replies; 15+ messages in thread
From: Jean Delvare @ 2011-05-26 7:39 UTC (permalink / raw)
To: Andi Kleen; +Cc: x86, linux-kernel, Andi Kleen
On Wed, 25 May 2011 12:32:27 -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> Now that the cpu update level is available the Atom PSE errata
> check can use it directly without reading the MSR again.
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Jean Delvare <khali@linux-fr.org>
> ---
> arch/x86/kernel/cpu/intel.c | 15 ++++-----------
> 1 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index ba5ba17..701efa4 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
> * need the microcode to have already been loaded... so if it is
> * not, recommend a BIOS update and disable large pages.
> */
> - if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
> - u32 ucode, junk;
> -
> - wrmsr(MSR_IA32_UCODE_REV, 0, 0);
> - sync_core();
> - rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
> -
> - if (ucode < 0x20e) {
> - printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
> - clear_cpu_cap(c, X86_FEATURE_PSE);
> - }
> + if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
> + c->cpu_update < 0x20e) {
> + printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
> + clear_cpu_cap(c, X86_FEATURE_PSE);
> }
>
> #ifdef CONFIG_X86_64
--
Jean Delvare
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/3] x86, intel: Output microcode revision
@ 2011-05-24 23:03 Andi Kleen
2011-05-24 23:03 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-05-24 23:03 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
I got a request to make it easier to determine the microcode update level
on Intel CPUs. This patch adds a new "cpu update" field to /proc/cpuinfo,
which I added at the end to minimize impact on parsers.
The update level is also outputed on fatal machine checks together
with the other CPUID model information.
I removed the respective code from the microcode update driver, it
just reads the field from cpu_data. Also when the microcode is updated
it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it being
optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/processor.h | 5 ++++-
arch/x86/kernel/cpu/intel.c | 10 ++++++++++
arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
arch/x86/kernel/cpu/proc.c | 6 +++++-
arch/x86/kernel/microcode_intel.c | 9 +++------
5 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 4c25ab4..23b7e26 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,8 @@ struct cpuinfo_x86 {
/* Index into per_cpu list: */
u16 cpu_index;
#endif
+ /* CPU update signature */
+ u32 x86_cpu_update;
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
#define X86_VENDOR_INTEL 0
@@ -179,7 +181,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
"=b" (*ebx),
"=c" (*ecx),
"=d" (*edx)
- : "0" (*eax), "2" (*ecx));
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
}
static inline void load_cr3(pgd_t *pgdir)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1edf5ba..150623a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -364,6 +364,16 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
early_init_intel(c);
+ /* Determine CPU update level */
+ if (c->x86 >= 6 && !(cpu_has(c, X86_FEATURE_IA64))) {
+ unsigned lo;
+
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+ /* The CPUID 1 fills in the MSR */
+ cpuid_eax(1);
+ rdmsr(MSR_IA32_UCODE_REV, lo, c->x86_cpu_update);
+ }
+
intel_workarounds(c);
/*
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index ff1ae9b..e93c41f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -220,8 +220,9 @@ static void print_mce(struct mce *m)
pr_cont("MISC %llx ", m->misc);
pr_cont("\n");
- pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
- m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+ pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x CPU-UPDATE %u\n",
+ m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+ cpu_data(m->extcpu).x86_cpu_update);
/*
* Print out human-readable details about the MCE error,
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb..cefcc27 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -132,8 +132,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, " [%d]", i);
}
}
+ seq_printf(m, "\n");
- seq_printf(m, "\n\n");
+ if (c->x86_cpu_update)
+ seq_printf(m, "cpu update\t: %u\n", c->x86_cpu_update);
+
+ seq_printf(m, "\n");
return 0;
}
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606..bb1fec6 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
csig->pf = 1 << ((val[1] >> 18) & 7);
}
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- /* see notes above for revision 1.07. Apparent chip bug */
- sync_core();
- /* get the current revision from MSR 0x8B */
- rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+ csig->rev = c->x86_cpu_update;
pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
cpu_num, csig->sig, csig->pf, csig->rev);
@@ -300,6 +295,7 @@ static int apply_microcode(int cpu)
struct ucode_cpu_info *uci;
unsigned int val[2];
int cpu_num;
+ struct cpuinfo_x86 *c = &cpu_data(cpu_num);
cpu_num = raw_smp_processor_id();
uci = ucode_cpu_info + cpu;
@@ -335,6 +331,7 @@ static int apply_microcode(int cpu)
(mc_intel->hdr.date >> 16) & 0xff);
uci->cpu_sig.rev = val[1];
+ c->x86_cpu_update = val[1];
return 0;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-05-24 23:03 [PATCH 1/3] x86, intel: Output microcode revision Andi Kleen
@ 2011-05-24 23:03 ` Andi Kleen
2011-05-25 6:59 ` Ingo Molnar
0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2011-05-24 23:03 UTC (permalink / raw)
To: x86; +Cc: linux-kernel, Andi Kleen
From: Andi Kleen <ak@linux.intel.com>
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/intel.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 150623a..9ae3782 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -55,17 +55,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
- u32 ucode, junk;
-
- wrmsr(MSR_IA32_UCODE_REV, 0, 0);
- sync_core();
- rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
-
- if (ucode < 0x20e) {
- printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
- clear_cpu_cap(c, X86_FEATURE_PSE);
- }
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ c->x86_cpu_update < 0x20e) {
+ printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
+ clear_cpu_cap(c, X86_FEATURE_PSE);
}
#ifdef CONFIG_X86_64
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check
2011-05-24 23:03 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
@ 2011-05-25 6:59 ` Ingo Molnar
0 siblings, 0 replies; 15+ messages in thread
From: Ingo Molnar @ 2011-05-25 6:59 UTC (permalink / raw)
To: Andi Kleen
Cc: x86, linux-kernel, Andi Kleen, Borislav Petkov, H. Peter Anvin,
Thomas Gleixner
* Andi Kleen <andi@firstfloor.org> wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> Now that the cpu update level is available the Atom PSE errata
> check can use it directly without reading the MSR again.
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
> arch/x86/kernel/cpu/intel.c | 15 ++++-----------
Ok, it's nice that you have split this one out.
Please also split out the MCE printk change you did in the first patch - even
if it's a oneliner we want the first patch to only include changes focused to
the primary purpose alone: the introduction of x86_cpu::microcode_version.
Also, please split the first patch into two other parts: a first one that
factors out the Intel microcode-version MSR function into a separate function,
and the second patch that introduces the x86_cpu::microcode_version field and
fills it in in the CPU detection code and keeps it updated in the microcode
driver.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2011-10-13 22:55 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-07-01 19:21 [PATCH 1/3] x86, intel: Output microcode revision v3 Andi Kleen
2011-07-01 19:21 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-07-01 19:21 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
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2011-10-13 22:55 [PATCH 1/3] x86, intel: Output microcode revision v7 Andi Kleen
2011-10-13 22:55 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-10-13 0:46 [PATCH 1/3] x86, intel: Output microcode revision v6 Andi Kleen
2011-10-13 0:46 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-10-13 5:38 ` H. Peter Anvin
2011-09-28 23:19 [PATCH 1/3] x86, intel: Output microcode revision v5 Andi Kleen
2011-09-28 23:19 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-08-29 23:47 [PATCH 1/3] x86, intel: Output microcode revision v4 Andi Kleen
2011-08-29 23:47 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-08-29 23:47 ` [PATCH 3/3] coretemp: Get microcode revision from cpu_data v2 Andi Kleen
2011-08-30 1:08 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Yu, Fenghua
2011-07-06 23:57 [PATCH 1/3] x86, intel: Output microcode revision v3 Andi Kleen
2011-07-06 23:57 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-07-11 8:19 ` Jean Delvare
2011-05-25 19:32 [PATCH 1/3] x86, intel: Output microcode revision v2 Andi Kleen
2011-05-25 19:32 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-05-26 7:39 ` Jean Delvare
2011-05-24 23:03 [PATCH 1/3] x86, intel: Output microcode revision Andi Kleen
2011-05-24 23:03 ` [PATCH 2/3] x86, intel: Use cpu_update for Atom errata check Andi Kleen
2011-05-25 6:59 ` Ingo Molnar
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