From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 11/13] clk: qcom: support for Brammo PLL
Date: Thu, 28 Sep 2017 23:20:48 +0530 [thread overview]
Message-ID: <1506621050-10129-12-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org>
1. Brammo PLL does not allow configuration of VCO
2. Supports the dynamic update in which the frequency can
be changed dynamically without turning off the PLL
3. The register offsets are different from normal Alpha PLL
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 24 ++++++++++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 4844e63..c682387 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -922,4 +922,28 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
.set_rate = alpha_pll_huayra_set_rate,
},
},
+ [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
+ .reg_offsets = {
+ [PLL_L_VAL] = 0x04,
+ [PLL_ALPHA_VAL] = 0x08,
+ [PLL_ALPHA_VAL_U] = 0x0c,
+ [PLL_USER_CTL] = 0x10,
+ [PLL_CONFIG_CTL] = 0x18,
+ [PLL_TEST_CTL] = 0x1c,
+ [PLL_STATUS] = 0x24,
+ },
+ .alpha_width = 40,
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .ops = {
+ .enable = alpha_pll_default_enable,
+ .disable = alpha_pll_default_disable,
+ .is_enabled = alpha_pll_default_is_enabled,
+ .hwfsm_enable = alpha_pll_default_hwfsm_enable,
+ .hwfsm_disable = alpha_pll_default_hwfsm_disable,
+ .hwfsm_is_enabled = alpha_pll_default_hwfsm_is_enabled,
+ .recalc_rate = alpha_pll_default_recalc_rate,
+ .round_rate = alpha_pll_default_round_rate,
+ .set_rate = alpha_pll_default_set_rate,
+ },
+ },
};
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index fed783e..dee71b4 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -21,6 +21,7 @@
enum {
CLK_ALPHA_PLL_TYPE_DEFAULT,
CLK_ALPHA_PLL_TYPE_HUAYRA,
+ CLK_ALPHA_PLL_TYPE_BRAMMO,
CLK_ALPHA_PLL_TYPE_MAX,
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-09-28 17:52 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-28 17:50 [PATCH 00/13] Updates for QCOM Alpha PLL Abhishek Sahu
2017-09-28 17:50 ` [PATCH 01/13] clk: qcom: remove redundant PLL_MODE macro offset Abhishek Sahu
2017-09-28 17:50 ` [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable Abhishek Sahu
2017-09-28 17:50 ` [PATCH 03/13] clk: qcom: support for alpha pll properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 07/13] clk: qcom: support for alpha mode configuration Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 09/13] clk: qcom: add flag for VCO operation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 10/13] clk: qcom: support for Huayra PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` Abhishek Sahu [this message]
2017-12-09 0:18 ` [PATCH 11/13] clk: qcom: support for Brammo PLL Stephen Boyd
2017-09-28 17:50 ` [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 13/13] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-12-07 6:23 ` [PATCH 00/13] Updates for QCOM Alpha PLL Stephen Boyd
2017-12-08 15:55 ` Abhishek Sahu
2017-12-09 0:16 ` Stephen Boyd
2017-12-11 6:26 ` Abhishek Sahu
2017-12-13 22:23 ` Stephen Boyd
2017-12-14 5:48 ` Abhishek Sahu
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