linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 01/13] clk: qcom: remove redundant PLL_MODE macro offset
Date: Thu, 28 Sep 2017 23:20:38 +0530	[thread overview]
Message-ID: <1506621050-10129-2-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org>

The PLL_MODE offset macro is redundant which is defined as zero.
The offset in PLL structure is the address of PLL_MODE register
itself so the PLL_MODE can be removed. It will help in subsequent
patches to support different PLL offset registers to reduce the
code diff.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 33 ++++++++++++++++-----------------
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 47a1da3..b9be822 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -20,7 +20,6 @@
 #include "clk-alpha-pll.h"
 #include "common.h"
 
-#define PLL_MODE		0x00
 # define PLL_OUTCTRL		BIT(0)
 # define PLL_BYPASSNL		BIT(1)
 # define PLL_RESET_N		BIT(2)
@@ -77,12 +76,12 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 	const char *name = clk_hw_get_name(&pll->clkr.hw);
 
 	off = pll->offset;
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
 
 	for (count = 100; count > 0; count--) {
-		ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+		ret = regmap_read(pll->clkr.regmap, off, &val);
 		if (ret)
 			return ret;
 		if (inverse && !(val & mask))
@@ -139,7 +138,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 	regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
 
 	if (pll->flags & SUPPORTS_FSM_MODE)
-		qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
+		qcom_pll_set_fsm_mode(regmap, off, 6, 0);
 }
 
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
@@ -149,7 +148,7 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 
 	off = pll->offset;
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
 
@@ -158,7 +157,7 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 	if (pll->flags & SUPPORTS_OFFLINE_REQ)
 		val &= ~PLL_OFFLINE_REQ;
 
-	ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val);
+	ret = regmap_write(pll->clkr.regmap, off, val);
 	if (ret)
 		return ret;
 
@@ -175,12 +174,12 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 
 	off = pll->offset;
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return;
 
 	if (pll->flags & SUPPORTS_OFFLINE_REQ) {
-		ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+		ret = regmap_update_bits(pll->clkr.regmap, off,
 					 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
 		if (ret)
 			return;
@@ -191,7 +190,7 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 	}
 
 	/* Disable hwfsm */
-	ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+	ret = regmap_update_bits(pll->clkr.regmap, off,
 				 PLL_FSM_ENA, 0);
 	if (ret)
 		return;
@@ -206,7 +205,7 @@ static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 
 	off = pll->offset;
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
 
@@ -232,7 +231,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
 	off = pll->offset;
 
 	mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
 
@@ -248,7 +247,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
 	if ((val & mask) == mask)
 		return 0;
 
-	ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+	ret = regmap_update_bits(pll->clkr.regmap, off,
 				 PLL_BYPASSNL, PLL_BYPASSNL);
 	if (ret)
 		return ret;
@@ -260,7 +259,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
 	mb();
 	udelay(5);
 
-	ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+	ret = regmap_update_bits(pll->clkr.regmap, off,
 				 PLL_RESET_N, PLL_RESET_N);
 	if (ret)
 		return ret;
@@ -269,7 +268,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
 	if (ret)
 		return ret;
 
-	ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+	ret = regmap_update_bits(pll->clkr.regmap, off,
 				 PLL_OUTCTRL, PLL_OUTCTRL);
 
 	/* Ensure that the write above goes through before returning. */
@@ -285,7 +284,7 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
 
 	off = pll->offset;
 
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return;
 
@@ -296,14 +295,14 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
 	}
 
 	mask = PLL_OUTCTRL;
-	regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+	regmap_update_bits(pll->clkr.regmap, off, mask, 0);
 
 	/* Delay of 2 output clock ticks required until output is disabled */
 	mb();
 	udelay(1);
 
 	mask = PLL_RESET_N | PLL_BYPASSNL;
-	regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+	regmap_update_bits(pll->clkr.regmap, off, mask, 0);
 }
 
 static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

  reply	other threads:[~2017-09-28 17:51 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-28 17:50 [PATCH 00/13] Updates for QCOM Alpha PLL Abhishek Sahu
2017-09-28 17:50 ` Abhishek Sahu [this message]
2017-09-28 17:50 ` [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable Abhishek Sahu
2017-09-28 17:50 ` [PATCH 03/13] clk: qcom: support for alpha pll properties Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 07/13] clk: qcom: support for alpha mode configuration Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 09/13] clk: qcom: add flag for VCO operation Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 10/13] clk: qcom: support for Huayra PLL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 11/13] clk: qcom: support for Brammo PLL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 13/13] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-12-07  6:23 ` [PATCH 00/13] Updates for QCOM Alpha PLL Stephen Boyd
2017-12-08 15:55   ` Abhishek Sahu
2017-12-09  0:16     ` Stephen Boyd
2017-12-11  6:26       ` Abhishek Sahu
2017-12-13 22:23         ` Stephen Boyd
2017-12-14  5:48           ` Abhishek Sahu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1506621050-10129-2-git-send-email-absahu@codeaurora.org \
    --to=absahu@codeaurora.org \
    --cc=andy.gross@linaro.org \
    --cc=david.brown@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-soc@vger.kernel.org \
    --cc=mturquette@baylibre.com \
    --cc=rnayak@codeaurora.org \
    --cc=sboyd@codeaurora.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).