From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL
Date: Thu, 28 Sep 2017 23:20:43 +0530 [thread overview]
Message-ID: <1506621050-10129-7-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org>
Some of the Alpha PLL’s (like Spark, Brammo PLL) do not have
CONFIG_CTL_U register. This patch adds the flag in properties
for PLL’s which have CONFIG_CTL_U register and checks the same
while doing PLL initial configuration.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 78eb6bf..b33d120 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -49,6 +49,9 @@
/* Returns the Alpha register width for pll type */
#define pll_alpha_width(type) (alpha_pll_props[type].alpha_width)
+/* Returns the flags for pll type */
+#define pll_flags(type) (alpha_pll_props[type].flags)
+
/* Returns the alpha_pll_clk_ops for pll type */
#define pll_clk_ops(hw) (alpha_pll_props[to_clk_alpha_pll(hw)-> \
pll_type].ops)
@@ -130,6 +133,9 @@ struct alpha_pll_clk_ops {
struct alpha_pll_props {
u8 reg_offsets[PLL_MAX_REGS];
u8 alpha_width;
+
+#define HAVE_64BIT_CONFIG_CTL BIT(0)
+ u8 flags;
struct alpha_pll_clk_ops ops;
};
@@ -180,7 +186,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
{
u32 val, mask;
u32 off = pll->offset;
- u8 type = pll->pll_type;
+ u8 type = pll->pll_type, flags = pll_flags(type);
regmap_write(regmap, off + pll_l(type), config->l);
regmap_write(regmap, off + pll_alpha(type), config->alpha);
@@ -188,6 +194,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
regmap_write(regmap, off + pll_cfg_ctl_u(type),
config->config_ctl_hi_val);
+ if (flags & HAVE_64BIT_CONFIG_CTL)
+ regmap_write(regmap, off + pll_cfg_ctl_u(type),
+ config->config_ctl_hi_val);
+
val = config->main_output_mask;
val |= config->aux_output_mask;
val |= config->aux2_output_mask;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-09-28 17:53 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-28 17:50 [PATCH 00/13] Updates for QCOM Alpha PLL Abhishek Sahu
2017-09-28 17:50 ` [PATCH 01/13] clk: qcom: remove redundant PLL_MODE macro offset Abhishek Sahu
2017-09-28 17:50 ` [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable Abhishek Sahu
2017-09-28 17:50 ` [PATCH 03/13] clk: qcom: support for alpha pll properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` Abhishek Sahu [this message]
2017-12-09 0:18 ` [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Stephen Boyd
2017-09-28 17:50 ` [PATCH 07/13] clk: qcom: support for alpha mode configuration Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 09/13] clk: qcom: add flag for VCO operation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 10/13] clk: qcom: support for Huayra PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 11/13] clk: qcom: support for Brammo PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 13/13] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-12-07 6:23 ` [PATCH 00/13] Updates for QCOM Alpha PLL Stephen Boyd
2017-12-08 15:55 ` Abhishek Sahu
2017-12-09 0:16 ` Stephen Boyd
2017-12-11 6:26 ` Abhishek Sahu
2017-12-13 22:23 ` Stephen Boyd
2017-12-14 5:48 ` Abhishek Sahu
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