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From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable
Date: Thu, 28 Sep 2017 23:20:39 +0530	[thread overview]
Message-ID: <1506621050-10129-3-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org>

This patch does minor code reorganization related with offset
variable assignment. The offset variable can be directly defined
which will help in subsequent patches to support different PLL
offset registers.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index b9be822..ab2f23c 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -70,12 +70,11 @@
 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 			const char *action)
 {
-	u32 val, off;
+	u32 val, off = pll->offset;
 	int count;
 	int ret;
 	const char *name = clk_hw_get_name(&pll->clkr.hw);
 
-	off = pll->offset;
 	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
@@ -143,11 +142,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 {
-	int ret;
-	u32 val, off;
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	int ret;
+	u32 val, off = pll->offset;
 
-	off = pll->offset;
 	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
@@ -169,11 +167,10 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 
 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 {
-	int ret;
-	u32 val, off;
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	int ret;
+	u32 val, off = pll->offset;
 
-	off = pll->offset;
 	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return;
@@ -200,11 +197,10 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 
 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 {
-	int ret;
-	u32 val, off;
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	int ret;
+	u32 val, off = pll->offset;
 
-	off = pll->offset;
 	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
 		return ret;
@@ -226,9 +222,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
 {
 	int ret;
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	u32 val, mask, off;
-
-	off = pll->offset;
+	u32 val, mask, off = pll->offset;
 
 	mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
 	ret = regmap_read(pll->clkr.regmap, off, &val);
@@ -280,9 +274,7 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
 {
 	int ret;
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	u32 val, mask, off;
-
-	off = pll->offset;
+	u32 val, mask, off = pll->offset;
 
 	ret = regmap_read(pll->clkr.regmap, off, &val);
 	if (ret)
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

  parent reply	other threads:[~2017-09-28 17:54 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-28 17:50 [PATCH 00/13] Updates for QCOM Alpha PLL Abhishek Sahu
2017-09-28 17:50 ` [PATCH 01/13] clk: qcom: remove redundant PLL_MODE macro offset Abhishek Sahu
2017-09-28 17:50 ` Abhishek Sahu [this message]
2017-09-28 17:50 ` [PATCH 03/13] clk: qcom: support for alpha pll properties Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 07/13] clk: qcom: support for alpha mode configuration Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 09/13] clk: qcom: add flag for VCO operation Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 10/13] clk: qcom: support for Huayra PLL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 11/13] clk: qcom: support for Brammo PLL Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 13/13] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu
2017-12-09  0:18   ` Stephen Boyd
2017-12-07  6:23 ` [PATCH 00/13] Updates for QCOM Alpha PLL Stephen Boyd
2017-12-08 15:55   ` Abhishek Sahu
2017-12-09  0:16     ` Stephen Boyd
2017-12-11  6:26       ` Abhishek Sahu
2017-12-13 22:23         ` Stephen Boyd
2017-12-14  5:48           ` Abhishek Sahu

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