From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider
Date: Thu, 28 Sep 2017 23:20:49 +0530 [thread overview]
Message-ID: <1506621050-10129-13-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org>
Current PLL driver only supports 4 bit PLL post divider so
modified the PLL divider operations to support 2 bit PLL
post divider.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index c682387..62b84fa 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -39,7 +39,6 @@
# define PLL_LOCK_DET BIT(31)
# define PLL_POST_DIV_SHIFT 8
-# define PLL_POST_DIV_MASK 0xf
# define PLL_ALPHA_EN BIT(24)
# define PLL_ALPHA_MODE BIT(25)
# define PLL_VCO_SHIFT 20
@@ -822,7 +821,7 @@ static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
&ctl);
ctl >>= PLL_POST_DIV_SHIFT;
- ctl &= PLL_POST_DIV_MASK;
+ ctl &= BIT(pll->width) - 1;
return parent_rate >> fls(ctl);
}
@@ -836,13 +835,26 @@ static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
{ }
};
+static const struct clk_div_table clk_alpha_2bit_div_table[] = {
+ { 0x0, 1 },
+ { 0x1, 2 },
+ { 0x3, 4 },
+ { }
+};
+
static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+ const struct clk_div_table *table;
- return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
+ if (pll->width == 2)
+ table = clk_alpha_2bit_div_table;
+ else
+ table = clk_alpha_div_table;
+
+ return divider_round_rate(hw, rate, prate, table,
pll->width, CLK_DIVIDER_POWER_OF_TWO);
}
@@ -857,7 +869,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
return regmap_update_bits(pll->clkr.regmap, pll->offset +
pll_user_ctl(pll->pll_type),
- PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
+ (BIT(pll->width) - 1) << PLL_POST_DIV_SHIFT,
div << PLL_POST_DIV_SHIFT);
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-09-28 17:51 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-28 17:50 [PATCH 00/13] Updates for QCOM Alpha PLL Abhishek Sahu
2017-09-28 17:50 ` [PATCH 01/13] clk: qcom: remove redundant PLL_MODE macro offset Abhishek Sahu
2017-09-28 17:50 ` [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable Abhishek Sahu
2017-09-28 17:50 ` [PATCH 03/13] clk: qcom: support for alpha pll properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 07/13] clk: qcom: support for alpha mode configuration Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 09/13] clk: qcom: add flag for VCO operation Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 10/13] clk: qcom: support for Huayra PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` [PATCH 11/13] clk: qcom: support for Brammo PLL Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-09-28 17:50 ` Abhishek Sahu [this message]
2017-12-09 0:18 ` [PATCH 12/13] clk: qcom: support for 2 bit PLL post divider Stephen Boyd
2017-09-28 17:50 ` [PATCH 13/13] clk: qcom: add read-only alpha pll post divider operations Abhishek Sahu
2017-12-09 0:18 ` Stephen Boyd
2017-12-07 6:23 ` [PATCH 00/13] Updates for QCOM Alpha PLL Stephen Boyd
2017-12-08 15:55 ` Abhishek Sahu
2017-12-09 0:16 ` Stephen Boyd
2017-12-11 6:26 ` Abhishek Sahu
2017-12-13 22:23 ` Stephen Boyd
2017-12-14 5:48 ` Abhishek Sahu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1506621050-10129-13-git-send-email-absahu@codeaurora.org \
--to=absahu@codeaurora.org \
--cc=andy.gross@linaro.org \
--cc=david.brown@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-soc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=rnayak@codeaurora.org \
--cc=sboyd@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).