From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>, "H Peter Anvin" <hpa@zytor.com>,
"David Woodhouse" <dwmw2@infradead.org>,
"Lu Baolu" <baolu.lu@linux.intel.com>,
"Frederic Barrat" <fbarrat@linux.ibm.com>,
"Andrew Donnellan" <ajd@linux.ibm.com>,
"Felix Kuehling" <Felix.Kuehling@amd.com>,
"Joerg Roedel" <joro@8bytes.org>,
"Dave Hansen" <dave.hansen@intel.com>,
"Tony Luck" <tony.luck@intel.com>,
"Ashok Raj" <ashok.raj@intel.com>,
"Jacob Jun Pan" <jacob.jun.pan@intel.com>,
"Dave Jiang" <dave.jiang@intel.com>,
"Yu-cheng Yu" <yu-cheng.yu@intel.com>,
"Sohil Mehta" <sohil.mehta@intel.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>,
iommu@lists.linux-foundation.org,
"amd-gfx" <amd-gfx@lists.freedesktop.org>,
"linuxppc-dev" <linuxppc-dev@lists.ozlabs.org>,
Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH v2 06/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature
Date: Fri, 12 Jun 2020 17:41:27 -0700 [thread overview]
Message-ID: <1592008893-9388-7-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1592008893-9388-1-git-send-email-fenghua.yu@intel.com>
From: Yu-cheng Yu <yu-cheng.yu@intel.com>
ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored
in the task's supervisor FPU PASID state and is context switched by
XSAVES/XRSTORS.
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Co-developed-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
v2:
- Modify the commit message (Thomas)
arch/x86/include/asm/fpu/types.h | 10 ++++++++++
arch/x86/include/asm/fpu/xstate.h | 2 +-
arch/x86/kernel/fpu/xstate.c | 4 ++++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h
index f098f6cab94b..00f8efd4c07d 100644
--- a/arch/x86/include/asm/fpu/types.h
+++ b/arch/x86/include/asm/fpu/types.h
@@ -114,6 +114,7 @@ enum xfeature {
XFEATURE_Hi16_ZMM,
XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
XFEATURE_PKRU,
+ XFEATURE_PASID,
XFEATURE_MAX,
};
@@ -128,6 +129,7 @@ enum xfeature {
#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
#define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
+#define XFEATURE_MASK_PASID (1 << XFEATURE_PASID)
#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \
@@ -229,6 +231,14 @@ struct pkru_state {
u32 pad;
} __packed;
+/*
+ * State component 10 is supervisor state used for context-switching the
+ * PASID state.
+ */
+struct ia32_pasid_state {
+ u64 pasid;
+} __packed;
+
struct xstate_header {
u64 xfeatures;
u64 xcomp_bv;
diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h
index 422d8369012a..ab9833c57aaa 100644
--- a/arch/x86/include/asm/fpu/xstate.h
+++ b/arch/x86/include/asm/fpu/xstate.h
@@ -33,7 +33,7 @@
XFEATURE_MASK_BNDCSR)
/* All currently supported supervisor features */
-#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (0)
+#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID)
/*
* Unsupported supervisor features. When a supervisor feature in this mask is
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index bda2e5eaca0e..31629e43383c 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -37,6 +37,7 @@ static const char *xfeature_names[] =
"AVX-512 ZMM_Hi256" ,
"Processor Trace (unused)" ,
"Protection Keys User registers",
+ "PASID state",
"unknown xstate feature" ,
};
@@ -51,6 +52,7 @@ static short xsave_cpuid_features[] __initdata = {
X86_FEATURE_AVX512F,
X86_FEATURE_INTEL_PT,
X86_FEATURE_PKU,
+ X86_FEATURE_ENQCMD,
};
/*
@@ -316,6 +318,7 @@ static void __init print_xstate_features(void)
print_xstate_feature(XFEATURE_MASK_ZMM_Hi256);
print_xstate_feature(XFEATURE_MASK_Hi16_ZMM);
print_xstate_feature(XFEATURE_MASK_PKRU);
+ print_xstate_feature(XFEATURE_MASK_PASID);
}
/*
@@ -590,6 +593,7 @@ static void check_xstate_against_struct(int nr)
XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state);
XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state);
XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state);
+ XCHECK_SZ(sz, nr, XFEATURE_PASID, struct ia32_pasid_state);
/*
* Make *SURE* to add any feature numbers in below if
--
2.19.1
next prev parent reply other threads:[~2020-06-13 0:42 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-13 0:41 [PATCH v2 00/12] x86: tag application address space for devices Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 01/12] iommu: Change type of pasid to unsigned int Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 02/12] ocxl: " Fenghua Yu
2020-06-18 8:05 ` Frederic Barrat
2020-06-18 15:37 ` Fenghua Yu
2020-06-18 16:56 ` Frederic Barrat
2020-06-13 0:41 ` [PATCH v2 03/12] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 04/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2020-06-13 12:17 ` Lu Baolu
2020-06-15 23:16 ` Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 05/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-06-13 0:41 ` Fenghua Yu [this message]
2020-06-13 0:41 ` [PATCH v2 07/12] x86/msr-index: Define IA32_PASID MSR Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 08/12] mm: Define pasid in mm Fenghua Yu
2020-06-16 8:28 ` Jean-Philippe Brucker
2020-06-16 15:11 ` Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 09/12] fork: Clear PASID for new mm Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 10/12] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 11/12] x86/mmu: Allocate/free PASID Fenghua Yu
2020-06-13 13:07 ` Lu Baolu
2020-06-15 2:13 ` Lu Baolu
2020-06-13 0:41 ` [PATCH v2 12/12] x86/traps: Fix up invalid PASID Fenghua Yu
2020-06-15 7:53 ` Peter Zijlstra
2020-06-15 7:56 ` Peter Zijlstra
2020-06-15 15:48 ` Fenghua Yu
2020-06-15 16:03 ` Peter Zijlstra
2020-06-15 17:11 ` Luck, Tony
2020-06-15 18:12 ` Fenghua Yu
2020-06-15 18:31 ` Peter Zijlstra
2020-06-15 18:55 ` Fenghua Yu
2020-06-15 19:09 ` Peter Zijlstra
2020-06-15 20:17 ` Fenghua Yu
2020-06-15 20:51 ` Andy Lutomirski
2020-06-15 20:56 ` Luck, Tony
2020-06-15 21:18 ` Andy Lutomirski
2020-06-15 21:24 ` Luck, Tony
2020-06-15 21:53 ` Peter Zijlstra
2020-06-16 23:23 ` Fenghua Yu
2020-06-17 8:31 ` Peter Zijlstra
2020-06-15 18:19 ` Raj, Ashok
2020-06-15 18:32 ` Peter Zijlstra
2020-06-15 7:52 ` [PATCH v2 00/12] x86: tag application address space for devices Peter Zijlstra
2020-06-15 14:53 ` Fenghua Yu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1592008893-9388-7-git-send-email-fenghua.yu@intel.com \
--to=fenghua.yu@intel.com \
--cc=Felix.Kuehling@amd.com \
--cc=ajd@linux.ibm.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=ashok.raj@intel.com \
--cc=baolu.lu@linux.intel.com \
--cc=bp@alien8.de \
--cc=dave.hansen@intel.com \
--cc=dave.jiang@intel.com \
--cc=dwmw2@infradead.org \
--cc=fbarrat@linux.ibm.com \
--cc=hpa@zytor.com \
--cc=iommu@lists.linux-foundation.org \
--cc=jacob.jun.pan@intel.com \
--cc=joro@8bytes.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mingo@redhat.com \
--cc=ravi.v.shankar@intel.com \
--cc=sohil.mehta@intel.com \
--cc=tglx@linutronix.de \
--cc=tony.luck@intel.com \
--cc=x86@kernel.org \
--cc=yu-cheng.yu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).