From: Peter Zijlstra <peterz@infradead.org>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
H Peter Anvin <hpa@zytor.com>,
David Woodhouse <dwmw2@infradead.org>,
Lu Baolu <baolu.lu@linux.intel.com>,
Frederic Barrat <fbarrat@linux.ibm.com>,
Andrew Donnellan <ajd@linux.ibm.com>,
Felix Kuehling <Felix.Kuehling@amd.com>,
Joerg Roedel <joro@8bytes.org>,
Dave Hansen <dave.hansen@intel.com>,
Tony Luck <tony.luck@intel.com>, Ashok Raj <ashok.raj@intel.com>,
Jacob Jun Pan <jacob.jun.pan@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
Yu-cheng Yu <yu-cheng.yu@intel.com>,
Sohil Mehta <sohil.mehta@intel.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
iommu@lists.linux-foundation.org,
amd-gfx <amd-gfx@lists.freedesktop.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH v2 12/12] x86/traps: Fix up invalid PASID
Date: Mon, 15 Jun 2020 18:03:57 +0200 [thread overview]
Message-ID: <20200615160357.GA2531@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20200615154854.GB13792@romley-ivt3.sc.intel.com>
On Mon, Jun 15, 2020 at 08:48:54AM -0700, Fenghua Yu wrote:
> Hi, Peter,
> On Mon, Jun 15, 2020 at 09:56:49AM +0200, Peter Zijlstra wrote:
> > On Fri, Jun 12, 2020 at 05:41:33PM -0700, Fenghua Yu wrote:
> > > +/*
> > > + * Apply some heuristics to see if the #GP fault was caused by a thread
> > > + * that hasn't had the IA32_PASID MSR initialized. If it looks like that
> > > + * is the problem, try initializing the IA32_PASID MSR. If the heuristic
> > > + * guesses incorrectly, take one more #GP fault.
> >
> > How is that going to help? Aren't we then going to run this same
> > heuristic again and again and again?
>
> The heuristic always initializes the MSR with the per mm PASID IIF the
> mm has a valid PASID but the MSR doesn't have one. This heuristic usually
> happens only once on the first #GP in a thread.
But it doesn't guarantee the PASID is the right one. Suppose both the mm
has a PASID and the MSR has a VALID one, but the MSR isn't the mm one.
Then we NO-OP. So if the exception was due to us having the wrong PASID,
we stuck.
> If the next #GP still comes in, the heuristic finds out the MSR already
> has a valid PASID and thus will not fixup the MSR any more. The fixup()
> returns "false" and lets others to handle the #GP.
>
> So the heuristic will be executed once (at most) and won't be executed
> again and again.
So I get that you want to set the PASID on-demand, but I find this all
really weird code to make that happen.
> > > +bool __fixup_pasid_exception(void)
> > > +{
> > > + u64 pasid_msr;
> > > + unsigned int pasid;
> > > +
> > > + /*
> > > + * This function is called only when this #GP was triggered from user
> > > + * space. So the mm cannot be NULL.
> > > + */
> > > + pasid = current->mm->pasid;
> > > + /* If the mm doesn't have a valid PASID, then can't help. */
> > > + if (invalid_pasid(pasid))
> > > + return false;
> > > +
> > > + /*
> > > + * Since IRQ is disabled now, the current task still owns the FPU on
> >
> > That's just weird and confusing. What you want to say is that you rely
> > on the exception disabling the interrupt.
>
> I checked SDM again. You are right. #GP can be interrupted by machine check
> or other interrupts. So I cannot assume the current task still owns the FPU.
> Instead of directly rdmsr() and wrmsr(), I will add helpers that can access
> either the MSR on the processor or the PASID state in the memory.
That's not in fact what I meant, but yes, you can take exceptions while
!IF just fine.
> > > + * this CPU and the PASID MSR can be directly accessed.
> > > + *
> > > + * If the MSR has a valid PASID, the #GP must be for some other reason.
> > > + *
> > > + * If rdmsr() is really a performance issue, a TIF_ flag may be
> > > + * added to check if the thread has a valid PASID instead of rdmsr().
> >
> > I don't understand any of this. Nobody except us writes to this MSR, we
> > should bloody well know what's in it. What gives?
>
> Patch 4 describes how to manage the MSR and patch 7 describes the format
> of the MSR (20-bit PASID value and bit 31 is valid bit).
>
> Are they sufficient to help? Or do you mean something else?
I don't get why you need a rdmsr here, or why not having one would
require a TIF flag. Is that because this MSR is XSAVE/XRSTOR managed?
> > > + */
> > > + rdmsrl(MSR_IA32_PASID, pasid_msr);
> > > + if (pasid_msr & MSR_IA32_PASID_VALID)
> > > + return false;
> > > +
> > > + /* Fix up the MSR if the MSR doesn't have a valid PASID. */
> > > + wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID);
How much more expensive is the wrmsr over the rdmsr? Can't we just
unconditionally write the current PASID and call it a day?
next prev parent reply other threads:[~2020-06-15 16:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-13 0:41 [PATCH v2 00/12] x86: tag application address space for devices Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 01/12] iommu: Change type of pasid to unsigned int Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 02/12] ocxl: " Fenghua Yu
2020-06-18 8:05 ` Frederic Barrat
2020-06-18 15:37 ` Fenghua Yu
2020-06-18 16:56 ` Frederic Barrat
2020-06-13 0:41 ` [PATCH v2 03/12] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 04/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2020-06-13 12:17 ` Lu Baolu
2020-06-15 23:16 ` Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 05/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 06/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 07/12] x86/msr-index: Define IA32_PASID MSR Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 08/12] mm: Define pasid in mm Fenghua Yu
2020-06-16 8:28 ` Jean-Philippe Brucker
2020-06-16 15:11 ` Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 09/12] fork: Clear PASID for new mm Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 10/12] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu
2020-06-13 0:41 ` [PATCH v2 11/12] x86/mmu: Allocate/free PASID Fenghua Yu
2020-06-13 13:07 ` Lu Baolu
2020-06-15 2:13 ` Lu Baolu
2020-06-13 0:41 ` [PATCH v2 12/12] x86/traps: Fix up invalid PASID Fenghua Yu
2020-06-15 7:53 ` Peter Zijlstra
2020-06-15 7:56 ` Peter Zijlstra
2020-06-15 15:48 ` Fenghua Yu
2020-06-15 16:03 ` Peter Zijlstra [this message]
2020-06-15 17:11 ` Luck, Tony
2020-06-15 18:12 ` Fenghua Yu
2020-06-15 18:31 ` Peter Zijlstra
2020-06-15 18:55 ` Fenghua Yu
2020-06-15 19:09 ` Peter Zijlstra
2020-06-15 20:17 ` Fenghua Yu
2020-06-15 20:51 ` Andy Lutomirski
2020-06-15 20:56 ` Luck, Tony
2020-06-15 21:18 ` Andy Lutomirski
2020-06-15 21:24 ` Luck, Tony
2020-06-15 21:53 ` Peter Zijlstra
2020-06-16 23:23 ` Fenghua Yu
2020-06-17 8:31 ` Peter Zijlstra
2020-06-15 18:19 ` Raj, Ashok
2020-06-15 18:32 ` Peter Zijlstra
2020-06-15 7:52 ` [PATCH v2 00/12] x86: tag application address space for devices Peter Zijlstra
2020-06-15 14:53 ` Fenghua Yu
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