[PATCH v2 00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling

[PATCH v2 00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling

[Bjorn Andersson]

The SC8280XP currently shows depressing results in memory benchmarks.
Fix this by introducing support for the platform in the OSM (and EPSS)
L3 driver and support for the platform in the bwmon binding.

Then add the necessary nodes and values throughout the sc8280xp and
sa8540p dtsi files to make the various devices on these platforms scale
both L3, memory bus and DDR.

Bjorn Andersson (10):
  interconnect: qcom: osm-l3: Use platform-independent node ids
  interconnect: qcom: osm-l3: Squash common descriptors
  interconnect: qcom: osm-l3: Add per-core EPSS L3 support
  interconnect: qcom: osm-l3: Simplify osm_l3_set()
  dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3
    compatibles
  arm64: dts: qcom: Align with generic osm-l3/epss-l3
  arm64: dts: qcom: sc8280xp: Add epss_l3 node
  arm64: dts: qcom: sc8280xp: Set up L3 scaling
  dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon
    instances
  arm64: dts: qcom: sc8280xp: Add bwmon instances

 .../interconnect/qcom,msm8998-bwmon.yaml      |   5 +
 .../bindings/interconnect/qcom,osm-l3.yaml    |  24 ++-
 arch/arm64/boot/dts/qcom/sa8540p.dtsi         |  39 +++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi          |   2 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi          |   2 +-
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        | 152 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |   2 +-
 arch/arm64/boot/dts/qcom/sm8150.dtsi          |   2 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |   2 +-
 drivers/interconnect/qcom/osm-l3.c            | 126 ++++-----------
 10 files changed, 252 insertions(+), 104 deletions(-)

-- 
2.17.1

[PATCH v2 01/10] interconnect: qcom: osm-l3: Use platform-independent node ids

[Bjorn Andersson]

The identifiers used for nodes needs to be unique in the running system,
but defining them per platform results in a lot of duplicated
definitions and prevents us from using generic compatibles.

As these identifiers are not exposed outside the kernel, change to use
driver-local numbers, picked completely at random.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 drivers/interconnect/qcom/osm-l3.c | 87 +++++++++++-------------------
 1 file changed, 30 insertions(+), 57 deletions(-)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index ddbdf0943f94..d23769844419 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -74,6 +74,11 @@ struct qcom_osm_l3_desc {
 	unsigned int reg_perf_state;
 };
 
+enum {
+	OSM_L3_MASTER_NODE = 10000,
+	OSM_L3_SLAVE_NODE,
+};
+
 #define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
 	static const struct qcom_osm_l3_node _name = {			\
 		.name = #_name,						\
@@ -83,97 +88,65 @@ struct qcom_osm_l3_desc {
 		.links = { __VA_ARGS__ },				\
 	}
 
-DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
-DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
+DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE);
+DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16);
+
+static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
+	[MASTER_OSM_L3_APPS] = &osm_l3_master,
+	[SLAVE_OSM_L3] = &osm_l3_slave,
+};
+
+DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE);
+DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32);
 
-static const struct qcom_osm_l3_node * const sdm845_osm_l3_nodes[] = {
-	[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
-	[SLAVE_OSM_L3] = &sdm845_osm_l3,
+static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
+	[MASTER_EPSS_L3_APPS] = &epss_l3_master,
+	[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
 };
 
 static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
-	.nodes = sdm845_osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
+	.nodes = osm_l3_nodes,
+	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
 	.lut_row_size = OSM_LUT_ROW_SIZE,
 	.reg_freq_lut = OSM_REG_FREQ_LUT,
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
-DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
-
-static const struct qcom_osm_l3_node * const sc7180_osm_l3_nodes[] = {
-	[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
-	[SLAVE_OSM_L3] = &sc7180_osm_l3,
-};
-
 static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
-	.nodes = sc7180_osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
+	.nodes = osm_l3_nodes,
+	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
 	.lut_row_size = OSM_LUT_ROW_SIZE,
 	.reg_freq_lut = OSM_REG_FREQ_LUT,
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
-DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
-
-static const struct qcom_osm_l3_node * const sc7280_epss_l3_nodes[] = {
-	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
-	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
-};
-
 static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
-	.nodes = sc7280_epss_l3_nodes,
-	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+	.nodes = epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
 	.lut_row_size = EPSS_LUT_ROW_SIZE,
 	.reg_freq_lut = EPSS_REG_FREQ_LUT,
 	.reg_perf_state = EPSS_REG_PERF_STATE,
 };
 
-DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
-DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
-
-static const struct qcom_osm_l3_node * const sc8180x_osm_l3_nodes[] = {
-	[MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3,
-	[SLAVE_OSM_L3] = &sc8180x_osm_l3,
-};
-
 static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
-	.nodes = sc8180x_osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(sc8180x_osm_l3_nodes),
+	.nodes = osm_l3_nodes,
+	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
 	.lut_row_size = OSM_LUT_ROW_SIZE,
 	.reg_freq_lut = OSM_REG_FREQ_LUT,
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
-DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
-
-static const struct qcom_osm_l3_node * const sm8150_osm_l3_nodes[] = {
-	[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
-	[SLAVE_OSM_L3] = &sm8150_osm_l3,
-};
-
 static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
-	.nodes = sm8150_osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
+	.nodes = osm_l3_nodes,
+	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
 	.lut_row_size = OSM_LUT_ROW_SIZE,
 	.reg_freq_lut = OSM_REG_FREQ_LUT,
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
-DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
-
-static const struct qcom_osm_l3_node * const sm8250_epss_l3_nodes[] = {
-	[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
-	[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
-};
-
 static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
-	.nodes = sm8250_epss_l3_nodes,
-	.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
+	.nodes = epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
 	.lut_row_size = EPSS_LUT_ROW_SIZE,
 	.reg_freq_lut = EPSS_REG_FREQ_LUT,
 	.reg_perf_state = EPSS_REG_PERF_STATE,
-- 
2.17.1

Re: [PATCH v2 01/10] interconnect: qcom: osm-l3: Use platform-independent node ids

[Sibi Sankar]

Hey Bjorn
Thanks for the patch.

On 11/11/22 08:55, Bjorn Andersson wrote:
> The identifiers used for nodes needs to be unique in the running system,
> but defining them per platform results in a lot of duplicated
> definitions and prevents us from using generic compatibles.
> 
> As these identifiers are not exposed outside the kernel, change to use
> driver-local numbers, picked completely at random.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

With the change in implementation, you can remove now remove the per soc
node id headers included in the driver. With ^^ done.

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   drivers/interconnect/qcom/osm-l3.c | 87 +++++++++++-------------------
>   1 file changed, 30 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index ddbdf0943f94..d23769844419 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -74,6 +74,11 @@ struct qcom_osm_l3_desc {
>   	unsigned int reg_perf_state;
>   };
>   
> +enum {
> +	OSM_L3_MASTER_NODE = 10000,
> +	OSM_L3_SLAVE_NODE,
> +};
> +
>   #define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
>   	static const struct qcom_osm_l3_node _name = {			\
>   		.name = #_name,						\
> @@ -83,97 +88,65 @@ struct qcom_osm_l3_desc {
>   		.links = { __VA_ARGS__ },				\
>   	}
>   
> -DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
> -DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
> +DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE);
> +DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16);
> +
> +static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
> +	[MASTER_OSM_L3_APPS] = &osm_l3_master,
> +	[SLAVE_OSM_L3] = &osm_l3_slave,
> +};
> +
> +DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE);
> +DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32);
>   
> -static const struct qcom_osm_l3_node * const sdm845_osm_l3_nodes[] = {
> -	[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
> -	[SLAVE_OSM_L3] = &sdm845_osm_l3,
> +static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
> +	[MASTER_EPSS_L3_APPS] = &epss_l3_master,
> +	[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
>   };
>   
>   static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
> -	.nodes = sdm845_osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
> +	.nodes = osm_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
>   	.lut_row_size = OSM_LUT_ROW_SIZE,
>   	.reg_freq_lut = OSM_REG_FREQ_LUT,
>   	.reg_perf_state = OSM_REG_PERF_STATE,
>   };
>   
> -DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
> -DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
> -
> -static const struct qcom_osm_l3_node * const sc7180_osm_l3_nodes[] = {
> -	[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
> -	[SLAVE_OSM_L3] = &sc7180_osm_l3,
> -};
> -
>   static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
> -	.nodes = sc7180_osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
> +	.nodes = osm_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
>   	.lut_row_size = OSM_LUT_ROW_SIZE,
>   	.reg_freq_lut = OSM_REG_FREQ_LUT,
>   	.reg_perf_state = OSM_REG_PERF_STATE,
>   };
>   
> -DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
> -DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
> -
> -static const struct qcom_osm_l3_node * const sc7280_epss_l3_nodes[] = {
> -	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
> -	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
> -};
> -
>   static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
> -	.nodes = sc7280_epss_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
> +	.nodes = epss_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
>   	.lut_row_size = EPSS_LUT_ROW_SIZE,
>   	.reg_freq_lut = EPSS_REG_FREQ_LUT,
>   	.reg_perf_state = EPSS_REG_PERF_STATE,
>   };
>   
> -DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
> -DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
> -
> -static const struct qcom_osm_l3_node * const sc8180x_osm_l3_nodes[] = {
> -	[MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3,
> -	[SLAVE_OSM_L3] = &sc8180x_osm_l3,
> -};
> -
>   static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
> -	.nodes = sc8180x_osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(sc8180x_osm_l3_nodes),
> +	.nodes = osm_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
>   	.lut_row_size = OSM_LUT_ROW_SIZE,
>   	.reg_freq_lut = OSM_REG_FREQ_LUT,
>   	.reg_perf_state = OSM_REG_PERF_STATE,
>   };
>   
> -DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
> -DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
> -
> -static const struct qcom_osm_l3_node * const sm8150_osm_l3_nodes[] = {
> -	[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
> -	[SLAVE_OSM_L3] = &sm8150_osm_l3,
> -};
> -
>   static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
> -	.nodes = sm8150_osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
> +	.nodes = osm_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
>   	.lut_row_size = OSM_LUT_ROW_SIZE,
>   	.reg_freq_lut = OSM_REG_FREQ_LUT,
>   	.reg_perf_state = OSM_REG_PERF_STATE,
>   };
>   
> -DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
> -DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
> -
> -static const struct qcom_osm_l3_node * const sm8250_epss_l3_nodes[] = {
> -	[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
> -	[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
> -};
> -
>   static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
> -	.nodes = sm8250_epss_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
> +	.nodes = epss_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
>   	.lut_row_size = EPSS_LUT_ROW_SIZE,
>   	.reg_freq_lut = EPSS_REG_FREQ_LUT,
>   	.reg_perf_state = EPSS_REG_PERF_STATE,

[PATCH v2 02/10] interconnect: qcom: osm-l3: Squash common descriptors

[Bjorn Andersson]

Each platform defines their own OSM L3 descriptor, but in practice
there's only two: one for OSM and one for EPSS. Remove the duplicated
definitions.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 drivers/interconnect/qcom/osm-l3.c | 48 +++++-------------------------
 1 file changed, 8 insertions(+), 40 deletions(-)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index d23769844419..7d6844253241 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -104,7 +104,7 @@ static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
 	[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
 };
 
-static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
+static const struct qcom_osm_l3_desc osm_l3 = {
 	.nodes = osm_l3_nodes,
 	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
 	.lut_row_size = OSM_LUT_ROW_SIZE,
@@ -112,39 +112,7 @@ static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
-	.nodes = osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
-	.lut_row_size = OSM_LUT_ROW_SIZE,
-	.reg_freq_lut = OSM_REG_FREQ_LUT,
-	.reg_perf_state = OSM_REG_PERF_STATE,
-};
-
-static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
-	.nodes = epss_l3_nodes,
-	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
-	.lut_row_size = EPSS_LUT_ROW_SIZE,
-	.reg_freq_lut = EPSS_REG_FREQ_LUT,
-	.reg_perf_state = EPSS_REG_PERF_STATE,
-};
-
-static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
-	.nodes = osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
-	.lut_row_size = OSM_LUT_ROW_SIZE,
-	.reg_freq_lut = OSM_REG_FREQ_LUT,
-	.reg_perf_state = OSM_REG_PERF_STATE,
-};
-
-static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
-	.nodes = osm_l3_nodes,
-	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
-	.lut_row_size = OSM_LUT_ROW_SIZE,
-	.reg_freq_lut = OSM_REG_FREQ_LUT,
-	.reg_perf_state = OSM_REG_PERF_STATE,
-};
-
-static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
+static const struct qcom_osm_l3_desc epss_l3 = {
 	.nodes = epss_l3_nodes,
 	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
 	.lut_row_size = EPSS_LUT_ROW_SIZE,
@@ -317,12 +285,12 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id osm_l3_of_match[] = {
-	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
-	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
-	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
-	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
-	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
-	{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
+	{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 },
+	{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
+	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
+	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
+	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, osm_l3_of_match);
-- 
2.17.1

Re: [PATCH v2 02/10] interconnect: qcom: osm-l3: Squash common descriptors

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> Each platform defines their own OSM L3 descriptor, but in practice
> there's only two: one for OSM and one for EPSS. Remove the duplicated
> definitions.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   drivers/interconnect/qcom/osm-l3.c | 48 +++++-------------------------
>   1 file changed, 8 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index d23769844419..7d6844253241 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -104,7 +104,7 @@ static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
>   	[SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
>   };
>   
> -static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
> +static const struct qcom_osm_l3_desc osm_l3 = {
>   	.nodes = osm_l3_nodes,
>   	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
>   	.lut_row_size = OSM_LUT_ROW_SIZE,
> @@ -112,39 +112,7 @@ static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = {
>   	.reg_perf_state = OSM_REG_PERF_STATE,
>   };
>   
> -static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
> -	.nodes = osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
> -	.lut_row_size = OSM_LUT_ROW_SIZE,
> -	.reg_freq_lut = OSM_REG_FREQ_LUT,
> -	.reg_perf_state = OSM_REG_PERF_STATE,
> -};
> -
> -static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
> -	.nodes = epss_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
> -	.lut_row_size = EPSS_LUT_ROW_SIZE,
> -	.reg_freq_lut = EPSS_REG_FREQ_LUT,
> -	.reg_perf_state = EPSS_REG_PERF_STATE,
> -};
> -
> -static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = {
> -	.nodes = osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
> -	.lut_row_size = OSM_LUT_ROW_SIZE,
> -	.reg_freq_lut = OSM_REG_FREQ_LUT,
> -	.reg_perf_state = OSM_REG_PERF_STATE,
> -};
> -
> -static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = {
> -	.nodes = osm_l3_nodes,
> -	.num_nodes = ARRAY_SIZE(osm_l3_nodes),
> -	.lut_row_size = OSM_LUT_ROW_SIZE,
> -	.reg_freq_lut = OSM_REG_FREQ_LUT,
> -	.reg_perf_state = OSM_REG_PERF_STATE,
> -};
> -
> -static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = {
> +static const struct qcom_osm_l3_desc epss_l3 = {
>   	.nodes = epss_l3_nodes,
>   	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
>   	.lut_row_size = EPSS_LUT_ROW_SIZE,
> @@ -317,12 +285,12 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>   }
>   
>   static const struct of_device_id osm_l3_of_match[] = {
> -	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
> -	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
> -	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
> -	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
> -	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
> -	{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
> +	{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
> +	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 },
> +	{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
> +	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
> +	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
> +	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 },
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, osm_l3_of_match);

[PATCH v2 03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support

[Bjorn Andersson]

The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting
enabled. In this configuration, the "shared" vote is done using the
REG_L3_VOTE register instead of PERF_STATE.

Rename epss_l3 to clarify that it's affecting the PERF_STATE register
and add a new L3_VOTE description. Given platform lineage it's assumed
that the L3_VOTE-based case will be the predominant one, so use this for
a new generic qcom,epss-l3 compatible.

While adding the EPSS generic, also add qcom,osm-l3.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 drivers/interconnect/qcom/osm-l3.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 7d6844253241..469be732a00b 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -34,6 +34,7 @@
 
 /* EPSS Register offsets */
 #define EPSS_LUT_ROW_SIZE		4
+#define EPSS_REG_L3_VOTE		0x90
 #define EPSS_REG_FREQ_LUT		0x100
 #define EPSS_REG_PERF_STATE		0x320
 
@@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = {
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
-static const struct qcom_osm_l3_desc epss_l3 = {
+static const struct qcom_osm_l3_desc epss_l3_perf_state = {
 	.nodes = epss_l3_nodes,
 	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
 	.lut_row_size = EPSS_LUT_ROW_SIZE,
@@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = {
 	.reg_perf_state = EPSS_REG_PERF_STATE,
 };
 
+static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
+	.nodes = epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
+	.lut_row_size = EPSS_LUT_ROW_SIZE,
+	.reg_freq_lut = EPSS_REG_FREQ_LUT,
+	.reg_perf_state = EPSS_REG_L3_VOTE,
+};
+
 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct qcom_osm_l3_icc_provider *qp;
@@ -285,12 +294,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id osm_l3_of_match[] = {
+	{ .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
+	{ .compatible = "qcom,osm-l3", .data = &osm_l3 },
 	{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
-	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
 	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
 	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
-	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 },
+	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, osm_l3_of_match);
-- 
2.17.1

Re: [PATCH v2 03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting
> enabled. In this configuration, the "shared" vote is done using the
> REG_L3_VOTE register instead of PERF_STATE.
> 
> Rename epss_l3 to clarify that it's affecting the PERF_STATE register
> and add a new L3_VOTE description. Given platform lineage it's assumed
> that the L3_VOTE-based case will be the predominant one, so use this for
> a new generic qcom,epss-l3 compatible.
> 
> While adding the EPSS generic, also add qcom,osm-l3.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   drivers/interconnect/qcom/osm-l3.c | 17 ++++++++++++++---
>   1 file changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index 7d6844253241..469be732a00b 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -34,6 +34,7 @@
>   
>   /* EPSS Register offsets */
>   #define EPSS_LUT_ROW_SIZE		4
> +#define EPSS_REG_L3_VOTE		0x90
>   #define EPSS_REG_FREQ_LUT		0x100
>   #define EPSS_REG_PERF_STATE		0x320
>   
> @@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = {
>   	.reg_perf_state = OSM_REG_PERF_STATE,
>   };
>   
> -static const struct qcom_osm_l3_desc epss_l3 = {
> +static const struct qcom_osm_l3_desc epss_l3_perf_state = {
>   	.nodes = epss_l3_nodes,
>   	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
>   	.lut_row_size = EPSS_LUT_ROW_SIZE,
> @@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = {
>   	.reg_perf_state = EPSS_REG_PERF_STATE,
>   };
>   
> +static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
> +	.nodes = epss_l3_nodes,
> +	.num_nodes = ARRAY_SIZE(epss_l3_nodes),
> +	.lut_row_size = EPSS_LUT_ROW_SIZE,
> +	.reg_freq_lut = EPSS_REG_FREQ_LUT,
> +	.reg_perf_state = EPSS_REG_L3_VOTE,
> +};
> +
>   static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
>   {
>   	struct qcom_osm_l3_icc_provider *qp;
> @@ -285,12 +294,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>   }
>   
>   static const struct of_device_id osm_l3_of_match[] = {
> +	{ .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
> +	{ .compatible = "qcom,osm-l3", .data = &osm_l3 },
>   	{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
> -	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 },
> +	{ .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
>   	{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
>   	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
>   	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
> -	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 },
> +	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, osm_l3_of_match);

[PATCH v2 04/10] interconnect: qcom: osm-l3: Simplify osm_l3_set()

[Bjorn Andersson]

The aggregation over votes for all nodes in the provider will always
only find the bandwidth votes for the destination side of the path.
Further more, the average kBps value will always be 0.

Simplify the logic by directly looking at the destination node's peak
bandwidth request.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 drivers/interconnect/qcom/osm-l3.c | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 469be732a00b..5fa171087425 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -134,22 +134,14 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 	struct qcom_osm_l3_icc_provider *qp;
 	struct icc_provider *provider;
 	const struct qcom_osm_l3_node *qn;
-	struct icc_node *n;
 	unsigned int index;
-	u32 agg_peak = 0;
-	u32 agg_avg = 0;
 	u64 rate;
 
 	qn = src->data;
 	provider = src->provider;
 	qp = to_osm_l3_provider(provider);
 
-	list_for_each_entry(n, &provider->nodes, node_list)
-		provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
-				    &agg_avg, &agg_peak);
-
-	rate = max(agg_avg, agg_peak);
-	rate = icc_units_to_bps(rate);
+	rate = icc_units_to_bps(dst->peak_bw);
 	do_div(rate, qn->buswidth);
 
 	for (index = 0; index < qp->max_state - 1; index++) {
-- 
2.17.1

Re: [PATCH v2 04/10] interconnect: qcom: osm-l3: Simplify osm_l3_set()

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> The aggregation over votes for all nodes in the provider will always
> only find the bandwidth votes for the destination side of the path.
> Further more, the average kBps value will always be 0.
> 
> Simplify the logic by directly looking at the destination node's peak
> bandwidth request.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   drivers/interconnect/qcom/osm-l3.c | 10 +---------
>   1 file changed, 1 insertion(+), 9 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index 469be732a00b..5fa171087425 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -134,22 +134,14 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
>   	struct qcom_osm_l3_icc_provider *qp;
>   	struct icc_provider *provider;
>   	const struct qcom_osm_l3_node *qn;
> -	struct icc_node *n;
>   	unsigned int index;
> -	u32 agg_peak = 0;
> -	u32 agg_avg = 0;
>   	u64 rate;
>   
>   	qn = src->data;
>   	provider = src->provider;
>   	qp = to_osm_l3_provider(provider);
>   
> -	list_for_each_entry(n, &provider->nodes, node_list)
> -		provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
> -				    &agg_avg, &agg_peak);
> -
> -	rate = max(agg_avg, agg_peak);
> -	rate = icc_units_to_bps(rate);
> +	rate = icc_units_to_bps(dst->peak_bw);
>   	do_div(rate, qn->buswidth);
>   
>   	for (index = 0; index < qp->max_state - 1; index++) {

[PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles

[Bjorn Andersson]

Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- Fixed oneOf to be valid schema
- Fixed example to follow schema

 .../bindings/interconnect/qcom,osm-l3.yaml    | 24 ++++++++++++-------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index bf538c0c5a81..aadae4424ba9 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -16,13 +16,21 @@ description:
 
 properties:
   compatible:
-    enum:
-      - qcom,sc7180-osm-l3
-      - qcom,sc7280-epss-l3
-      - qcom,sc8180x-osm-l3
-      - qcom,sdm845-osm-l3
-      - qcom,sm8150-osm-l3
-      - qcom,sm8250-epss-l3
+    oneOf:
+      - items:
+          - enum:
+              - qcom,sc7180-osm-l3
+              - qcom,sc8180x-osm-l3
+              - qcom,sdm845-osm-l3
+              - qcom,sm8150-osm-l3
+          - const: qcom,osm-l3
+      - items:
+          - enum:
+              - qcom,sc7280-epss-l3
+              - qcom,sc8280xp-epss-l3
+              - qcom,sm8250-epss-l3
+              - qcom,sm8350-epss-l3
+          - const: qcom,epss-l3
 
   reg:
     maxItems: 1
@@ -56,7 +64,7 @@ examples:
     #define RPMH_CXO_CLK        0
 
     osm_l3: interconnect@17d41000 {
-      compatible = "qcom,sdm845-osm-l3";
+      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
       reg = <0x17d41000 0x1400>;
 
       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
-- 
2.17.1

Re: [PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles

[Krzysztof Kozlowski]

On 11/11/2022 04:25, Bjorn Andersson wrote:
> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>
> ---
> 
> Changes since v1:
> - Fixed oneOf to be valid schema
> - Fixed example to follow schema
> 
>   .../bindings/interconnect/qcom,osm-l3.yaml    | 24 ++++++++++++-------
>   1 file changed, 16 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index bf538c0c5a81..aadae4424ba9 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -16,13 +16,21 @@ description:
>   
>   properties:
>     compatible:
> -    enum:
> -      - qcom,sc7180-osm-l3
> -      - qcom,sc7280-epss-l3
> -      - qcom,sc8180x-osm-l3
> -      - qcom,sdm845-osm-l3
> -      - qcom,sm8150-osm-l3
> -      - qcom,sm8250-epss-l3
> +    oneOf:
> +      - items:
> +          - enum:
> +              - qcom,sc7180-osm-l3
> +              - qcom,sc8180x-osm-l3
> +              - qcom,sdm845-osm-l3
> +              - qcom,sm8150-osm-l3
> +          - const: qcom,osm-l3
> +      - items:
> +          - enum:
> +              - qcom,sc7280-epss-l3
> +              - qcom,sc8280xp-epss-l3
> +              - qcom,sm8250-epss-l3
> +              - qcom,sm8350-epss-l3
> +          - const: qcom,epss-l3

isn't it incorrect to describe qcom,epss-l3 as a working
backup compatible for sc7280-epss-l3 and sm8250-epss-l3?
Shouldn't we just add another items list with those 2 as
enums?

>   
>     reg:
>       maxItems: 1
> @@ -56,7 +64,7 @@ examples:
>       #define RPMH_CXO_CLK        0
>   
>       osm_l3: interconnect@17d41000 {
> -      compatible = "qcom,sdm845-osm-l3";
> +      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
>         reg = <0x17d41000 0x1400>;
>   
>         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

Re: [PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles

[Bjorn Andersson]

On Fri, Nov 11, 2022 at 04:02:42PM +0530, Sibi Sankar wrote:
> 
> 
> On 11/11/22 08:55, Bjorn Andersson wrote:
> > Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
> > introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
> > 
> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> > Tested-by: Steev Klimaszewski <steev@kali.org>
> > ---
> > 
> > Changes since v1:
> > - Fixed oneOf to be valid schema
> > - Fixed example to follow schema
> > 
> >   .../bindings/interconnect/qcom,osm-l3.yaml    | 24 ++++++++++++-------
> >   1 file changed, 16 insertions(+), 8 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> > index bf538c0c5a81..aadae4424ba9 100644
> > --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> > +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> > @@ -16,13 +16,21 @@ description:
> >   properties:
> >     compatible:
> > -    enum:
> > -      - qcom,sc7180-osm-l3
> > -      - qcom,sc7280-epss-l3
> > -      - qcom,sc8180x-osm-l3
> > -      - qcom,sdm845-osm-l3
> > -      - qcom,sm8150-osm-l3
> > -      - qcom,sm8250-epss-l3
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - qcom,sc7180-osm-l3
> > +              - qcom,sc8180x-osm-l3
> > +              - qcom,sdm845-osm-l3
> > +              - qcom,sm8150-osm-l3
> > +          - const: qcom,osm-l3
> > +      - items:
> > +          - enum:
> > +              - qcom,sc7280-epss-l3
> > +              - qcom,sc8280xp-epss-l3
> > +              - qcom,sm8250-epss-l3
> > +              - qcom,sm8350-epss-l3
> > +          - const: qcom,epss-l3
> 
> isn't it incorrect to describe qcom,epss-l3 as a working
> backup compatible for sc7280-epss-l3 and sm8250-epss-l3?
> Shouldn't we just add another items list with those 2 as
> enums?
> 

I was about to agree, but the difference between the two sets are which
registers we use to request the speed.

And per our recent discussion, I was under the impression that this
would be a property of BIT(0) in 0xb0 being set, not which platform
we're running on.

If that's the case then they are indeed compatible and we should adjust
.ref_perf_state based on per-core DCVS being set or not.


So I do think this description is appropriate...

Regards,
Bjorn

> >     reg:
> >       maxItems: 1
> > @@ -56,7 +64,7 @@ examples:
> >       #define RPMH_CXO_CLK        0
> >       osm_l3: interconnect@17d41000 {
> > -      compatible = "qcom,sdm845-osm-l3";
> > +      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
> >         reg = <0x17d41000 0x1400>;
> >         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

Re: [PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles

[Sibi Sankar]

On 11/11/22 23:38, Bjorn Andersson wrote:
> On Fri, Nov 11, 2022 at 04:02:42PM +0530, Sibi Sankar wrote:
>>
>>
>> On 11/11/22 08:55, Bjorn Andersson wrote:
>>> Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also
>>> introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3.
>>>
>>> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
>>> Tested-by: Steev Klimaszewski <steev@kali.org>
>>> ---
>>>
>>> Changes since v1:
>>> - Fixed oneOf to be valid schema
>>> - Fixed example to follow schema
>>>
>>>    .../bindings/interconnect/qcom,osm-l3.yaml    | 24 ++++++++++++-------
>>>    1 file changed, 16 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>>> index bf538c0c5a81..aadae4424ba9 100644
>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>>> @@ -16,13 +16,21 @@ description:
>>>    properties:
>>>      compatible:
>>> -    enum:
>>> -      - qcom,sc7180-osm-l3
>>> -      - qcom,sc7280-epss-l3
>>> -      - qcom,sc8180x-osm-l3
>>> -      - qcom,sdm845-osm-l3
>>> -      - qcom,sm8150-osm-l3
>>> -      - qcom,sm8250-epss-l3
>>> +    oneOf:
>>> +      - items:
>>> +          - enum:
>>> +              - qcom,sc7180-osm-l3
>>> +              - qcom,sc8180x-osm-l3
>>> +              - qcom,sdm845-osm-l3
>>> +              - qcom,sm8150-osm-l3
>>> +          - const: qcom,osm-l3
>>> +      - items:
>>> +          - enum:
>>> +              - qcom,sc7280-epss-l3
>>> +              - qcom,sc8280xp-epss-l3
>>> +              - qcom,sm8250-epss-l3
>>> +              - qcom,sm8350-epss-l3
>>> +          - const: qcom,epss-l3
>>
>> isn't it incorrect to describe qcom,epss-l3 as a working
>> backup compatible for sc7280-epss-l3 and sm8250-epss-l3?
>> Shouldn't we just add another items list with those 2 as
>> enums?
>>
> 
> I was about to agree, but the difference between the two sets are which
> registers we use to request the speed.
> 
> And per our recent discussion, I was under the impression that this
> would be a property of BIT(0) in 0xb0 being set, not which platform
> we're running on.
> 
> If that's the case then they are indeed compatible and we should adjust
> .ref_perf_state based on per-core DCVS being set or not.
> 
> 
> So I do think this description is appropriate...

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> 
> Regards,
> Bjorn
> 
>>>      reg:
>>>        maxItems: 1
>>> @@ -56,7 +64,7 @@ examples:
>>>        #define RPMH_CXO_CLK        0
>>>        osm_l3: interconnect@17d41000 {
>>> -      compatible = "qcom,sdm845-osm-l3";
>>> +      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
>>>          reg = <0x17d41000 0x1400>;
>>>          clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

[PATCH v2 06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3

[Bjorn Andersson]

Update all references to OSM or EPSS L3 compatibles, to include the
generic compatible, as defined by the updated binding.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ea886cf08b4d..f71cf21a8dd8 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3558,7 +3558,7 @@
 		};
 
 		osm_l3: interconnect@18321000 {
-			compatible = "qcom,sc7180-osm-l3";
+			compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
 			reg = <0 0x18321000 0 0x1400>;
 
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 07334e19be99..ad9c61768016 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5359,7 +5359,7 @@
 		};
 
 		epss_l3: interconnect@18590000 {
-			compatible = "qcom,sc7280-epss-l3";
+			compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
 			reg = <0 0x18590000 0 0x1000>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
 			clock-names = "xo", "alternate";
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1a257f672887..9c7d484ce72f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5302,7 +5302,7 @@
 		};
 
 		osm_l3: interconnect@17d41000 {
-			compatible = "qcom,sdm845-osm-l3";
+			compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
 			reg = <0 0x17d41000 0 0x1400>;
 
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 18bf51ce8b13..8409fb5ea532 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3958,7 +3958,7 @@
 		};
 
 		osm_l3: interconnect@18321000 {
-			compatible = "qcom,sm8150-osm-l3";
+			compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
 			reg = <0 0x18321000 0 0x1400>;
 
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 27b507f3632b..351c232b8dc6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4884,7 +4884,7 @@
 		};
 
 		epss_l3: interconnect@18590000 {
-			compatible = "qcom,sm8250-epss-l3";
+			compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
 			reg = <0 0x18590000 0 0x1000>;
 
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
-- 
2.17.1

Re: [PATCH v2 06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> Update all references to OSM or EPSS L3 compatibles, to include the
> generic compatible, as defined by the updated binding.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>
> ---
> 
> Changes since v1:
> - None
> 
>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
>   arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
>   arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
>   5 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index ea886cf08b4d..f71cf21a8dd8 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -3558,7 +3558,7 @@
>   		};
>   
>   		osm_l3: interconnect@18321000 {
> -			compatible = "qcom,sc7180-osm-l3";
> +			compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
>   			reg = <0 0x18321000 0 0x1400>;
>   
>   			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 07334e19be99..ad9c61768016 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -5359,7 +5359,7 @@
>   		};
>   
>   		epss_l3: interconnect@18590000 {
> -			compatible = "qcom,sc7280-epss-l3";
> +			compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
>   			reg = <0 0x18590000 0 0x1000>;
>   			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>   			clock-names = "xo", "alternate";
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 1a257f672887..9c7d484ce72f 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -5302,7 +5302,7 @@
>   		};
>   
>   		osm_l3: interconnect@17d41000 {
> -			compatible = "qcom,sdm845-osm-l3";
> +			compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
>   			reg = <0 0x17d41000 0 0x1400>;
>   
>   			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 18bf51ce8b13..8409fb5ea532 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -3958,7 +3958,7 @@
>   		};
>   
>   		osm_l3: interconnect@18321000 {
> -			compatible = "qcom,sm8150-osm-l3";
> +			compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
>   			reg = <0 0x18321000 0 0x1400>;
>   
>   			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 27b507f3632b..351c232b8dc6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -4884,7 +4884,7 @@
>   		};
>   
>   		epss_l3: interconnect@18590000 {
> -			compatible = "qcom,sm8250-epss-l3";
> +			compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";

if we do change sc7280, sm8250 epss compatible in the bindings, you'll
no longer need to list the qcom,epss-l3 here. With ^^ done.

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>


>   			reg = <0 0x18590000 0 0x1000>;
>   
>   			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

[PATCH v2 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node

[Bjorn Andersson]

Add a device node for the EPSS L3 frequency domain.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 6bc12e507d21..0e80cdcf6bcf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1782,6 +1782,16 @@
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,
-- 
2.17.1

Re: [PATCH v2 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> Add a device node for the EPSS L3 frequency domain.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 6bc12e507d21..0e80cdcf6bcf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1782,6 +1782,16 @@
>   			};
>   		};
>   
> +		epss_l3: interconnect@18590000 {
> +			compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
> +			reg = <0 0x18590000 0 0x1000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +
> +			#interconnect-cells = <1>;
> +		};
> +
>   		cpufreq_hw: cpufreq@18591000 {
>   			compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
>   			reg = <0 0x18591000 0 0x1000>,

[PATCH v2 08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling

[Bjorn Andersson]

Add the L3 interconnect path to all CPUs and define the bandwidth
requirements for all opp entries across sc8280xp and sa8540p.

The values are based on the tables reported by the hardware, distributed
such that each value is the largest value, lower than the cluster
frequency.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- None

 arch/arm64/boot/dts/qcom/sa8540p.dtsi  | 39 ++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 51 ++++++++++++++++++++++++++
 2 files changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
index 8ea2886fbab2..fd36800a7578 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
@@ -14,59 +14,81 @@
 		compatible = "operating-points-v2";
 		opp-shared;
 
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-peak-kBps = <(300000 * 32)>;
+		};
 		opp-403200000 {
 			opp-hz = /bits/ 64 <403200000>;
+			opp-peak-kBps = <(384000 * 32)>;
 		};
 		opp-499200000 {
 			opp-hz = /bits/ 64 <499200000>;
+			opp-peak-kBps = <(480000 * 32)>;
 		};
 		opp-595200000 {
 			opp-hz = /bits/ 64 <595200000>;
+			opp-peak-kBps = <(576000 * 32)>;
 		};
 		opp-710400000 {
 			opp-hz = /bits/ 64 <710400000>;
+			opp-peak-kBps = <(672000 * 32)>;
 		};
 		opp-806400000 {
 			opp-hz = /bits/ 64 <806400000>;
+			opp-peak-kBps = <(768000 * 32)>;
 		};
 		opp-902400000 {
 			opp-hz = /bits/ 64 <902400000>;
+			opp-peak-kBps = <(864000 * 32)>;
 		};
 		opp-1017600000 {
 			opp-hz = /bits/ 64 <1017600000>;
+			opp-peak-kBps = <(960000 * 32)>;
 		};
 		opp-1113600000 {
 			opp-hz = /bits/ 64 <1113600000>;
+			opp-peak-kBps = <(1075200 * 32)>;
 		};
 		opp-1209600000 {
 			opp-hz = /bits/ 64 <1209600000>;
+			opp-peak-kBps = <(1171200 * 32)>;
 		};
 		opp-1324800000 {
 			opp-hz = /bits/ 64 <1324800000>;
+			opp-peak-kBps = <(1286400 * 32)>;
 		};
 		opp-1440000000 {
 			opp-hz = /bits/ 64 <1440000000>;
+			opp-peak-kBps = <(1382400 * 32)>;
 		};
 		opp-1555200000 {
 			opp-hz = /bits/ 64 <1555200000>;
+			opp-peak-kBps = <(1497600 * 32)>;
 		};
 		opp-1670400000 {
 			opp-hz = /bits/ 64 <1670400000>;
+			opp-peak-kBps = <(1593600 * 32)>;
 		};
 		opp-1785600000 {
 			opp-hz = /bits/ 64 <1785600000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-1881600000 {
 			opp-hz = /bits/ 64 <1881600000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2016000000 {
 			opp-hz = /bits/ 64 <2016000000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2131200000 {
 			opp-hz = /bits/ 64 <2131200000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2246400000 {
 			opp-hz = /bits/ 64 <2246400000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 	};
 
@@ -76,54 +98,71 @@
 
 		opp-825600000 {
 			opp-hz = /bits/ 64 <825600000>;
+			opp-peak-kBps = <(300000 * 32)>;
 		};
 		opp-940800000 {
 			opp-hz = /bits/ 64 <940800000>;
+			opp-peak-kBps = <(864000 * 32)>;
 		};
 		opp-1056000000 {
 			opp-hz = /bits/ 64 <1056000000>;
+			opp-peak-kBps = <(960000 * 32)>;
 		};
 		opp-1171200000 {
 			opp-hz = /bits/ 64 <1171200000>;
+			opp-peak-kBps = <(1171200 * 32)>;
 		};
 		opp-1286400000 {
 			opp-hz = /bits/ 64 <1286400000>;
+			opp-peak-kBps = <(1286400 * 32)>;
 		};
 		opp-1401600000 {
 			opp-hz = /bits/ 64 <1401600000>;
+			opp-peak-kBps = <(1382400 * 32)>;
 		};
 		opp-1516800000 {
 			opp-hz = /bits/ 64 <1516800000>;
+			opp-peak-kBps = <(1497600 * 32)>;
 		};
 		opp-1632000000 {
 			opp-hz = /bits/ 64 <1632000000>;
+			opp-peak-kBps = <(1593600 * 32)>;
 		};
 		opp-1747200000 {
 			opp-hz = /bits/ 64 <1747200000>;
+			opp-peak-kBps = <(1593600 * 32)>;
 		};
 		opp-1862400000 {
 			opp-hz = /bits/ 64 <1862400000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-1977600000 {
 			opp-hz = /bits/ 64 <1977600000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2073600000 {
 			opp-hz = /bits/ 64 <2073600000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2169600000 {
 			opp-hz = /bits/ 64 <2169600000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2284800000 {
 			opp-hz = /bits/ 64 <2284800000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2380800000 {
 			opp-hz = /bits/ 64 <2380800000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2496000000 {
 			opp-hz = /bits/ 64 <2496000000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 		opp-2592000000 {
 			opp-hz = /bits/ 64 <2592000000>;
+			opp-peak-kBps = <(1708800 * 32)>;
 		};
 	};
 };
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0e80cdcf6bcf..2ac8f5204905 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -38,66 +39,87 @@
 
 		opp-300000000 {
 			opp-hz = /bits/ 64 <300000000>;
+			opp-peak-kBps = <(300000 * 32)>;
 		};
 		opp-403200000 {
 			opp-hz = /bits/ 64 <403200000>;
+			opp-peak-kBps = <(384000 * 32)>;
 		};
 		opp-499200000 {
 			opp-hz = /bits/ 64 <499200000>;
+			opp-peak-kBps = <(480000 * 32)>;
 		};
 		opp-595200000 {
 			opp-hz = /bits/ 64 <595200000>;
+			opp-peak-kBps = <(576000 * 32)>;
 		};
 		opp-691200000 {
 			opp-hz = /bits/ 64 <691200000>;
+			opp-peak-kBps = <(672000 * 32)>;
 		};
 		opp-806400000 {
 			opp-hz = /bits/ 64 <806400000>;
+			opp-peak-kBps = <(768000 * 32)>;
 		};
 		opp-902400000 {
 			opp-hz = /bits/ 64 <902400000>;
+			opp-peak-kBps = <(864000 * 32)>;
 		};
 		opp-1017600000 {
 			opp-hz = /bits/ 64 <1017600000>;
+			opp-peak-kBps = <(960000 * 32)>;
 		};
 		opp-1113600000 {
 			opp-hz = /bits/ 64 <1113600000>;
+			opp-peak-kBps = <(1075200 * 32)>;
 		};
 		opp-1209600000 {
 			opp-hz = /bits/ 64 <1209600000>;
+			opp-peak-kBps = <(1171200 * 32)>;
 		};
 		opp-1324800000 {
 			opp-hz = /bits/ 64 <1324800000>;
+			opp-peak-kBps = <(1267200 * 32)>;
 		};
 		opp-1440000000 {
 			opp-hz = /bits/ 64 <1440000000>;
+			opp-peak-kBps = <(1363200 * 32)>;
 		};
 		opp-1555200000 {
 			opp-hz = /bits/ 64 <1555200000>;
+			opp-peak-kBps = <(1536000 * 32)>;
 		};
 		opp-1670400000 {
 			opp-hz = /bits/ 64 <1670400000>;
+			opp-peak-kBps = <(1612800 * 32)>;
 		};
 		opp-1785600000 {
 			opp-hz = /bits/ 64 <1785600000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-1881600000 {
 			opp-hz = /bits/ 64 <1881600000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-1996800000 {
 			opp-hz = /bits/ 64 <1996800000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2112000000 {
 			opp-hz = /bits/ 64 <2112000000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2227200000 {
 			opp-hz = /bits/ 64 <2227200000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2342400000 {
 			opp-hz = /bits/ 64 <2342400000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2438400000 {
 			opp-hz = /bits/ 64 <2438400000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 	};
 
@@ -107,66 +129,87 @@
 
 		opp-825600000 {
 			opp-hz = /bits/ 64 <825600000>;
+			opp-peak-kBps = <(768000 * 32)>;
 		};
 		opp-940800000 {
 			opp-hz = /bits/ 64 <940800000>;
+			opp-peak-kBps = <(864000 * 32)>;
 		};
 		opp-1056000000 {
 			opp-hz = /bits/ 64 <1056000000>;
+			opp-peak-kBps = <(960000 * 32)>;
 		};
 		opp-1171200000 {
 			opp-hz = /bits/ 64 <1171200000>;
+			opp-peak-kBps = <(1171200 * 32)>;
 		};
 		opp-1286400000 {
 			opp-hz = /bits/ 64 <1286400000>;
+			opp-peak-kBps = <(1267200 * 32)>;
 		};
 		opp-1401600000 {
 			opp-hz = /bits/ 64 <1401600000>;
+			opp-peak-kBps = <(1363200 * 32)>;
 		};
 		opp-1516800000 {
 			opp-hz = /bits/ 64 <1516800000>;
+			opp-peak-kBps = <(1459200 * 32)>;
 		};
 		opp-1632000000 {
 			opp-hz = /bits/ 64 <1632000000>;
+			opp-peak-kBps = <(1612800 * 32)>;
 		};
 		opp-1747200000 {
 			opp-hz = /bits/ 64 <1747200000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-1862400000 {
 			opp-hz = /bits/ 64 <1862400000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-1977600000 {
 			opp-hz = /bits/ 64 <1977600000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2073600000 {
 			opp-hz = /bits/ 64 <2073600000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2169600000 {
 			opp-hz = /bits/ 64 <2169600000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2284800000 {
 			opp-hz = /bits/ 64 <2284800000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2400000000 {
 			opp-hz = /bits/ 64 <2400000000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2496000000 {
 			opp-hz = /bits/ 64 <2496000000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2592000000 {
 			opp-hz = /bits/ 64 <2592000000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2688000000 {
 			opp-hz = /bits/ 64 <2688000000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2803200000 {
 			opp-hz = /bits/ 64 <2803200000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2899200000 {
 			opp-hz = /bits/ 64 <2899200000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 		opp-2995200000 {
 			opp-hz = /bits/ 64 <2995200000>;
+			opp-peak-kBps = <(1689600 * 32)>;
 		};
 	};
 
@@ -185,6 +228,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_0: l2-cache {
 				compatible = "cache";
@@ -206,6 +250,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_100: l2-cache {
 				compatible = "cache";
@@ -224,6 +269,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_200: l2-cache {
 				compatible = "cache";
@@ -242,6 +288,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_300: l2-cache {
 				compatible = "cache";
@@ -260,6 +307,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_400: l2-cache {
 				compatible = "cache";
@@ -278,6 +326,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_500: l2-cache {
 				compatible = "cache";
@@ -296,6 +345,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_600: l2-cache {
 				compatible = "cache";
@@ -314,6 +364,7 @@
 			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			operating-points-v2 = <&cpu4_opp_table>;
+			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 			#cooling-cells = <2>;
 			L2_700: l2-cache {
 				compatible = "cache";
-- 
2.17.1

Re: [PATCH v2 08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> Add the L3 interconnect path to all CPUs and define the bandwidth
> requirements for all opp entries across sc8280xp and sa8540p.
> 
> The values are based on the tables reported by the hardware, distributed
> such that each value is the largest value, lower than the cluster
> frequency.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - None
> 
>   arch/arm64/boot/dts/qcom/sa8540p.dtsi  | 39 ++++++++++++++++++++
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 51 ++++++++++++++++++++++++++
>   2 files changed, 90 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
> index 8ea2886fbab2..fd36800a7578 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
> @@ -14,59 +14,81 @@
>   		compatible = "operating-points-v2";
>   		opp-shared;
>   
> +		opp-300000000 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-peak-kBps = <(300000 * 32)>;
> +		};
>   		opp-403200000 {
>   			opp-hz = /bits/ 64 <403200000>;
> +			opp-peak-kBps = <(384000 * 32)>;
>   		};
>   		opp-499200000 {
>   			opp-hz = /bits/ 64 <499200000>;
> +			opp-peak-kBps = <(480000 * 32)>;
>   		};
>   		opp-595200000 {
>   			opp-hz = /bits/ 64 <595200000>;
> +			opp-peak-kBps = <(576000 * 32)>;
>   		};
>   		opp-710400000 {
>   			opp-hz = /bits/ 64 <710400000>;
> +			opp-peak-kBps = <(672000 * 32)>;
>   		};
>   		opp-806400000 {
>   			opp-hz = /bits/ 64 <806400000>;
> +			opp-peak-kBps = <(768000 * 32)>;
>   		};
>   		opp-902400000 {
>   			opp-hz = /bits/ 64 <902400000>;
> +			opp-peak-kBps = <(864000 * 32)>;
>   		};
>   		opp-1017600000 {
>   			opp-hz = /bits/ 64 <1017600000>;
> +			opp-peak-kBps = <(960000 * 32)>;
>   		};
>   		opp-1113600000 {
>   			opp-hz = /bits/ 64 <1113600000>;
> +			opp-peak-kBps = <(1075200 * 32)>;
>   		};
>   		opp-1209600000 {
>   			opp-hz = /bits/ 64 <1209600000>;
> +			opp-peak-kBps = <(1171200 * 32)>;
>   		};
>   		opp-1324800000 {
>   			opp-hz = /bits/ 64 <1324800000>;
> +			opp-peak-kBps = <(1286400 * 32)>;
>   		};
>   		opp-1440000000 {
>   			opp-hz = /bits/ 64 <1440000000>;
> +			opp-peak-kBps = <(1382400 * 32)>;
>   		};
>   		opp-1555200000 {
>   			opp-hz = /bits/ 64 <1555200000>;
> +			opp-peak-kBps = <(1497600 * 32)>;
>   		};
>   		opp-1670400000 {
>   			opp-hz = /bits/ 64 <1670400000>;
> +			opp-peak-kBps = <(1593600 * 32)>;
>   		};
>   		opp-1785600000 {
>   			opp-hz = /bits/ 64 <1785600000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-1881600000 {
>   			opp-hz = /bits/ 64 <1881600000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2016000000 {
>   			opp-hz = /bits/ 64 <2016000000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2131200000 {
>   			opp-hz = /bits/ 64 <2131200000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2246400000 {
>   			opp-hz = /bits/ 64 <2246400000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   	};
>   
> @@ -76,54 +98,71 @@
>   
>   		opp-825600000 {
>   			opp-hz = /bits/ 64 <825600000>;
> +			opp-peak-kBps = <(300000 * 32)>;
>   		};
>   		opp-940800000 {
>   			opp-hz = /bits/ 64 <940800000>;
> +			opp-peak-kBps = <(864000 * 32)>;
>   		};
>   		opp-1056000000 {
>   			opp-hz = /bits/ 64 <1056000000>;
> +			opp-peak-kBps = <(960000 * 32)>;
>   		};
>   		opp-1171200000 {
>   			opp-hz = /bits/ 64 <1171200000>;
> +			opp-peak-kBps = <(1171200 * 32)>;
>   		};
>   		opp-1286400000 {
>   			opp-hz = /bits/ 64 <1286400000>;
> +			opp-peak-kBps = <(1286400 * 32)>;
>   		};
>   		opp-1401600000 {
>   			opp-hz = /bits/ 64 <1401600000>;
> +			opp-peak-kBps = <(1382400 * 32)>;
>   		};
>   		opp-1516800000 {
>   			opp-hz = /bits/ 64 <1516800000>;
> +			opp-peak-kBps = <(1497600 * 32)>;
>   		};
>   		opp-1632000000 {
>   			opp-hz = /bits/ 64 <1632000000>;
> +			opp-peak-kBps = <(1593600 * 32)>;
>   		};
>   		opp-1747200000 {
>   			opp-hz = /bits/ 64 <1747200000>;
> +			opp-peak-kBps = <(1593600 * 32)>;
>   		};
>   		opp-1862400000 {
>   			opp-hz = /bits/ 64 <1862400000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-1977600000 {
>   			opp-hz = /bits/ 64 <1977600000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2073600000 {
>   			opp-hz = /bits/ 64 <2073600000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2169600000 {
>   			opp-hz = /bits/ 64 <2169600000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2284800000 {
>   			opp-hz = /bits/ 64 <2284800000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2380800000 {
>   			opp-hz = /bits/ 64 <2380800000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2496000000 {
>   			opp-hz = /bits/ 64 <2496000000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   		opp-2592000000 {
>   			opp-hz = /bits/ 64 <2592000000>;
> +			opp-peak-kBps = <(1708800 * 32)>;
>   		};
>   	};
>   };
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 0e80cdcf6bcf..2ac8f5204905 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -6,6 +6,7 @@
>   
>   #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
>   #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
>   #include <dt-bindings/interconnect/qcom,sc8280xp.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/mailbox/qcom-ipcc.h>
> @@ -38,66 +39,87 @@
>   
>   		opp-300000000 {
>   			opp-hz = /bits/ 64 <300000000>;
> +			opp-peak-kBps = <(300000 * 32)>;
>   		};
>   		opp-403200000 {
>   			opp-hz = /bits/ 64 <403200000>;
> +			opp-peak-kBps = <(384000 * 32)>;
>   		};
>   		opp-499200000 {
>   			opp-hz = /bits/ 64 <499200000>;
> +			opp-peak-kBps = <(480000 * 32)>;
>   		};
>   		opp-595200000 {
>   			opp-hz = /bits/ 64 <595200000>;
> +			opp-peak-kBps = <(576000 * 32)>;
>   		};
>   		opp-691200000 {
>   			opp-hz = /bits/ 64 <691200000>;
> +			opp-peak-kBps = <(672000 * 32)>;
>   		};
>   		opp-806400000 {
>   			opp-hz = /bits/ 64 <806400000>;
> +			opp-peak-kBps = <(768000 * 32)>;
>   		};
>   		opp-902400000 {
>   			opp-hz = /bits/ 64 <902400000>;
> +			opp-peak-kBps = <(864000 * 32)>;
>   		};
>   		opp-1017600000 {
>   			opp-hz = /bits/ 64 <1017600000>;
> +			opp-peak-kBps = <(960000 * 32)>;
>   		};
>   		opp-1113600000 {
>   			opp-hz = /bits/ 64 <1113600000>;
> +			opp-peak-kBps = <(1075200 * 32)>;
>   		};
>   		opp-1209600000 {
>   			opp-hz = /bits/ 64 <1209600000>;
> +			opp-peak-kBps = <(1171200 * 32)>;
>   		};
>   		opp-1324800000 {
>   			opp-hz = /bits/ 64 <1324800000>;
> +			opp-peak-kBps = <(1267200 * 32)>;
>   		};
>   		opp-1440000000 {
>   			opp-hz = /bits/ 64 <1440000000>;
> +			opp-peak-kBps = <(1363200 * 32)>;
>   		};
>   		opp-1555200000 {
>   			opp-hz = /bits/ 64 <1555200000>;
> +			opp-peak-kBps = <(1536000 * 32)>;
>   		};
>   		opp-1670400000 {
>   			opp-hz = /bits/ 64 <1670400000>;
> +			opp-peak-kBps = <(1612800 * 32)>;
>   		};
>   		opp-1785600000 {
>   			opp-hz = /bits/ 64 <1785600000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-1881600000 {
>   			opp-hz = /bits/ 64 <1881600000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-1996800000 {
>   			opp-hz = /bits/ 64 <1996800000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2112000000 {
>   			opp-hz = /bits/ 64 <2112000000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2227200000 {
>   			opp-hz = /bits/ 64 <2227200000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2342400000 {
>   			opp-hz = /bits/ 64 <2342400000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2438400000 {
>   			opp-hz = /bits/ 64 <2438400000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   	};
>   
> @@ -107,66 +129,87 @@
>   
>   		opp-825600000 {
>   			opp-hz = /bits/ 64 <825600000>;
> +			opp-peak-kBps = <(768000 * 32)>;
>   		};
>   		opp-940800000 {
>   			opp-hz = /bits/ 64 <940800000>;
> +			opp-peak-kBps = <(864000 * 32)>;
>   		};
>   		opp-1056000000 {
>   			opp-hz = /bits/ 64 <1056000000>;
> +			opp-peak-kBps = <(960000 * 32)>;
>   		};
>   		opp-1171200000 {
>   			opp-hz = /bits/ 64 <1171200000>;
> +			opp-peak-kBps = <(1171200 * 32)>;
>   		};
>   		opp-1286400000 {
>   			opp-hz = /bits/ 64 <1286400000>;
> +			opp-peak-kBps = <(1267200 * 32)>;
>   		};
>   		opp-1401600000 {
>   			opp-hz = /bits/ 64 <1401600000>;
> +			opp-peak-kBps = <(1363200 * 32)>;
>   		};
>   		opp-1516800000 {
>   			opp-hz = /bits/ 64 <1516800000>;
> +			opp-peak-kBps = <(1459200 * 32)>;
>   		};
>   		opp-1632000000 {
>   			opp-hz = /bits/ 64 <1632000000>;
> +			opp-peak-kBps = <(1612800 * 32)>;
>   		};
>   		opp-1747200000 {
>   			opp-hz = /bits/ 64 <1747200000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-1862400000 {
>   			opp-hz = /bits/ 64 <1862400000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-1977600000 {
>   			opp-hz = /bits/ 64 <1977600000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2073600000 {
>   			opp-hz = /bits/ 64 <2073600000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2169600000 {
>   			opp-hz = /bits/ 64 <2169600000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2284800000 {
>   			opp-hz = /bits/ 64 <2284800000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2400000000 {
>   			opp-hz = /bits/ 64 <2400000000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2496000000 {
>   			opp-hz = /bits/ 64 <2496000000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2592000000 {
>   			opp-hz = /bits/ 64 <2592000000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2688000000 {
>   			opp-hz = /bits/ 64 <2688000000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2803200000 {
>   			opp-hz = /bits/ 64 <2803200000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2899200000 {
>   			opp-hz = /bits/ 64 <2899200000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   		opp-2995200000 {
>   			opp-hz = /bits/ 64 <2995200000>;
> +			opp-peak-kBps = <(1689600 * 32)>;
>   		};
>   	};
>   
> @@ -185,6 +228,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 0>;
>   			operating-points-v2 = <&cpu0_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_0: l2-cache {
>   				compatible = "cache";
> @@ -206,6 +250,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 0>;
>   			operating-points-v2 = <&cpu0_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_100: l2-cache {
>   				compatible = "cache";
> @@ -224,6 +269,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 0>;
>   			operating-points-v2 = <&cpu0_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_200: l2-cache {
>   				compatible = "cache";
> @@ -242,6 +288,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 0>;
>   			operating-points-v2 = <&cpu0_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_300: l2-cache {
>   				compatible = "cache";
> @@ -260,6 +307,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 1>;
>   			operating-points-v2 = <&cpu4_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_400: l2-cache {
>   				compatible = "cache";
> @@ -278,6 +326,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 1>;
>   			operating-points-v2 = <&cpu4_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_500: l2-cache {
>   				compatible = "cache";
> @@ -296,6 +345,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 1>;
>   			operating-points-v2 = <&cpu4_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_600: l2-cache {
>   				compatible = "cache";
> @@ -314,6 +364,7 @@
>   			power-domain-names = "psci";
>   			qcom,freq-domain = <&cpufreq_hw 1>;
>   			operating-points-v2 = <&cpu4_opp_table>;
> +			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   			#cooling-cells = <2>;
>   			L2_700: l2-cache {
>   				compatible = "cache";

[PATCH v2 09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances

[Bjorn Andersson]

The sc8280xp platform has two BWMON instances, one v4 and one v5. Extend
the existing qcom,msm8998-bwmon and qcom,sc7280-llcc-bwmon to describe
these.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- Added "cpu" to compatible

 .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index be29e0b80995..0c720dbde36e 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -25,9 +25,14 @@ properties:
       - items:
           - enum:
               - qcom,sc7280-cpu-bwmon
+              - qcom,sc8280xp-cpu-bwmon
               - qcom,sdm845-bwmon
           - const: qcom,msm8998-bwmon
       - const: qcom,msm8998-bwmon       # BWMON v4
+      - items:
+          - enum:
+              - qcom,sc8280xp-llcc-bwmon
+          - const: qcom,sc7280-llcc-bwmon
       - const: qcom,sc7280-llcc-bwmon   # BWMON v5
       - const: qcom,sdm845-llcc-bwmon   # BWMON v5
 
-- 
2.17.1

Re: [PATCH v2 09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances

[Krzysztof Kozlowski]

On 11/11/2022 04:25, Bjorn Andersson wrote:
> The sc8280xp platform has two BWMON instances, one v4 and one v5. Extend
> the existing qcom,msm8998-bwmon and qcom,sc7280-llcc-bwmon to describe
> these.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> The sc8280xp platform has two BWMON instances, one v4 and one v5. Extend
> the existing qcom,msm8998-bwmon and qcom,sc7280-llcc-bwmon to describe
> these.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - Added "cpu" to compatible
> 
>   .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
> index be29e0b80995..0c720dbde36e 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
> @@ -25,9 +25,14 @@ properties:
>         - items:
>             - enum:
>                 - qcom,sc7280-cpu-bwmon
> +              - qcom,sc8280xp-cpu-bwmon
>                 - qcom,sdm845-bwmon
>             - const: qcom,msm8998-bwmon
>         - const: qcom,msm8998-bwmon       # BWMON v4
> +      - items:
> +          - enum:
> +              - qcom,sc8280xp-llcc-bwmon
> +          - const: qcom,sc7280-llcc-bwmon
>         - const: qcom,sc7280-llcc-bwmon   # BWMON v5
>         - const: qcom,sdm845-llcc-bwmon   # BWMON v5
>   

[PATCH v2 10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances

[Bjorn Andersson]

Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
DDR, with bandwidth values based on the downstream DeviceTree.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
---

Changes since v1:
- Added "cpu" to compatible for the CPU-subsystem bwmon instance

 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 91 ++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 2ac8f5204905..62e9dd8a2f07 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1287,6 +1287,97 @@
 			};
 		};
 
+		pmu@9091000 {
+			compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0 0x9091000 0 0x1000>;
+
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <762000>;
+				};
+				opp-1 {
+					opp-peak-kBps = <1720000>;
+				};
+				opp-2 {
+					opp-peak-kBps = <2086000>;
+				};
+				opp-3 {
+					opp-peak-kBps = <2597000>;
+				};
+				opp-4 {
+					opp-peak-kBps = <2929000>;
+				};
+				opp-5 {
+					opp-peak-kBps = <3879000>;
+				};
+				opp-6 {
+					opp-peak-kBps = <5161000>;
+				};
+				opp-7 {
+					opp-peak-kBps = <5931000>;
+				};
+				opp-8 {
+					opp-peak-kBps = <6515000>;
+				};
+				opp-9 {
+					opp-peak-kBps = <7980000>;
+				};
+				opp-10 {
+					opp-peak-kBps = <8136000>;
+				};
+				opp-11 {
+					opp-peak-kBps = <10437000>;
+				};
+				opp-12 {
+					opp-peak-kBps = <12191000>;
+				};
+			};
+		};
+
+		pmu@90b6400 {
+			compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
+			reg = <0 0x090b6400 0 0x600>;
+
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <2288000>;
+				};
+				opp-1 {
+					opp-peak-kBps = <4577000>;
+				};
+				opp-2 {
+					opp-peak-kBps = <7110000>;
+				};
+				opp-3 {
+					opp-peak-kBps = <9155000>;
+				};
+				opp-4 {
+					opp-peak-kBps = <12298000>;
+				};
+				opp-5 {
+					opp-peak-kBps = <14236000>;
+				};
+				opp-6 {
+					opp-peak-kBps = <15258001>;
+				};
+			};
+		};
+
 		system-cache-controller@9200000 {
 			compatible = "qcom,sc8280xp-llcc";
 			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
-- 
2.17.1

Re: [PATCH v2 10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances

[Sibi Sankar]

On 11/11/22 08:55, Bjorn Andersson wrote:
> Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
> DDR, with bandwidth values based on the downstream DeviceTree.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - Added "cpu" to compatible for the CPU-subsystem bwmon instance
> 
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 91 ++++++++++++++++++++++++++
>   1 file changed, 91 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 2ac8f5204905..62e9dd8a2f07 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1287,6 +1287,97 @@
>   			};
>   		};
>   
> +		pmu@9091000 {
> +			compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> +			reg = <0 0x9091000 0 0x1000>;
> +
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
> +
> +			operating-points-v2 = <&llcc_bwmon_opp_table>;
> +
> +			llcc_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <762000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <1720000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <2086000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <2597000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <2929000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <3879000>;
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <5161000>;
> +				};
> +				opp-7 {
> +					opp-peak-kBps = <5931000>;
> +				};
> +				opp-8 {
> +					opp-peak-kBps = <6515000>;
> +				};
> +				opp-9 {
> +					opp-peak-kBps = <7980000>;
> +				};
> +				opp-10 {
> +					opp-peak-kBps = <8136000>;
> +				};
> +				opp-11 {
> +					opp-peak-kBps = <10437000>;
> +				};
> +				opp-12 {
> +					opp-peak-kBps = <12191000>;
> +				};
> +			};
> +		};
> +
> +		pmu@90b6400 {
> +			compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
> +			reg = <0 0x090b6400 0 0x600>;
> +
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +			operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> +			cpu_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <2288000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <4577000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <7110000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <9155000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <12298000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <14236000>;
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <15258001>;
> +				};
> +			};
> +		};
> +
>   		system-cache-controller@9200000 {
>   			compatible = "qcom,sc8280xp-llcc";
>   			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;

Re: [PATCH v2 00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling

[Georgi Djakov]

On 11.11.22 5:25, Bjorn Andersson wrote:
> The SC8280XP currently shows depressing results in memory benchmarks.
> Fix this by introducing support for the platform in the OSM (and EPSS)
> L3 driver and support for the platform in the bwmon binding.
> 
> Then add the necessary nodes and values throughout the sc8280xp and
> sa8540p dtsi files to make the various devices on these platforms scale
> both L3, memory bus and DDR.

Good stuff! Thanks Bjorn!

I plan to merge everything except the dts patches, that should go
through the qcom tree.

BR,
Georgi


> Bjorn Andersson (10):
>    interconnect: qcom: osm-l3: Use platform-independent node ids
>    interconnect: qcom: osm-l3: Squash common descriptors
>    interconnect: qcom: osm-l3: Add per-core EPSS L3 support
>    interconnect: qcom: osm-l3: Simplify osm_l3_set()
>    dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3
>      compatibles
>    arm64: dts: qcom: Align with generic osm-l3/epss-l3
>    arm64: dts: qcom: sc8280xp: Add epss_l3 node
>    arm64: dts: qcom: sc8280xp: Set up L3 scaling
>    dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon
>      instances
>    arm64: dts: qcom: sc8280xp: Add bwmon instances
> 
>   .../interconnect/qcom,msm8998-bwmon.yaml      |   5 +
>   .../bindings/interconnect/qcom,osm-l3.yaml    |  24 ++-
>   arch/arm64/boot/dts/qcom/sa8540p.dtsi         |  39 +++++
>   arch/arm64/boot/dts/qcom/sc7180.dtsi          |   2 +-
>   arch/arm64/boot/dts/qcom/sc7280.dtsi          |   2 +-
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi        | 152 ++++++++++++++++++
>   arch/arm64/boot/dts/qcom/sdm845.dtsi          |   2 +-
>   arch/arm64/boot/dts/qcom/sm8150.dtsi          |   2 +-
>   arch/arm64/boot/dts/qcom/sm8250.dtsi          |   2 +-
>   drivers/interconnect/qcom/osm-l3.c            | 126 ++++-----------
>   10 files changed, 252 insertions(+), 104 deletions(-)
> 

Re: (subset) [PATCH v2 00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling

[Bjorn Andersson]

On Thu, 10 Nov 2022 19:25:05 -0800, Bjorn Andersson wrote:
> The SC8280XP currently shows depressing results in memory benchmarks.
> Fix this by introducing support for the platform in the OSM (and EPSS)
> L3 driver and support for the platform in the bwmon binding.
> 
> Then add the necessary nodes and values throughout the sc8280xp and
> sa8540p dtsi files to make the various devices on these platforms scale
> both L3, memory bus and DDR.
> 
> [...]

Applied, thanks!

[06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3
        commit: a0289a1040a557428a65d099dfdebe80f1a0d0eb
[07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node
        commit: e4f68d6c32aec8f3c7cdb07d18278e9a068a7eb0
[08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling
        commit: 33ba07ffd30a1da6f10995ef0a6ec51e17c84f31
[10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances
        commit: 64ebe7fc473fb3a7d67b73a2faa0a10cb322cdce

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>