* [PATCH 0/6] Add core dtsi for rk3399 from Rockchip
@ 2016-02-17 1:53 jianqun.xu
2016-02-17 1:53 ` [PATCH 1/6] clk: rockchip: add dt-binding header for rk3399 jianqun.xu
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: jianqun.xu @ 2016-02-17 1:53 UTC (permalink / raw)
To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
jwerner, broonie, catalin.marinas, will.deacon, sboyd,
linus.walleij, sjoerd.simons
Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel,
devicetree, Xu Jianqun
From: Xu Jianqun <jay.xu@rock-chips.com>
There is the new SoCs from Rockchip which named rk3399, the
patches are added to support them.
Two patch of cru from Xing are quoted, but the cru driver will
be pushed by Xing near later.
Xing Zheng (2):
clk: rockchip: add dt-binding header for rk3399
dt-bindings: add documentation of rk3399 clock controller
Xu Jianqun (4):
spi: rockchip: add bindings for rk3399 spi
ASoC: rockchip: add bindings for rk3399 i2s
pinctrl: rockchip: add bindings for rk3399 pinctrl
ARM64: dts: rockchip: add core dtsi file for rk3399
.../bindings/clock/rockchip,rk3399-cru.txt | 82 ++
.../bindings/pinctrl/rockchip,pinctrl.txt | 2 +-
.../devicetree/bindings/sound/rockchip-i2s.txt | 1 +
.../devicetree/bindings/spi/spi-rockchip.txt | 1 +
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 +++++++++++++++++++++
include/dt-bindings/clock/rk3399-cru.h | 610 +++++++++++++
6 files changed, 1684 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
create mode 100644 include/dt-bindings/clock/rk3399-cru.h
--
1.9.1
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/6] clk: rockchip: add dt-binding header for rk3399 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu @ 2016-02-17 1:53 ` jianqun.xu 2016-02-17 1:53 ` [PATCH 2/6] spi: rockchip: add bindings for rk3399 spi jianqun.xu ` (5 subsequent siblings) 6 siblings, 0 replies; 24+ messages in thread From: jianqun.xu @ 2016-02-17 1:53 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng From: Xing Zheng <zhengxing@rock-chips.com> Add the dt-bindings header for the rk3399, that gets shared between the clock controller and the clock references in the dts. Change-Id: I01830a46b679f4630506e8cb48b1a39e113a9952 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- include/dt-bindings/clock/rk3399-cru.h | 610 +++++++++++++++++++++++++++++++++ 1 file changed, 610 insertions(+) create mode 100644 include/dt-bindings/clock/rk3399-cru.h diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 0000000..42a1618 --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,610 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define PLL_PPLL 8 +#define ARMCLKL 9 +#define ARMCLKB 10 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 68 +#define SCLK_SPI3 69 +#define SCLK_SPI4 70 +#define SCLK_SPI5 71 +#define SCLK_SDMMC 72 +#define SCLK_SDIO0 73 +#define SCLK_EMMC 74 +#define SCLK_TSADC 75 +#define SCLK_SARADC 76 +#define SCLK_NANDC0 77 +#define SCLK_UART0 78 +#define SCLK_UART1 79 +#define SCLK_UART2 80 +#define SCLK_UART3 81 +#define SCLK_UART4 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S0_8CH 84 +#define SCLK_I2S1_8CH 85 +#define SCLK_I2S2_8CH 86 +#define SCLK_TIMER00 87 +#define SCLK_TIMER01 88 +#define SCLK_TIMER02 89 +#define SCLK_TIMER03 90 +#define SCLK_TIMER04 91 +#define SCLK_TIMER05 92 +#define SCLK_TIMER06 93 +#define SCLK_TIMER07 94 +#define SCLK_TIMER08 95 +#define SCLK_TIMER09 96 +#define SCLK_TIMER10 97 +#define SCLK_TIMER11 98 +#define SCLK_HSICPHY480M 99 +#define SCLK_HSICPHY12M 100 +#define SCLK_MACREF 101 +#define SCLK_VOPB_PWM 102 +#define SCLK_VOPL_PWM 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE_L 123 +#define SCLK_PVTM_CORE_B 124 +#define SCLK_PVTM_GPU 125 +#define SCLK_PVTM_PMU 126 +#define SCLK_SFC 127 +#define SCLK_MAC_RX 128 +#define SCLK_MAC_TX 129 +#define SCLK_MAC 130 +#define SCLK_MACREF_OUT 131 +#define SCLK_USB2_PHY0_REF 132 +#define SCLK_USB2_PHY1_REF 133 +#define SCLK_USB3_OTG0_REF 134 +#define SCLK_USB3_OTG1_REF 135 +#define SCLK_USB3_OTG0_SUSPEND 136 +#define SCLK_USB3_OTG1_SUSPEND 137 +#define SCLK_CRYPTO 138 +#define SCLK_CRYPTO1 139 + +#define DCLK_VOPB 170 +#define DCLK_VOPL 171 +#define MCLK_CRYPTO 172 +#define MCLK_CRYPTO1 173 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOPB 198 +#define ACLK_VOPL 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 +#define ACLK_EMMC_GPLL 211 +#define ACLK_EMMC_CPLL 212 +#define ACLK_EMMC_CORE 213 +#define ACLK_EMMC_NIU 214 +#define ACLK_EMMC_GRF 215 +#define ACLK_USB3_OTG0 216 +#define ACLK_USB3_OTG1 217 +#define ACLK_USB3_GRF 218 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GPIO4 324 +#define PCLK_PMUGRF 325 +#define PCLK_MAILBOX 326 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_SPI3 341 +#define PCLK_SPI4 342 +#define PCLK_SPI5 343 +#define PCLK_UART0 344 +#define PCLK_UART1 345 +#define PCLK_UART2 346 +#define PCLK_UART3 347 +#define PCLK_UART4 348 +#define PCLK_TSADC 349 +#define PCLK_SARADC 350 +#define PCLK_SIM 351 +#define PCLK_GMAC 352 +#define PCLK_PWM0 353 +#define PCLK_PWM1 354 +#define PCLK_TIMER0 355 +#define PCLK_TIMER1 356 +#define PCLK_EDP_CTRL 357 +#define PCLK_MIPI_DSI0 358 +#define PCLK_MIPI_CSI 359 +#define PCLK_HDCP 360 +#define PCLK_HDMI_CTRL 361 +#define PCLK_VIO_H2P 362 +#define PCLK_BUS 363 +#define PCLK_PERI 364 +#define PCLK_DDRUPCTL 365 +#define PCLK_DDRPHY 366 +#define PCLK_ISP 367 +#define PCLK_VIP 368 +#define PCLK_WDT 369 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S0_8CH 462 +#define HCLK_I2S1_8CH 463 +#define HCLK_I2S2_8CH 464 +#define HCLK_SPDIF 465 +#define HCLK_VOPB 466 +#define HCLK_VOPL 467 +#define HCLK_ROM 468 +#define HCLK_IEP 469 +#define HCLK_ISP 470 +#define HCLK_RGA 471 +#define HCLK_VIO_AHB_ARBI 472 +#define HCLK_VIO_NOC 473 +#define HCLK_VIP 474 +#define HCLK_VIO_H2P 475 +#define HCLK_VIO_HDCPMMU 476 +#define HCLK_VIDEO 477 +#define HCLK_BUS 478 +#define HCLK_PERI 479 + +/* pmu-clocks indices */ +#define SCLK_CM0S 500 +#define SCLK_SPI5 501 +#define SCLK_TIMER12 502 +#define SCLK_TIMER13 503 +#define SCLK_UART 504 + +#define CLK_NR_CLKS (SCLK_UART + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NIU 9 +#define SRST_A_CCIM1_NIU 10 +#define SRST_DBG_NIU 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2_CORE_L 24 +#define SRST_A_ADB400_CORE_L_GIC2 25 +#define SRST_P_DBG_L 26 +#define SRST_SOC_DBG_L 27 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKREF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2_CORE_B 40 +#define SRST_A_ADB400_CORE_B_GIC2 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_SOC_DBG_B 44 +#define SRST_ADB_B_T 45 +#define SRST_A_RKREF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NIU_T 51 +#define SRST_A_CCIM1_NIU_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NIU_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NIU 64 +#define SRST_A_CENTER_PERI_NIU 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMAON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NIU 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NIU 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NIU 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NIU 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NIU 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NIU 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NIU 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NIU 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NIU 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 +#define SRST_EMMCPHY_SYSRX 111 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NIU 112 +#define SRST_A_PERIHP_GRF 113 +#define SRST_H_PERIHP_NIU 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOSTC0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOSTC1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NIU 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NIU 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NIU 138 +#define SRST_P_GMAC 139 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NIU 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NIU 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NIU 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NIU 188 +#define SRST_SD_NIU 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NIU 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NIU 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI3 222 +#define SRST_SPI4 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NIU 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NIU 240 +#define SRST_A_HDCP_NIU 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NIU 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NIU 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 +#define SRST_DP_VIF 255 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_SGRF 257 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NIU 262 +#define SRST_A_ISP1_NIU 263 +#define SRST_A_ISP0 264 +#define SRST_A_ISP1 265 +#define SRST_H_ISP0_NIU 266 +#define SRST_H_ISP1_NIU 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NIU 272 +#define SRST_A_VOP1_NIU 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NIU 276 +#define SRST_H_VOP1_NIU 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NIU 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NIU 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NIU 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 +#define SRST_PVTM_PMU 297 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIME5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NIU 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY1_DPTX 329 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY1_APB 331 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NIU 0 +#define SRST_P_INTMEN 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NIU 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/6] spi: rockchip: add bindings for rk3399 spi 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu 2016-02-17 1:53 ` [PATCH 1/6] clk: rockchip: add dt-binding header for rk3399 jianqun.xu @ 2016-02-17 1:53 ` jianqun.xu 2016-02-18 14:37 ` Rob Herring 2016-02-17 1:53 ` [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s jianqun.xu ` (4 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: jianqun.xu @ 2016-02-17 1:53 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xu Jianqun From: Xu Jianqun <jay.xu@rock-chips.com> Add devicetree bindings for Rockchip rk3399 spi which found on Rockchip rk3399 SoCs. Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> --- Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt index 0c491bd..1b14d69 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt @@ -9,6 +9,7 @@ Required Properties: "rockchip,rk3066-spi" for rk3066. "rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188. "rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288. + "rockchip,rk3399-spi", "rockchip,rk3066-spi" for rk3399. - reg: physical base address of the controller and length of memory mapped region. - interrupts: The interrupt number to the cpu. The interrupt specifier format -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 2/6] spi: rockchip: add bindings for rk3399 spi 2016-02-17 1:53 ` [PATCH 2/6] spi: rockchip: add bindings for rk3399 spi jianqun.xu @ 2016-02-18 14:37 ` Rob Herring 0 siblings, 0 replies; 24+ messages in thread From: Rob Herring @ 2016-02-18 14:37 UTC (permalink / raw) To: jianqun.xu Cc: heiko, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree On Wed, Feb 17, 2016 at 09:53:08AM +0800, jianqun.xu wrote: > From: Xu Jianqun <jay.xu@rock-chips.com> > > Add devicetree bindings for Rockchip rk3399 spi which found on > Rockchip rk3399 SoCs. > > Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu 2016-02-17 1:53 ` [PATCH 1/6] clk: rockchip: add dt-binding header for rk3399 jianqun.xu 2016-02-17 1:53 ` [PATCH 2/6] spi: rockchip: add bindings for rk3399 spi jianqun.xu @ 2016-02-17 1:53 ` jianqun.xu 2016-02-17 11:03 ` Mark Brown 2016-02-18 14:36 ` Rob Herring 2016-02-17 1:53 ` [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl jianqun.xu ` (3 subsequent siblings) 6 siblings, 2 replies; 24+ messages in thread From: jianqun.xu @ 2016-02-17 1:53 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xu Jianqun From: Xu Jianqun <jay.xu@rock-chips.com> Add devicetree bindings for i2s controller found on rk3399 processors from rockchip. Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> --- Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt index b7f3a93..6e86d8a 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt @@ -9,6 +9,7 @@ Required properties: - "rockchip,rk3066-i2s": for rk3066 - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188 - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288 + - "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399 - reg: physical base address of the controller and length of memory mapped region. - interrupts: should contain the I2S interrupt. -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s 2016-02-17 1:53 ` [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s jianqun.xu @ 2016-02-17 11:03 ` Mark Brown 2016-02-18 14:37 ` Rob Herring 2016-02-18 14:36 ` Rob Herring 1 sibling, 1 reply; 24+ messages in thread From: Mark Brown @ 2016-02-17 11:03 UTC (permalink / raw) To: jianqun.xu Cc: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree [-- Attachment #1: Type: text/plain, Size: 271 bytes --] On Wed, Feb 17, 2016 at 09:53:09AM +0800, jianqun.xu wrote: > --- > Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 1 + > 1 file changed, 1 insertion(+) As with the other patch I'd expect to see a matching driver update if only for documentation purposes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 473 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s 2016-02-17 11:03 ` Mark Brown @ 2016-02-18 14:37 ` Rob Herring 2016-02-18 14:59 ` Mark Brown 0 siblings, 1 reply; 24+ messages in thread From: Rob Herring @ 2016-02-18 14:37 UTC (permalink / raw) To: Mark Brown Cc: jianqun.xu, heiko, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree On Wed, Feb 17, 2016 at 11:03:06AM +0000, Mark Brown wrote: > On Wed, Feb 17, 2016 at 09:53:09AM +0800, jianqun.xu wrote: > > > --- > > Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 1 + > > 1 file changed, 1 insertion(+) > > As with the other patch I'd expect to see a matching driver update if > only for documentation purposes. Why? They match on the prior chip's compatible until there is some difference the driver needs to handle. Rob ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s 2016-02-18 14:37 ` Rob Herring @ 2016-02-18 14:59 ` Mark Brown 0 siblings, 0 replies; 24+ messages in thread From: Mark Brown @ 2016-02-18 14:59 UTC (permalink / raw) To: Rob Herring Cc: jianqun.xu, heiko, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree [-- Attachment #1: Type: text/plain, Size: 743 bytes --] On Thu, Feb 18, 2016 at 08:37:02AM -0600, Rob Herring wrote: > On Wed, Feb 17, 2016 at 11:03:06AM +0000, Mark Brown wrote: > > As with the other patch I'd expect to see a matching driver update if > > only for documentation purposes. > Why? They match on the prior chip's compatible until there is some > difference the driver needs to handle. That then requires anyone using a compatible string to also know the full set of other compatible strings that can be used for this device and that they have to list the others too in the correct order which isn't something the binding document tells them. It also feels better to record in the code how we think we should support the device when we know it, seems more helpful. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 473 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s 2016-02-17 1:53 ` [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s jianqun.xu 2016-02-17 11:03 ` Mark Brown @ 2016-02-18 14:36 ` Rob Herring 1 sibling, 0 replies; 24+ messages in thread From: Rob Herring @ 2016-02-18 14:36 UTC (permalink / raw) To: jianqun.xu Cc: heiko, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree On Wed, Feb 17, 2016 at 09:53:09AM +0800, jianqun.xu wrote: > From: Xu Jianqun <jay.xu@rock-chips.com> > > Add devicetree bindings for i2s controller found on rk3399 > processors from rockchip. > > Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu ` (2 preceding siblings ...) 2016-02-17 1:53 ` [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s jianqun.xu @ 2016-02-17 1:53 ` jianqun.xu 2016-02-17 6:47 ` Heiko Stuebner 2016-02-17 1:54 ` [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller jianqun.xu ` (2 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: jianqun.xu @ 2016-02-17 1:53 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xu Jianqun From: Xu Jianqun <jay.xu@rock-chips.com> Add devicetree bindings for pinctrl found on rk3399 processors from rockchip. Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> --- Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 0cd701b..c68b955 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -22,7 +22,7 @@ Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" - "rockchip,rk3368-pinctrl" + "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl 2016-02-17 1:53 ` [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl jianqun.xu @ 2016-02-17 6:47 ` Heiko Stuebner 2016-02-17 7:23 ` Jianqun Xu 0 siblings, 1 reply; 24+ messages in thread From: Heiko Stuebner @ 2016-02-17 6:47 UTC (permalink / raw) To: jianqun.xu Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree Hi Jianqun, Am Mittwoch, 17. Februar 2016, 09:53:10 schrieb jianqun.xu: > From: Xu Jianqun <jay.xu@rock-chips.com> > > Add devicetree bindings for pinctrl found on rk3399 > processors from rockchip. > > Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index > 0cd701b..c68b955 100644 > --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt > @@ -22,7 +22,7 @@ Required properties for iomux controller: > - compatible: one of "rockchip,rk2928-pinctrl", > "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", > "rockchip,rk3188-pinctrl" > "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" > - "rockchip,rk3368-pinctrl" > + "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl" > - rockchip,grf: phandle referencing a syscon providing the > "general register files" that is already contained in David's core pinctrl patch that already got applied to the pinctrl tree. Heiko ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl 2016-02-17 6:47 ` Heiko Stuebner @ 2016-02-17 7:23 ` Jianqun Xu 0 siblings, 0 replies; 24+ messages in thread From: Jianqun Xu @ 2016-02-17 7:23 UTC (permalink / raw) To: Heiko Stuebner Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree 在 17/02/2016 14:47, Heiko Stuebner 写道: > Hi Jianqun, > > Am Mittwoch, 17. Februar 2016, 09:53:10 schrieb jianqun.xu: >> From: Xu Jianqun <jay.xu@rock-chips.com> >> >> Add devicetree bindings for pinctrl found on rk3399 >> processors from rockchip. >> >> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> >> --- >> Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git >> a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt >> b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index >> 0cd701b..c68b955 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt >> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt >> @@ -22,7 +22,7 @@ Required properties for iomux controller: >> - compatible: one of "rockchip,rk2928-pinctrl", >> "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", >> "rockchip,rk3188-pinctrl" >> "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" >> - "rockchip,rk3368-pinctrl" >> + "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl" >> - rockchip,grf: phandle referencing a syscon providing the >> "general register files" > > that is already contained in David's core pinctrl patch that already got > applied to the pinctrl tree. > Sorry very much, I forgot it after a long time of spring holiday thanks > > Heiko > > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu ` (3 preceding siblings ...) 2016-02-17 1:53 ` [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl jianqun.xu @ 2016-02-17 1:54 ` jianqun.xu 2016-02-18 14:36 ` Rob Herring 2016-02-17 2:01 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu 2016-02-17 2:04 ` [PATCH 1/6] clk: rockchip: add dt-binding header " jianqun.xu 6 siblings, 1 reply; 24+ messages in thread From: jianqun.xu @ 2016-02-17 1:54 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng From: Xing Zheng <zhengxing@rock-chips.com> Add the devicetree binding for the cru on the rk3399 which quite similar structured as previous clock controllers. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- .../bindings/clock/rockchip,rk3399-cru.txt | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new file mode 100644 index 0000000..07bcc6e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt @@ -0,0 +1,82 @@ +* Rockchip RK3399 Clock and Reset Unit + +The RK3399 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" +- compatible: CRU should be "rockchip,rk3399-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing, pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + - "ext_vip" - external VIP clock - optional, + - "usbotg_out" - output clock of the pll in the otg phy + +Example: General Register Files + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon"; + reg = <0x0 0xff320000 0x0 0x1000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x10000>; + }; + +Example: Clock controller node: + + pmucru: pmu-clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0x0 0xff750000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@ff1a0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller 2016-02-17 1:54 ` [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller jianqun.xu @ 2016-02-18 14:36 ` Rob Herring 2016-02-19 0:48 ` Jianqun Xu 0 siblings, 1 reply; 24+ messages in thread From: Rob Herring @ 2016-02-18 14:36 UTC (permalink / raw) To: jianqun.xu Cc: heiko, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote: > From: Xing Zheng <zhengxing@rock-chips.com> > > Add the devicetree binding for the cru on the rk3399 which quite > similar structured as previous clock controllers. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > --- > .../bindings/clock/rockchip,rk3399-cru.txt | 82 ++++++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > new file mode 100644 > index 0000000..07bcc6e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > @@ -0,0 +1,82 @@ > +* Rockchip RK3399 Clock and Reset Unit [...] > +Example: General Register Files > + > + pmugrf: syscon@ff320000 { > + compatible = "rockchip,rk3399-pmugrf", "syscon"; Is this documented? > + reg = <0x0 0xff320000 0x0 0x1000>; > + }; > + > + grf: syscon@ff770000 { > + compatible = "rockchip,rk3399-grf", "syscon"; ditto. > + reg = <0x0 0xff770000 0x0 0x10000>; > + }; > + > +Example: Clock controller node: > + > + pmucru: pmu-clock-controller@ff750000 { > + compatible = "rockchip,rk3399-pmucru"; > + reg = <0x0 0xff750000 0x0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + cru: clock-controller@ff760000 { > + compatible = "rockchip,rk3399-cru"; > + reg = <0x0 0xff760000 0x0 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > +Example: UART controller node that consumes the clock generated by the clock > + controller: > + > + uart0: serial@ff1a0000 { > + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xff180000 0x0 0x100>; > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > + clock-names = "baudclk", "apb_pclk"; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + }; > -- > 1.9.1 > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller 2016-02-18 14:36 ` Rob Herring @ 2016-02-19 0:48 ` Jianqun Xu 2016-02-19 0:53 ` Heiko Stuebner 0 siblings, 1 reply; 24+ messages in thread From: Jianqun Xu @ 2016-02-19 0:48 UTC (permalink / raw) To: Rob Herring Cc: heiko, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng Hi Rob 在 18/02/2016 22:36, Rob Herring 写道: > On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote: >> From: Xing Zheng <zhengxing@rock-chips.com> >> >> Add the devicetree binding for the cru on the rk3399 which quite >> similar structured as previous clock controllers. >> >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> >> --- >> .../bindings/clock/rockchip,rk3399-cru.txt | 82 ++++++++++++++++++++++ >> 1 file changed, 82 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >> new file mode 100644 >> index 0000000..07bcc6e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >> @@ -0,0 +1,82 @@ >> +* Rockchip RK3399 Clock and Reset Unit > > [...] > >> +Example: General Register Files >> + >> + pmugrf: syscon@ff320000 { >> + compatible = "rockchip,rk3399-pmugrf", "syscon"; > > Is this documented? Since there is no documentation for rockchip grf from early SoCs, I think if we need to add a new devicetree documentation, such as Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ? If you agree, I will add it in next patch > >> + reg = <0x0 0xff320000 0x0 0x1000>; >> + }; >> + >> + grf: syscon@ff770000 { >> + compatible = "rockchip,rk3399-grf", "syscon"; > > ditto. > >> + reg = <0x0 0xff770000 0x0 0x10000>; >> + }; >> + >> +Example: Clock controller node: >> + >> + pmucru: pmu-clock-controller@ff750000 { >> + compatible = "rockchip,rk3399-pmucru"; >> + reg = <0x0 0xff750000 0x0 0x1000>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + cru: clock-controller@ff760000 { >> + compatible = "rockchip,rk3399-cru"; >> + reg = <0x0 0xff760000 0x0 0x1000>; >> + rockchip,grf = <&grf>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> +Example: UART controller node that consumes the clock generated by the clock >> + controller: >> + >> + uart0: serial@ff1a0000 { >> + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; >> + reg = <0x0 0xff180000 0x0 0x100>; >> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + }; >> -- >> 1.9.1 >> >> > > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller 2016-02-19 0:48 ` Jianqun Xu @ 2016-02-19 0:53 ` Heiko Stuebner 2016-02-19 1:05 ` Jianqun Xu 0 siblings, 1 reply; 24+ messages in thread From: Heiko Stuebner @ 2016-02-19 0:53 UTC (permalink / raw) To: Jianqun Xu Cc: Rob Herring, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng Am Freitag, 19. Februar 2016, 08:48:15 schrieb Jianqun Xu: > Hi Rob > > 在 18/02/2016 22:36, Rob Herring 写道: > > On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote: > >> From: Xing Zheng <zhengxing@rock-chips.com> > >> > >> Add the devicetree binding for the cru on the rk3399 which quite > >> similar structured as previous clock controllers. > >> > >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > >> --- > >> > >> .../bindings/clock/rockchip,rk3399-cru.txt | 82 > >> ++++++++++++++++++++++ 1 file changed, 82 insertions(+) > >> create mode 100644 > >> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt>> > >> diff --git > >> a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > >> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new > >> file mode 100644 > >> index 0000000..07bcc6e > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt > >> @@ -0,0 +1,82 @@ > >> +* Rockchip RK3399 Clock and Reset Unit > > > > [...] > > > >> +Example: General Register Files > >> + > >> + pmugrf: syscon@ff320000 { > >> + compatible = "rockchip,rk3399-pmugrf", "syscon"; > > > > Is this documented? > > Since there is no documentation for rockchip grf from early SoCs, I > think if we need to add a new devicetree documentation, such as > Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ? The grf is not clock-specific, so the directory is probably not correct. I'd think bindings/arm/rockchip/grf.txt might be better or bindings/soc/rockchip/grf.txt or somewhere else. And define the properties for all per-soc GRFs in there. In any case we really should add the missing grf binding documentation (in a separate patch of course), as the grf is a pretty commonly used shared component. > > If you agree, I will add it in next patch > > >> + reg = <0x0 0xff320000 0x0 0x1000>; > >> + }; > >> + > >> + grf: syscon@ff770000 { > >> + compatible = "rockchip,rk3399-grf", "syscon"; > > > > ditto. > > > >> + reg = <0x0 0xff770000 0x0 0x10000>; > >> + }; > >> + > >> +Example: Clock controller node: > >> + > >> + pmucru: pmu-clock-controller@ff750000 { > >> + compatible = "rockchip,rk3399-pmucru"; > >> + reg = <0x0 0xff750000 0x0 0x1000>; > >> + #clock-cells = <1>; > >> + #reset-cells = <1>; > >> + }; > >> + > >> + cru: clock-controller@ff760000 { > >> + compatible = "rockchip,rk3399-cru"; > >> + reg = <0x0 0xff760000 0x0 0x1000>; > >> + rockchip,grf = <&grf>; > >> + #clock-cells = <1>; > >> + #reset-cells = <1>; > >> + }; > >> + > >> +Example: UART controller node that consumes the clock generated by the > >> clock + controller: > >> + > >> + uart0: serial@ff1a0000 { > >> + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; > >> + reg = <0x0 0xff180000 0x0 0x100>; > >> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > >> + clock-names = "baudclk", "apb_pclk"; > >> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > >> + reg-shift = <2>; > >> + reg-io-width = <4>; > >> + }; > >> -- > >> 1.9.1 ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller 2016-02-19 0:53 ` Heiko Stuebner @ 2016-02-19 1:05 ` Jianqun Xu 0 siblings, 0 replies; 24+ messages in thread From: Jianqun Xu @ 2016-02-19 1:05 UTC (permalink / raw) To: Heiko Stuebner Cc: Rob Herring, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng Hi Heiko 在 19/02/2016 08:53, Heiko Stuebner 写道: > Am Freitag, 19. Februar 2016, 08:48:15 schrieb Jianqun Xu: >> Hi Rob >> >> 在 18/02/2016 22:36, Rob Herring 写道: >>> On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote: >>>> From: Xing Zheng <zhengxing@rock-chips.com> >>>> >>>> Add the devicetree binding for the cru on the rk3399 which quite >>>> similar structured as previous clock controllers. >>>> >>>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> >>>> --- >>>> >>>> .../bindings/clock/rockchip,rk3399-cru.txt | 82 >>>> ++++++++++++++++++++++ 1 file changed, 82 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new >>>> file mode 100644 >>>> index 0000000..07bcc6e >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>>> @@ -0,0 +1,82 @@ >>>> +* Rockchip RK3399 Clock and Reset Unit >>> >>> [...] >>> >>>> +Example: General Register Files >>>> + >>>> + pmugrf: syscon@ff320000 { >>>> + compatible = "rockchip,rk3399-pmugrf", "syscon"; >>> >>> Is this documented? >> >> Since there is no documentation for rockchip grf from early SoCs, I >> think if we need to add a new devicetree documentation, such as >> Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ? > > The grf is not clock-specific, so the directory is probably not correct. > I'd think bindings/arm/rockchip/grf.txt might be better or > bindings/soc/rockchip/grf.txt or somewhere else. And define the properties > for all per-soc GRFs in there. > > In any case we really should add the missing grf binding documentation (in a > separate patch of course), as the grf is a pretty commonly used shared > component. > Got it, I will add bindings/soc/rockchip/grf.txt in next patch Thanks ! > >> >> If you agree, I will add it in next patch >> >>>> + reg = <0x0 0xff320000 0x0 0x1000>; >>>> + }; >>>> + >>>> + grf: syscon@ff770000 { >>>> + compatible = "rockchip,rk3399-grf", "syscon"; >>> >>> ditto. >>> >>>> + reg = <0x0 0xff770000 0x0 0x10000>; >>>> + }; >>>> + >>>> +Example: Clock controller node: >>>> + >>>> + pmucru: pmu-clock-controller@ff750000 { >>>> + compatible = "rockchip,rk3399-pmucru"; >>>> + reg = <0x0 0xff750000 0x0 0x1000>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >>>> + cru: clock-controller@ff760000 { >>>> + compatible = "rockchip,rk3399-cru"; >>>> + reg = <0x0 0xff760000 0x0 0x1000>; >>>> + rockchip,grf = <&grf>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >>>> +Example: UART controller node that consumes the clock generated by the >>>> clock + controller: >>>> + >>>> + uart0: serial@ff1a0000 { >>>> + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; >>>> + reg = <0x0 0xff180000 0x0 0x100>; >>>> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; >>>> + clock-names = "baudclk", "apb_pclk"; >>>> + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg-shift = <2>; >>>> + reg-io-width = <4>; >>>> + }; >>>> -- >>>> 1.9.1 > > > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu ` (4 preceding siblings ...) 2016-02-17 1:54 ` [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller jianqun.xu @ 2016-02-17 2:01 ` jianqun.xu 2016-02-17 7:00 ` Heiko Stuebner ` (2 more replies) 2016-02-17 2:04 ` [PATCH 1/6] clk: rockchip: add dt-binding header " jianqun.xu 6 siblings, 3 replies; 24+ messages in thread From: jianqun.xu @ 2016-02-17 2:01 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xu Jianqun From: Xu Jianqun <jay.xu@rock-chips.com> Add dtsi file for Rockchip rk3399 SoCs, which includes some general nodes such as cpu, pmu, cru, gic, amba and so on. Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644 index 0000000..eb671f6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -0,0 +1,989 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <dt-bindings/clock/rk3399-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "rockchip,rk3399"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep-0 { + compatible = "arm,idle-state"; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = + <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + gic: interrupt-controller@fee00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ + <0x0 0xfef00000 0 0xc0000>, /* GICR */ + <0x0 0xfff00000 0 0x10000>, /* GICC */ + <0x0 0xfff10000 0 0x10000>, /* GICH */ + <0x0 0xfff20000 0 0x10000>; /* GICV */ + interrupts = + <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + its: interrupt-controller@fee20000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xfee20000 0x0 0x20000>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_bus: dma-controller@ff6d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6d0000 0x0 0x4000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC_BUS>; + clock-names = "apb_pclk"; + }; + + dmac_peri: dma-controller@ff6e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6e0000 0x0 0x4000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC_PERI>; + clock-names = "apb_pclk"; + }; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff1a0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1a0000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi0: spi@ff1c0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff110000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff1d0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff1e0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@ff1f0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@ff200000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon"; + reg = <0x0 0xff320000 0x0 0x1000>; + }; + + spi3: spi@ff350000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff110000 0x0 0x1000>; + clocks = <&cru SCLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@ff370000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff370000 0x0 0x100>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: pmu-clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0x0 0xff750000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x10000>; + }; + + i2s0: i2s@ff880000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff880000 0x0 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>; + status = "disabled"; + }; + + i2s1: i2s@ff890000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac_bus 2>, <&dmac_bus 3>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>; + status = "disabled"; + }; + + i2s2: i2s@ff8a0000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff8a0000 0x0 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac_bus 4>, <&dmac_bus 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3399-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + gpio0: gpio0@ff720000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff720000 0x0 0x100>; + clocks = <&xin24m>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1@ff730000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff730000 0x0 0x100>; + clocks = <&xin24m>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&xin24m>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3@ff788000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff788000 0x0 0x100>; + clocks = <&xin24m>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio4: gpio4@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&xin24m>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_down_12ma: pcfg-pull-down-12ma { + bias-pull-down; + drive-strength = <12>; + }; + + emmc { + emmc_pwr: emmc-pwr { + rockchip,pins = + <0 5 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = + <3 11 RK_FUNC_1 &pcfg_pull_none>, + <3 13 RK_FUNC_1 &pcfg_pull_none>, + <3 8 RK_FUNC_1 &pcfg_pull_none>, + <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 6 RK_FUNC_1 &pcfg_pull_none>, + <3 7 RK_FUNC_1 &pcfg_pull_none>, + <3 2 RK_FUNC_1 &pcfg_pull_none>, + <3 3 RK_FUNC_1 &pcfg_pull_none>, + <3 14 RK_FUNC_1 &pcfg_pull_none>, + <3 9 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = + <3 11 RK_FUNC_1 &pcfg_pull_none>, + <3 13 RK_FUNC_1 &pcfg_pull_none>, + <3 8 RK_FUNC_1 &pcfg_pull_none>, + <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 6 RK_FUNC_1 &pcfg_pull_none>, + <3 7 RK_FUNC_1 &pcfg_pull_none>, + <3 9 RK_FUNC_1 &pcfg_pull_none>, + <3 10 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <1 15 RK_FUNC_2 &pcfg_pull_none>, + <1 16 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <4 2 RK_FUNC_1 &pcfg_pull_none>, + <4 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, + <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <4 17 RK_FUNC_1 &pcfg_pull_none>, + <4 16 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>, + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = + <3 11 RK_FUNC_2 &pcfg_pull_none>, + <3 10 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c6 { + i2c6_xfer: i2c6-xfer { + rockchip,pins = + <2 10 RK_FUNC_2 &pcfg_pull_none>, + <2 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c7 { + i2c7_xfer: i2c7-xfer { + rockchip,pins = + <2 8 RK_FUNC_2 &pcfg_pull_none>, + <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c8 { + i2c8_xfer: i2c8-xfer { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>, + <1 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>, + <3 28 RK_FUNC_1 &pcfg_pull_none>, + <3 29 RK_FUNC_1 &pcfg_pull_none>, + <3 30 RK_FUNC_1 &pcfg_pull_none>, + <3 31 RK_FUNC_1 &pcfg_pull_none>, + <4 0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_2ch_bus: i2s1-2ch-bus { + rockchip,pins = + <4 3 RK_FUNC_1 &pcfg_pull_none>, + <4 4 RK_FUNC_1 &pcfg_pull_none>, + <4 5 RK_FUNC_1 &pcfg_pull_none>, + <4 6 RK_FUNC_1 &pcfg_pull_none>, + <4 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = + <2 20 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 20 RK_FUNC_1 &pcfg_pull_up>, + <2 21 RK_FUNC_1 &pcfg_pull_up>, + <2 22 RK_FUNC_1 &pcfg_pull_up>, + <2 23 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 24 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = + <2 26 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = + <2 27 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = + <2 28 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = + <0 3 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = + <0 4 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up>, + <4 9 RK_FUNC_1 &pcfg_pull_up>, + <4 10 RK_FUNC_1 &pcfg_pull_up>, + <4 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmcc-cd { + rockchip,pins = + <0 7 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = + <0 8 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <3 6 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = + <3 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = + <3 8 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = + <3 5 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = + <3 4 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <1 9 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = + <1 10 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = + <1 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = + <1 8 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = + <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = + <2 12 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = + <2 9 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = + <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi3 { + spi3_clk: spi3-clk { + rockchip,pins = + <1 17 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_cs0: spi3-cs0 { + rockchip,pins = + <1 18 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_rx: spi3-rx { + rockchip,pins = + <1 15 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_tx: spi3-tx { + rockchip,pins = + <1 16 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi4 { + spi4_clk: spi4-clk { + rockchip,pins = + <3 2 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_cs0: spi4-cs0 { + rockchip,pins = + <3 3 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_rx: spi4-rx { + rockchip,pins = + <3 0 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_tx: spi4-tx { + rockchip,pins = + <3 1 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi5 { + spi5_clk: spi5-clk { + rockchip,pins = + <2 22 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_cs0: spi5-cs0 { + rockchip,pins = + <2 23 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_rx: spi5-rx { + rockchip,pins = + <2 20 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_tx: spi5-tx { + rockchip,pins = + <2 21 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <2 16 RK_FUNC_1 &pcfg_pull_up>, + <2 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <2 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <2 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <3 12 RK_FUNC_2 &pcfg_pull_up>, + <3 13 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2a { + uart2a_xfer: uart2a-xfer { + rockchip,pins = + <4 8 RK_FUNC_2 &pcfg_pull_up>, + <4 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2b { + uart2b_xfer: uart2b-xfer { + rockchip,pins = + <4 16 RK_FUNC_2 &pcfg_pull_up>, + <4 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2c { + uart2c_xfer: uart2c-xfer { + rockchip,pins = + <4 19 RK_FUNC_1 &pcfg_pull_up>, + <4 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = + <3 14 RK_FUNC_2 &pcfg_pull_up>, + <3 15 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = + <3 18 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + <1 7 RK_FUNC_1 &pcfg_pull_up>, + <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uarthdcp { + uarthdcp_xfer: uarthdcp-xfer { + rockchip,pins = + <4 21 RK_FUNC_2 &pcfg_pull_up>, + <4 22 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <4 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + vop0_pwm_pin: vop0-pwm-pin { + rockchip,pins = + <4 18 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <4 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 18 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 2016-02-17 2:01 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu @ 2016-02-17 7:00 ` Heiko Stuebner 2016-02-18 1:43 ` Jianqun Xu 2016-02-17 11:27 ` Marc Zyngier 2016-02-17 11:46 ` Mark Rutland 2 siblings, 1 reply; 24+ messages in thread From: Heiko Stuebner @ 2016-02-17 7:00 UTC (permalink / raw) To: jianqun.xu Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree Hi Jianqun, Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: > From: Xu Jianqun <jay.xu@rock-chips.com> > > Add dtsi file for Rockchip rk3399 SoCs, which includes some > general nodes such as cpu, pmu, cru, gic, amba and so on. > > Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c please remove any review-cruft like Change-Ids from mainline patches :-) > Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 > +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644 > index 0000000..eb671f6 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -0,0 +1,989 @@ > +/* > + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > +#include <dt-bindings/clock/rk3399-cru.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/pinctrl/rockchip.h> > + > +/ { > + compatible = "rockchip,rk3399"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + }; > + > + psci { > + compatible = "arm,psci"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu_l0>; > + }; > + core1 { > + cpu = <&cpu_l1>; > + }; > + core2 { > + cpu = <&cpu_l2>; > + }; > + core3 { > + cpu = <&cpu_l3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu_b0>; > + }; > + core1 { > + cpu = <&cpu_b1>; > + }; > + }; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + cpu_sleep: cpu-sleep-0 { > + compatible = "arm,idle-state"; > + }; > + }; why the essentially empty idle-states, which is probably missing properties? In the absence of a real idle driver the kernel will fall back to arch_cpu_idle(), which already does WFI handling even on arm64. > + > + cpu_l0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x0>; > + cpu-idle-states = <&cpu_sleep>; that won't compile, as the referenced node is not present > + enable-method = "psci"; > + }; > + > + cpu_l1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x1>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + > + cpu_l2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x2>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + > + cpu_l3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x3>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + > + cpu_b0: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x0 0x100>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + > + cpu_b1: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x0 0x101>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, > + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = > + <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, shouldn't that be GIC_CPU_MASK_SIMPLE(6) instead of 4? > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + clock-frequency = <24000000>; > + }; > + > + xin24m: xin24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + }; > + > + gic: interrupt-controller@fee00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + > + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ > + <0x0 0xfef00000 0 0xc0000>, /* GICR */ > + <0x0 0xfff00000 0 0x10000>, /* GICC */ > + <0x0 0xfff10000 0 0x10000>, /* GICH */ > + <0x0 0xfff20000 0 0x10000>; /* GICV */ > + interrupts = > + <GIC_PPI 9 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; again GIC_CPU_MASK_SIMPLE(6)? > + its: interrupt-controller@fee20000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0xfee20000 0x0 0x20000>; > + }; > + }; > + > + amba { > + compatible = "arm,amba-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + dmac_bus: dma-controller@ff6d0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x0 0xff6d0000 0x0 0x4000>; > + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + clocks = <&cru ACLK_DMAC_BUS>; > + clock-names = "apb_pclk"; has the FLUSHP bug gotten fixed? That would be cool. > + }; rest looks nice on first glance :-) Heiko ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 2016-02-17 7:00 ` Heiko Stuebner @ 2016-02-18 1:43 ` Jianqun Xu 0 siblings, 0 replies; 24+ messages in thread From: Jianqun Xu @ 2016-02-18 1:43 UTC (permalink / raw) To: Heiko Stuebner Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree 在 17/02/2016 15:00, Heiko Stuebner 写道: > Hi Jianqun, > > Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: >> From: Xu Jianqun <jay.xu@rock-chips.com> >> >> Add dtsi file for Rockchip rk3399 SoCs, which includes some >> general nodes such as cpu, pmu, cru, gic, amba and so on. >> >> Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c > > please remove any review-cruft like Change-Ids from mainline patches :-) ok, will fix it in next version patch > >> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> >> --- >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 >> +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+) >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644 >> index 0000000..eb671f6 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> @@ -0,0 +1,989 @@ >> +/* >> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> +#include <dt-bindings/clock/rk3399-cru.h> >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/pinctrl/rockchip.h> >> + >> +/ { >> + compatible = "rockchip,rk3399"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + serial3 = &uart3; >> + }; >> + >> + psci { >> + compatible = "arm,psci"; >> + method = "smc"; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu_l0>; >> + }; >> + core1 { >> + cpu = <&cpu_l1>; >> + }; >> + core2 { >> + cpu = <&cpu_l2>; >> + }; >> + core3 { >> + cpu = <&cpu_l3>; >> + }; >> + }; >> + >> + cluster1 { >> + core0 { >> + cpu = <&cpu_b0>; >> + }; >> + core1 { >> + cpu = <&cpu_b1>; >> + }; >> + }; >> + }; >> + >> + idle-states { >> + entry-method = "psci"; >> + >> + cpu_sleep: cpu-sleep-0 { >> + compatible = "arm,idle-state"; >> + }; >> + }; > > why the essentially empty idle-states, which is probably missing properties? > In the absence of a real idle driver the kernel will fall back to > arch_cpu_idle(), which already does WFI handling even on arm64. > the idle node will be added by my colleague with new patch later, so I will remove it first in next version patch. > >> + >> + cpu_l0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x0>; >> + cpu-idle-states = <&cpu_sleep>; > > that won't compile, as the referenced node is not present > > >> + enable-method = "psci"; >> + }; >> + >> + cpu_l1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x1>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_l2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x2>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_l3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x3>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_b0: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72", "arm,armv8"; >> + reg = <0x0 0x100>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + >> + cpu_b1: cpu@101 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72", "arm,armv8"; >> + reg = <0x0 0x101>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; >> + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, >> + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = >> + <GIC_PPI 13 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > > shouldn't that be GIC_CPU_MASK_SIMPLE(6) instead of 4? > ok, will fix it in next version patch > >> + <GIC_PPI 14 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + clock-frequency = <24000000>; >> + }; >> + >> + xin24m: xin24m { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <24000000>; >> + clock-output-names = "xin24m"; >> + }; >> + >> + gic: interrupt-controller@fee00000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + interrupt-controller; >> + >> + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ >> + <0x0 0xfef00000 0 0xc0000>, /* GICR */ >> + <0x0 0xfff00000 0 0x10000>, /* GICC */ >> + <0x0 0xfff10000 0 0x10000>, /* GICH */ >> + <0x0 0xfff20000 0 0x10000>; /* GICV */ >> + interrupts = >> + <GIC_PPI 9 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > again GIC_CPU_MASK_SIMPLE(6)? ok. > >> + its: interrupt-controller@fee20000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + reg = <0x0 0xfee20000 0x0 0x20000>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + dmac_bus: dma-controller@ff6d0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0xff6d0000 0x0 0x4000>; >> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >> + #dma-cells = <1>; >> + clocks = <&cru ACLK_DMAC_BUS>; >> + clock-names = "apb_pclk"; > > has the FLUSHP bug gotten fixed? That would be cool. > Since amba node is added by my colleague, I will double check it, thanks > >> + }; > > rest looks nice on first glance :-) > > > Heiko > > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 2016-02-17 2:01 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu 2016-02-17 7:00 ` Heiko Stuebner @ 2016-02-17 11:27 ` Marc Zyngier 2016-02-17 11:46 ` Mark Rutland 2 siblings, 0 replies; 24+ messages in thread From: Marc Zyngier @ 2016-02-17 11:27 UTC (permalink / raw) To: jianqun.xu, heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, devicetree, linux-kernel, linux-rockchip, linux-arm-kernel Hi Xu, On 17/02/16 02:01, jianqun.xu wrote: > From: Xu Jianqun <jay.xu@rock-chips.com> > > Add dtsi file for Rockchip rk3399 SoCs, which includes some > general nodes such as cpu, pmu, cru, gic, amba and so on. > > Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c > Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 +++++++++++++++++++++++++++++++ > 1 file changed, 989 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > new file mode 100644 > index 0000000..eb671f6 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = > + <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; Please drop these GIC_CPU_MASK_SIMPLE from the interrupt specifiers, they do not mean anything with GICv3. > + clock-frequency = <24000000>; Are you sure you do need this? Can't your firmware be fixed to correctly program CNTFRQ_EL0? > + }; > + > + xin24m: xin24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + }; > + > + gic: interrupt-controller@fee00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + > + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ > + <0x0 0xfef00000 0 0xc0000>, /* GICR */ > + <0x0 0xfff00000 0 0x10000>, /* GICC */ > + <0x0 0xfff10000 0 0x10000>, /* GICH */ > + <0x0 0xfff20000 0 0x10000>; /* GICV */ > + interrupts = > + <GIC_PPI 9 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; Same remark about the mask. > + its: interrupt-controller@fee20000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0xfee20000 0x0 0x20000>; > + }; Looks nice. Is there any peripheral capable of generating MSIs on this SoC? Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 2016-02-17 2:01 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu 2016-02-17 7:00 ` Heiko Stuebner 2016-02-17 11:27 ` Marc Zyngier @ 2016-02-17 11:46 ` Mark Rutland 2016-02-18 1:07 ` Jianqun Xu 2 siblings, 1 reply; 24+ messages in thread From: Mark Rutland @ 2016-02-17 11:46 UTC (permalink / raw) To: jianqun.xu Cc: heiko, robh+dt, pawel.moll, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree On Wed, Feb 17, 2016 at 10:01:16AM +0800, jianqun.xu wrote: > From: Xu Jianqun <jay.xu@rock-chips.com> > > Add dtsi file for Rockchip rk3399 SoCs, which includes some > general nodes such as cpu, pmu, cru, gic, amba and so on. > > Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c This is meaningless upstream. Please remove any "Change-Id" lines from upstream commit messages. > Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 +++++++++++++++++++++++++++++++ > 1 file changed, 989 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > new file mode 100644 > index 0000000..eb671f6 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -0,0 +1,989 @@ > +/* > + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > +#include <dt-bindings/clock/rk3399-cru.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/pinctrl/rockchip.h> > + > +/ { > + compatible = "rockchip,rk3399"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + }; > + > + psci { > + compatible = "arm,psci"; > + method = "smc"; > + }; That compatible string alone is insufficient, as it implies no particular function IDs. Hotplug and idle cannot possibly work. Have you tested this DT? Which PSCI version have you implemented? Are you using a standard firmware (e.g. ARM Trusted Firmware), or some custom implementation? > + cpu_l0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x0>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + cpu_b0: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x0 0x100>; > + cpu-idle-states = <&cpu_sleep>; > + enable-method = "psci"; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; > + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, > + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>; > + }; > + This isn't quite right. We should have separate nodes for the A72 and A53 PMUs. We can't describe that just yet due to needing cluster-local PPIs. I believe Will was looking into that. In the mean time, please drop the PMU node. > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = > + <GIC_PPI 13 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 14 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 11 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + <GIC_PPI 10 > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + clock-frequency = <24000000>; > + }; Please fix your firmware to program CNTFRQ. Using clock-frequency is really not sufficient, and new platforms have no excuse for not having it programmed correctly. Thanks, Mark. ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 2016-02-17 11:46 ` Mark Rutland @ 2016-02-18 1:07 ` Jianqun Xu 0 siblings, 0 replies; 24+ messages in thread From: Jianqun Xu @ 2016-02-18 1:07 UTC (permalink / raw) To: Mark Rutland Cc: heiko, robh+dt, pawel.moll, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons, huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree Hi Mark 在 17/02/2016 19:46, Mark Rutland 写道: > On Wed, Feb 17, 2016 at 10:01:16AM +0800, jianqun.xu wrote: >> From: Xu Jianqun <jay.xu@rock-chips.com> >> >> Add dtsi file for Rockchip rk3399 SoCs, which includes some >> general nodes such as cpu, pmu, cru, gic, amba and so on. >> >> Change-Id: Ie3b824e8ead967d4cb119d73222b7a198478c29c > > This is meaningless upstream. Please remove any "Change-Id" lines from > upstream commit messages. ok, next version will remove them. thanks > >> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> >> --- >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 +++++++++++++++++++++++++++++++ >> 1 file changed, 989 insertions(+) >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> new file mode 100644 >> index 0000000..eb671f6 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> @@ -0,0 +1,989 @@ >> +/* >> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> +#include <dt-bindings/clock/rk3399-cru.h> >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/pinctrl/rockchip.h> >> + >> +/ { >> + compatible = "rockchip,rk3399"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + serial3 = &uart3; >> + }; >> + >> + psci { >> + compatible = "arm,psci"; >> + method = "smc"; >> + }; > > That compatible string alone is insufficient, as it implies no > particular function IDs. Hotplug and idle cannot possibly work. > > Have you tested this DT? Yes, but only the simple system now, more function IDs will be added later. > > Which PSCI version have you implemented? Are you using a standard > firmware (e.g. ARM Trusted Firmware), or some custom implementation? > >> + cpu_l0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x0>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; > >> + cpu_b0: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a72", "arm,armv8"; >> + reg = <0x0 0x100>; >> + cpu-idle-states = <&cpu_sleep>; >> + enable-method = "psci"; >> + }; >> + > >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; >> + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, >> + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>; >> + }; >> + > > This isn't quite right. We should have separate nodes for the A72 and > A53 PMUs. > > We can't describe that just yet due to needing cluster-local PPIs. I > believe Will was looking into that. > > In the mean time, please drop the PMU node. ok, next version will drop the pmu node first, someone will add them in another patch. > >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = >> + <GIC_PPI 13 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 >> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + clock-frequency = <24000000>; >> + }; > > Please fix your firmware to program CNTFRQ. Using clock-frequency is > really not sufficient, and new platforms have no excuse for not having > it programmed correctly. ok, I will fix it. thanks > > Thanks, > Mark. > > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/6] clk: rockchip: add dt-binding header for rk3399 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu ` (5 preceding siblings ...) 2016-02-17 2:01 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu @ 2016-02-17 2:04 ` jianqun.xu 6 siblings, 0 replies; 24+ messages in thread From: jianqun.xu @ 2016-02-17 2:04 UTC (permalink / raw) To: heiko, robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, jwerner, broonie, catalin.marinas, will.deacon, sboyd, linus.walleij, sjoerd.simons Cc: huangtao, linux-rockchip, linux-kernel, linux-arm-kernel, devicetree, Xing Zheng From: Xing Zheng <zhengxing@rock-chips.com> Add the dt-bindings header for the rk3399, that gets shared between the clock controller and the clock references in the dts. Change-Id: I01830a46b679f4630506e8cb48b1a39e113a9952 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- include/dt-bindings/clock/rk3399-cru.h | 610 +++++++++++++++++++++++++++++++++ 1 file changed, 610 insertions(+) create mode 100644 include/dt-bindings/clock/rk3399-cru.h diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 0000000..42a1618 --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,610 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define PLL_PPLL 8 +#define ARMCLKL 9 +#define ARMCLKB 10 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 68 +#define SCLK_SPI3 69 +#define SCLK_SPI4 70 +#define SCLK_SPI5 71 +#define SCLK_SDMMC 72 +#define SCLK_SDIO0 73 +#define SCLK_EMMC 74 +#define SCLK_TSADC 75 +#define SCLK_SARADC 76 +#define SCLK_NANDC0 77 +#define SCLK_UART0 78 +#define SCLK_UART1 79 +#define SCLK_UART2 80 +#define SCLK_UART3 81 +#define SCLK_UART4 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S0_8CH 84 +#define SCLK_I2S1_8CH 85 +#define SCLK_I2S2_8CH 86 +#define SCLK_TIMER00 87 +#define SCLK_TIMER01 88 +#define SCLK_TIMER02 89 +#define SCLK_TIMER03 90 +#define SCLK_TIMER04 91 +#define SCLK_TIMER05 92 +#define SCLK_TIMER06 93 +#define SCLK_TIMER07 94 +#define SCLK_TIMER08 95 +#define SCLK_TIMER09 96 +#define SCLK_TIMER10 97 +#define SCLK_TIMER11 98 +#define SCLK_HSICPHY480M 99 +#define SCLK_HSICPHY12M 100 +#define SCLK_MACREF 101 +#define SCLK_VOPB_PWM 102 +#define SCLK_VOPL_PWM 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE_L 123 +#define SCLK_PVTM_CORE_B 124 +#define SCLK_PVTM_GPU 125 +#define SCLK_PVTM_PMU 126 +#define SCLK_SFC 127 +#define SCLK_MAC_RX 128 +#define SCLK_MAC_TX 129 +#define SCLK_MAC 130 +#define SCLK_MACREF_OUT 131 +#define SCLK_USB2_PHY0_REF 132 +#define SCLK_USB2_PHY1_REF 133 +#define SCLK_USB3_OTG0_REF 134 +#define SCLK_USB3_OTG1_REF 135 +#define SCLK_USB3_OTG0_SUSPEND 136 +#define SCLK_USB3_OTG1_SUSPEND 137 +#define SCLK_CRYPTO 138 +#define SCLK_CRYPTO1 139 + +#define DCLK_VOPB 170 +#define DCLK_VOPL 171 +#define MCLK_CRYPTO 172 +#define MCLK_CRYPTO1 173 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOPB 198 +#define ACLK_VOPL 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 +#define ACLK_EMMC_GPLL 211 +#define ACLK_EMMC_CPLL 212 +#define ACLK_EMMC_CORE 213 +#define ACLK_EMMC_NIU 214 +#define ACLK_EMMC_GRF 215 +#define ACLK_USB3_OTG0 216 +#define ACLK_USB3_OTG1 217 +#define ACLK_USB3_GRF 218 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GPIO4 324 +#define PCLK_PMUGRF 325 +#define PCLK_MAILBOX 326 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_SPI3 341 +#define PCLK_SPI4 342 +#define PCLK_SPI5 343 +#define PCLK_UART0 344 +#define PCLK_UART1 345 +#define PCLK_UART2 346 +#define PCLK_UART3 347 +#define PCLK_UART4 348 +#define PCLK_TSADC 349 +#define PCLK_SARADC 350 +#define PCLK_SIM 351 +#define PCLK_GMAC 352 +#define PCLK_PWM0 353 +#define PCLK_PWM1 354 +#define PCLK_TIMER0 355 +#define PCLK_TIMER1 356 +#define PCLK_EDP_CTRL 357 +#define PCLK_MIPI_DSI0 358 +#define PCLK_MIPI_CSI 359 +#define PCLK_HDCP 360 +#define PCLK_HDMI_CTRL 361 +#define PCLK_VIO_H2P 362 +#define PCLK_BUS 363 +#define PCLK_PERI 364 +#define PCLK_DDRUPCTL 365 +#define PCLK_DDRPHY 366 +#define PCLK_ISP 367 +#define PCLK_VIP 368 +#define PCLK_WDT 369 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S0_8CH 462 +#define HCLK_I2S1_8CH 463 +#define HCLK_I2S2_8CH 464 +#define HCLK_SPDIF 465 +#define HCLK_VOPB 466 +#define HCLK_VOPL 467 +#define HCLK_ROM 468 +#define HCLK_IEP 469 +#define HCLK_ISP 470 +#define HCLK_RGA 471 +#define HCLK_VIO_AHB_ARBI 472 +#define HCLK_VIO_NOC 473 +#define HCLK_VIP 474 +#define HCLK_VIO_H2P 475 +#define HCLK_VIO_HDCPMMU 476 +#define HCLK_VIDEO 477 +#define HCLK_BUS 478 +#define HCLK_PERI 479 + +/* pmu-clocks indices */ +#define SCLK_CM0S 500 +#define SCLK_SPI5 501 +#define SCLK_TIMER12 502 +#define SCLK_TIMER13 503 +#define SCLK_UART 504 + +#define CLK_NR_CLKS (SCLK_UART + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NIU 9 +#define SRST_A_CCIM1_NIU 10 +#define SRST_DBG_NIU 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2_CORE_L 24 +#define SRST_A_ADB400_CORE_L_GIC2 25 +#define SRST_P_DBG_L 26 +#define SRST_SOC_DBG_L 27 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKREF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2_CORE_B 40 +#define SRST_A_ADB400_CORE_B_GIC2 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_SOC_DBG_B 44 +#define SRST_ADB_B_T 45 +#define SRST_A_RKREF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NIU_T 51 +#define SRST_A_CCIM1_NIU_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NIU_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NIU 64 +#define SRST_A_CENTER_PERI_NIU 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMAON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NIU 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NIU 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NIU 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NIU 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NIU 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NIU 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NIU 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NIU 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NIU 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 +#define SRST_EMMCPHY_SYSRX 111 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NIU 112 +#define SRST_A_PERIHP_GRF 113 +#define SRST_H_PERIHP_NIU 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOSTC0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOSTC1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NIU 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NIU 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NIU 138 +#define SRST_P_GMAC 139 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NIU 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NIU 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NIU 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NIU 188 +#define SRST_SD_NIU 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NIU 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NIU 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI3 222 +#define SRST_SPI4 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NIU 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NIU 240 +#define SRST_A_HDCP_NIU 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NIU 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NIU 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 +#define SRST_DP_VIF 255 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_SGRF 257 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NIU 262 +#define SRST_A_ISP1_NIU 263 +#define SRST_A_ISP0 264 +#define SRST_A_ISP1 265 +#define SRST_H_ISP0_NIU 266 +#define SRST_H_ISP1_NIU 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NIU 272 +#define SRST_A_VOP1_NIU 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NIU 276 +#define SRST_H_VOP1_NIU 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NIU 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NIU 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NIU 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 +#define SRST_PVTM_PMU 297 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIME5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NIU 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY1_DPTX 329 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY1_APB 331 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NIU 0 +#define SRST_P_INTMEN 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NIU 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
end of thread, other threads:[~2016-02-19 1:05 UTC | newest] Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-02-17 1:53 [PATCH 0/6] Add core dtsi for rk3399 from Rockchip jianqun.xu 2016-02-17 1:53 ` [PATCH 1/6] clk: rockchip: add dt-binding header for rk3399 jianqun.xu 2016-02-17 1:53 ` [PATCH 2/6] spi: rockchip: add bindings for rk3399 spi jianqun.xu 2016-02-18 14:37 ` Rob Herring 2016-02-17 1:53 ` [PATCH 3/6] ASoC: rockchip: add bindings for rk3399 i2s jianqun.xu 2016-02-17 11:03 ` Mark Brown 2016-02-18 14:37 ` Rob Herring 2016-02-18 14:59 ` Mark Brown 2016-02-18 14:36 ` Rob Herring 2016-02-17 1:53 ` [PATCH 4/6] pinctrl: rockchip: add bindings for rk3399 pinctrl jianqun.xu 2016-02-17 6:47 ` Heiko Stuebner 2016-02-17 7:23 ` Jianqun Xu 2016-02-17 1:54 ` [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller jianqun.xu 2016-02-18 14:36 ` Rob Herring 2016-02-19 0:48 ` Jianqun Xu 2016-02-19 0:53 ` Heiko Stuebner 2016-02-19 1:05 ` Jianqun Xu 2016-02-17 2:01 ` [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399 jianqun.xu 2016-02-17 7:00 ` Heiko Stuebner 2016-02-18 1:43 ` Jianqun Xu 2016-02-17 11:27 ` Marc Zyngier 2016-02-17 11:46 ` Mark Rutland 2016-02-18 1:07 ` Jianqun Xu 2016-02-17 2:04 ` [PATCH 1/6] clk: rockchip: add dt-binding header " jianqun.xu
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