Re: [PATCH V3 3/6] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

From: Jerome Brunet <jbrunet@baylibre.com>
To: Yu Tu <yu.tu@amlogic.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH V3 3/6] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
Date: Tue, 30 Aug 2022 08:44:01 +0200	[thread overview]
Message-ID: <1jtu5uz0ry.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <0c7e6d90-2ce3-25ab-84b6-026ce8a238a8@amlogic.com>

On Tue 30 Aug 2022 at 14:13, Yu Tu <yu.tu@amlogic.com> wrote:

> On 2022/8/29 17:48, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>> On Mon 15 Aug 2022 at 21:20, Yu Tu <yu.tu@amlogic.com> wrote:
>> 
>>>>>> +
>>>>>> +static struct clk_regmap s4_hdmi_pll_dco = {
>>>>>> +    .data = &(struct meson_clk_pll_data){
>>>>>> +        .en = {
>>>>>> +            .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>>>> +            .shift   = 28,
>>>>>> +            .width   = 1,
>>>>>> +        },
>>>>>> +        .m = {
>>>>>> +            .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>>>> +            .shift   = 0,
>>>>>> +            .width   = 8,
>>>>>> +        },
>>>>>> +        .n = {
>>>>>> +            .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>>>> +            .shift   = 10,
>>>>>> +            .width   = 5,
>>>>>> +        },
>>>>>> +        .frac = {
>>>>>> +            .reg_off = ANACTRL_HDMIPLL_CTRL1,
>>>>>> +            .shift   = 0,
>>>>>> +            .width   = 17,
>>>>>> +        },
>>>>>> +        .l = {
>>>>>> +            .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>>>> +            .shift   = 31,
>>>>>> +            .width   = 1,
>>>>>> +        },
>>>>>> +        .rst = {
>>>>>> +            .reg_off = ANACTRL_HDMIPLL_CTRL0,
>>>>>> +            .shift   = 29,
>>>>>> +            .width   = 1,
>>>>>> +        },
>>>>>> +    },
>>>>>> +    .hw.init = &(struct clk_init_data){
>>>>>> +        .name = "hdmi_pll_dco",
>>>>>> +        .ops = &meson_clk_pll_ro_ops,
>>>>>> +        .parent_data = (const struct clk_parent_data []) {
>>>>>> +            { .fw_name = "xtal", }
>>>>>> +        },
>>>>>> +        .num_parents = 1,
>>>>>> +        /*
>>>>>> +         * Display directly handle hdmi pll registers ATM, we need
>>>>>> +         * NOCACHE to keep our view of the clock as accurate as
>>>>>> +         * possible
>>>>>> +         */
>>>>>
>>>>> Is it really ?
>>>>>
>>>>> Given that HDMI support for the s4 is there yet, the
>>>>> addresses have changes and the region is no longer a syscon, it is time
>>>>> for the HDMI driver to get fixed.
>>> The HDMI PLL is configured in the Uboot phase and does not change the
>>> frequency in the kernel phase. So we use the NOCACHE flag and
>>> "ro_ops".
>> That's no reason to put NOCACHE or ro-ops
>> If you want the frequencies to be statically assinged, the correct way
>> would be through assigned-rate in DT I guess.
>
> Okay. You're right. However, when registering with OPS, HDMI PLL will be
> reset. It takes time for PLL to stabilize the output frequency, which will
> lead to the startup screen flashing.
>
> I would like to know how to solve this problem if not using ro_ops.
>
>> 

You can add new ops or tweak the current init function.

Safest would be to do the following :
 * Check if the PLLs is already on.
 * Check if the 'pll->init_regs' matches what is already set
   - if so, you can skip the reset
   - if not, you need to reset as usual