From: Yu Tu <yu.tu@amlogic.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH V3 4/6] dt-bindings: clk: meson: add S4 SoC peripheral clock controller bindings
Date: Fri, 5 Aug 2022 17:33:03 +0800 [thread overview]
Message-ID: <4d923b9e-61d4-b4cc-906f-cb186a16e1f4@amlogic.com> (raw)
In-Reply-To: <562043e1-83d4-d4ab-2c18-20b770b02955@linaro.org>
Hi Krzysztof,
Thank you for your reply.
On 2022/8/5 17:15, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 05/08/2022 10:57, Yu Tu wrote:
>> Add peripheral clock controller compatible and dt-bindings header for
>> the of the S4 SoC.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> .../bindings/clock/amlogic,s4-clkc.yaml | 92 ++++++++++++
>> include/dt-bindings/clock/amlogic,s4-clkc.h | 131 ++++++++++++++++++
>> 2 files changed, 223 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml
>> create mode 100644 include/dt-bindings/clock/amlogic,s4-clkc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml
>> new file mode 100644
>> index 000000000000..2471276afda9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml
>
> Filename should be based on compatible, so amlogic,s4-periphs-clkc.yaml
I will correct as you suggest in the next version.
>
>> @@ -0,0 +1,92 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,s4-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic Meson S serials Peripheral Clock Controller Device Tree Bindings
>
> s/Device Tree Bindings//
what's mean?
>
>> +
>> +maintainers:
>> + - Neil Armstrong <narmstrong@baylibre.com>
>> + - Jerome Brunet <jbrunet@baylibre.com>
>> + - Yu Tu <yu.hu@amlogic.com>
>> +
>> +
>> +properties:
>> + compatible:
>> + const: amlogic,s4-periphs-clkc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: input fixed pll div2
>> + - description: input fixed pll div2p5
>> + - description: input fixed pll div3
>> + - description: input fixed pll div4
>> + - description: input fixed pll div5
>> + - description: input fixed pll div7
>> + - description: input hifi pll
>> + - description: input gp0 pll
>> + - description: input mpll0
>> + - description: input mpll1
>> + - description: input mpll2
>> + - description: input mpll3
>> + - description: input hdmi pll
>> + - description: input oscillator (usually at 24MHz)
>> +
>> + clock-names:
>> + items:
>> + - const: fclk_div2
>> + - const: fclk_div2p5
>> + - const: fclk_div3
>> + - const: fclk_div4
>> + - const: fclk_div5
>> + - const: fclk_div7
>> + - const: hifi_pll
>> + - const: gp0_pll
>> + - const: mpll0
>> + - const: mpll1
>> + - const: mpll2
>> + - const: mpll3
>> + - const: hdmi_pll
>> + - const: xtal
>> +
>> + "#clock-cells":
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - "#clock-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + clkc_periphs: periphs-clock-controller@fe000000 {
>> + compatible = "amlogic,s4-periphs-clkc";
>> + reg = <0xfe000000 0x49c>;
>> + clocks = <&clkc_pll 3>,
>> + <&clkc_pll 13>,
>> + <&clkc_pll 5>,
>> + <&clkc_pll 7>,
>> + <&clkc_pll 9>,
>> + <&clkc_pll 11>,
>> + <&clkc_pll 17>,
>> + <&clkc_pll 15>,
>> + <&clkc_pll 25>,
>> + <&clkc_pll 27>,
>> + <&clkc_pll 29>,
>> + <&clkc_pll 31>,
>> + <&clkc_pll 20>,
>> + <&xtal>;
>> + clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
>> + "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
>> + "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";
>> + #clock-cells = <1>;
>> + };
>> +...
>> diff --git a/include/dt-bindings/clock/amlogic,s4-clkc.h b/include/dt-bindings/clock/amlogic,s4-clkc.h
>> new file mode 100644
>> index 000000000000..d203b9bbf29e
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,s4-clkc.h
>
> Probably this should be then amlogic,s4-periphs-clkc.h
I will correct as you suggest in the next version.
>
>> @@ -0,0 +1,131 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
>
> Best regards,
> Krzysztof
>
> .
next prev parent reply other threads:[~2022-08-05 9:33 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 8:57 [PATCH V3 0/6] Add S4 SoC PLL and Peripheral clock controller Yu Tu
2022-08-05 8:57 ` [PATCH V3 1/6] dt-bindings: clock: meson: add S4 SoC PLL clock controller bindings Yu Tu
2022-08-05 9:13 ` Krzysztof Kozlowski
2022-08-05 8:57 ` [PATCH V3 2/6] arm64: dts: meson: add S4 Soc PLL clock controller in DT Yu Tu
2022-08-05 9:16 ` Krzysztof Kozlowski
2022-08-05 9:39 ` Yu Tu
2022-08-10 13:32 ` Jerome Brunet
2022-08-15 6:17 ` Yu Tu
2022-08-29 9:43 ` Jerome Brunet
2022-08-30 6:05 ` Yu Tu
2022-08-30 6:36 ` Jerome Brunet
2022-08-30 7:06 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 3/6] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2022-08-10 13:47 ` Jerome Brunet
2022-08-15 6:34 ` Yu Tu
2022-08-15 13:20 ` Yu Tu
2022-08-29 9:48 ` Jerome Brunet
2022-08-30 6:13 ` Yu Tu
2022-08-30 6:44 ` Jerome Brunet
2022-08-30 7:37 ` Yu Tu
2022-09-21 8:40 ` Yu Tu
2022-09-28 15:27 ` Jerome Brunet
2022-09-29 7:07 ` Yu Tu
2022-10-22 12:22 ` Jerome Brunet
2022-10-24 11:33 ` Yu Tu
2022-08-29 9:46 ` Jerome Brunet
2022-08-30 6:08 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 4/6] dt-bindings: clk: meson: add S4 SoC peripheral clock controller bindings Yu Tu
2022-08-05 9:15 ` Krzysztof Kozlowski
2022-08-05 9:33 ` Yu Tu [this message]
2022-08-08 6:16 ` Krzysztof Kozlowski
2022-08-08 10:00 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 5/6] arm64: dts: meson: add S4 Soc Peripheral clock controller in DT Yu Tu
2022-08-05 9:16 ` Krzysztof Kozlowski
2022-08-05 9:36 ` Yu Tu
2022-08-08 6:17 ` Krzysztof Kozlowski
2022-08-08 10:02 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 6/6] clk: meson: s4: add s4 SoC peripheral clock controller driver Yu Tu
2022-08-10 13:57 ` Jerome Brunet
2022-08-16 12:00 ` Yu Tu
2022-08-29 12:19 ` Jerome Brunet
2022-08-30 8:20 ` Yu Tu
2022-09-21 9:01 ` Yu Tu
2022-09-28 15:35 ` Jerome Brunet
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